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RDMA/hns: Fix incorrect symbol types
Types of some fields, variables and parameters of some functions should be unsigned. Link: https://lore.kernel.org/r/1607650657-35992-10-git-send-email-liweihang@huawei.com Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Wenpeng Liang
Jason Gunthorpe
parent
62f3b70ed6
commit
dcdc366acf
@ -60,7 +60,7 @@ static int hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev, u64 in_param,
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static int __hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
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u64 out_param, unsigned long in_modifier,
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u8 op_modifier, u16 op,
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unsigned long timeout)
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unsigned int timeout)
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{
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struct device *dev = hr_dev->dev;
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int ret;
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@ -78,7 +78,7 @@ static int __hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
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static int hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
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u64 out_param, unsigned long in_modifier,
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u8 op_modifier, u16 op, unsigned long timeout)
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u8 op_modifier, u16 op, unsigned int timeout)
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{
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int ret;
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@ -108,7 +108,7 @@ void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
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static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
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u64 out_param, unsigned long in_modifier,
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u8 op_modifier, u16 op,
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unsigned long timeout)
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unsigned int timeout)
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{
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struct hns_roce_cmdq *cmd = &hr_dev->cmd;
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struct hns_roce_cmd_context *context;
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@ -159,7 +159,7 @@ out:
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static int hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
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u64 out_param, unsigned long in_modifier,
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u8 op_modifier, u16 op, unsigned long timeout)
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u8 op_modifier, u16 op, unsigned int timeout)
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{
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int ret;
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@ -173,7 +173,7 @@ static int hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
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int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
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unsigned long in_modifier, u8 op_modifier, u16 op,
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unsigned long timeout)
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unsigned int timeout)
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{
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int ret;
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@ -141,7 +141,7 @@ enum {
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int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
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unsigned long in_modifier, u8 op_modifier, u16 op,
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unsigned long timeout);
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unsigned int timeout);
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struct hns_roce_cmd_mailbox *
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hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev);
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@ -38,19 +38,19 @@
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#define roce_raw_write(value, addr) \
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__raw_writel((__force u32)cpu_to_le32(value), (addr))
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#define roce_get_field(origin, mask, shift) \
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(((le32_to_cpu(origin)) & (mask)) >> (shift))
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#define roce_get_field(origin, mask, shift) \
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((le32_to_cpu(origin) & (mask)) >> (u32)(shift))
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#define roce_get_bit(origin, shift) \
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roce_get_field((origin), (1ul << (shift)), (shift))
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#define roce_set_field(origin, mask, shift, val) \
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do { \
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(origin) &= ~cpu_to_le32(mask); \
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(origin) |= cpu_to_le32(((u32)(val) << (shift)) & (mask)); \
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#define roce_set_field(origin, mask, shift, val) \
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do { \
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(origin) &= ~cpu_to_le32(mask); \
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(origin) |= cpu_to_le32(((u32)(val) << (u32)(shift)) & (mask)); \
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} while (0)
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#define roce_set_bit(origin, shift, val) \
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#define roce_set_bit(origin, shift, val) \
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roce_set_field((origin), (1ul << (shift)), (shift), (val))
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#define FIELD_LOC(field_type, field_h, field_l) field_type, field_h, field_l
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@ -95,8 +95,8 @@ static struct hns_roce_db_pgdir *hns_roce_alloc_db_pgdir(
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static int hns_roce_alloc_db_from_pgdir(struct hns_roce_db_pgdir *pgdir,
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struct hns_roce_db *db, int order)
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{
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int o;
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int i;
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unsigned long o;
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unsigned long i;
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for (o = order; o <= 1; ++o) {
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i = find_first_bit(pgdir->bits[o], HNS_ROCE_DB_PER_PAGE >> o);
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@ -154,8 +154,8 @@ out:
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void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db)
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{
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int o;
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int i;
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unsigned long o;
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unsigned long i;
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mutex_lock(&hr_dev->pgdir_mutex);
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@ -311,7 +311,7 @@ struct hns_roce_hem_table {
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};
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struct hns_roce_buf_region {
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int offset; /* page offset */
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u32 offset; /* page offset */
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u32 count; /* page count */
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int hopnum; /* addressing hop num */
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};
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@ -331,10 +331,10 @@ struct hns_roce_buf_attr {
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size_t size; /* region size */
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int hopnum; /* multi-hop addressing hop num */
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} region[HNS_ROCE_MAX_BT_REGION];
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int region_count; /* valid region count */
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unsigned int region_count; /* valid region count */
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unsigned int page_shift; /* buffer page shift */
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bool fixed_page; /* decide page shift is fixed-size or maximum size */
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int user_access; /* umem access flag */
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unsigned int user_access; /* umem access flag */
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bool mtt_only; /* only alloc buffer-required MTT memory */
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};
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@ -345,7 +345,7 @@ struct hns_roce_hem_cfg {
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unsigned int buf_pg_shift; /* buffer page shift */
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unsigned int buf_pg_count; /* buffer page count */
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struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
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int region_count;
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unsigned int region_count;
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};
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/* memory translate region */
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@ -393,7 +393,7 @@ struct hns_roce_wq {
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u64 *wrid; /* Work request ID */
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spinlock_t lock;
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u32 wqe_cnt; /* WQE num */
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int max_gs;
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u32 max_gs;
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int offset;
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int wqe_shift; /* WQE size */
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u32 head;
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@ -459,8 +459,8 @@ struct hns_roce_db {
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} u;
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dma_addr_t dma;
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void *virt_addr;
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int index;
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int order;
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unsigned long index;
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unsigned long order;
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};
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struct hns_roce_cq {
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@ -508,8 +508,8 @@ struct hns_roce_srq {
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u64 *wrid;
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struct hns_roce_idx_que idx_que;
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spinlock_t lock;
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int head;
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int tail;
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u16 head;
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u16 tail;
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struct mutex mutex;
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void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
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};
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@ -747,11 +747,11 @@ struct hns_roce_eq {
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int type_flag; /* Aeq:1 ceq:0 */
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int eqn;
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u32 entries;
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int log_entries;
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u32 log_entries;
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int eqe_size;
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int irq;
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int log_page_size;
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int cons_index;
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u32 cons_index;
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struct hns_roce_buf_list *buf_list;
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int over_ignore;
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int coalesce;
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@ -759,7 +759,7 @@ struct hns_roce_eq {
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int hop_num;
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struct hns_roce_mtr mtr;
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u16 eq_max_cnt;
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int eq_period;
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u32 eq_period;
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int shift;
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int event_type;
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int sub_type;
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@ -782,8 +782,8 @@ struct hns_roce_caps {
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u32 max_sq_inline;
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u32 max_rq_sg;
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u32 max_extend_sg;
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int num_qps;
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u32 reserved_qps;
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u32 num_qps;
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u32 reserved_qps;
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int num_qpc_timer;
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int num_cqc_timer;
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int num_srqs;
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@ -795,7 +795,7 @@ struct hns_roce_caps {
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u32 max_srq_desc_sz;
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int max_qp_init_rdma;
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int max_qp_dest_rdma;
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int num_cqs;
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u32 num_cqs;
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u32 max_cqes;
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u32 min_cqes;
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u32 min_wqes;
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@ -804,7 +804,7 @@ struct hns_roce_caps {
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int num_aeq_vectors;
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int num_comp_vectors;
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int num_other_vectors;
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int num_mtpts;
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u32 num_mtpts;
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u32 num_mtt_segs;
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u32 num_cqe_segs;
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u32 num_srqwqe_segs;
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@ -921,7 +921,7 @@ struct hns_roce_hw {
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int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
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u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
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u16 token, int event);
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int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
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int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned int timeout);
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int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
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int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
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const union ib_gid *gid, const struct ib_gid_attr *attr);
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@ -1096,15 +1096,16 @@ static inline struct hns_roce_qp
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return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
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}
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static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
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static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
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unsigned int offset)
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{
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return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
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(offset & ((1 << buf->trunk_shift) - 1));
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}
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static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx)
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static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
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{
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int offset = idx << buf->page_shift;
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unsigned int offset = idx << buf->page_shift;
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return buf->trunk_list[offset >> buf->trunk_shift].map +
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(offset & ((1 << buf->trunk_shift) - 1));
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@ -1179,7 +1180,7 @@ int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
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void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
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struct hns_roce_mtr *mtr);
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int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
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dma_addr_t *pages, int page_cnt);
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dma_addr_t *pages, unsigned int page_cnt);
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int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
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int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
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@ -1263,10 +1264,10 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
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int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
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int attr_mask, struct ib_udata *udata);
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void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
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void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
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void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n);
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void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n);
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bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
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void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
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void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
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void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
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bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
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struct ib_cq *ib_cq);
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enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
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void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
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@ -1296,7 +1297,7 @@ void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
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void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
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void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
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void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
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int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
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u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
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void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
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int hns_roce_init(struct hns_roce_dev *hr_dev);
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void hns_roce_exit(struct hns_roce_dev *hr_dev);
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@ -288,7 +288,7 @@ static int hns_roce_v1_post_send(struct ib_qp *ibqp,
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ret = -EINVAL;
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*bad_wr = wr;
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dev_err(dev, "inline len(1-%d)=%d, illegal",
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ctrl->msg_length,
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le32_to_cpu(ctrl->msg_length),
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hr_dev->caps.max_sq_inline);
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goto out;
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}
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@ -1639,7 +1639,7 @@ static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
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}
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static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
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unsigned long timeout)
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unsigned int timeout)
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{
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u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
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unsigned long end;
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@ -3600,10 +3600,10 @@ static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
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return 0;
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}
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static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
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static void set_eq_cons_index_v1(struct hns_roce_eq *eq, u32 req_not)
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{
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roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
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(req_not << eq->log_entries), eq->doorbell);
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(req_not << eq->log_entries), eq->doorbell);
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}
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static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
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@ -656,7 +656,7 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
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unsigned int sge_idx;
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unsigned int wqe_idx;
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void *wqe = NULL;
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int nreq;
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u32 nreq;
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int ret;
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spin_lock_irqsave(&qp->sq.lock, flags);
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@ -834,7 +834,7 @@ static void *get_srq_wqe(struct hns_roce_srq *srq, int n)
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return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
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}
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static void *get_idx_buf(struct hns_roce_idx_que *idx_que, int n)
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static void *get_idx_buf(struct hns_roce_idx_que *idx_que, unsigned int n)
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{
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return hns_roce_buf_offset(idx_que->mtr.kmem,
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n << idx_que->entry_shift);
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@ -875,12 +875,12 @@ static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
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struct hns_roce_v2_wqe_data_seg *dseg;
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struct hns_roce_v2_db srq_db;
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unsigned long flags;
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unsigned int ind;
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__le32 *srq_idx;
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int ret = 0;
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int wqe_idx;
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void *wqe;
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int nreq;
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int ind;
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int i;
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spin_lock_irqsave(&srq->lock, flags);
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@ -1125,7 +1125,7 @@ static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
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roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
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upper_32_bits(dma));
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roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
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ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
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(u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
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roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
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roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
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} else {
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@ -1133,7 +1133,7 @@ static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
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roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
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upper_32_bits(dma));
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roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
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ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
|
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(u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
|
||||
roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
|
||||
roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
|
||||
}
|
||||
@ -1919,8 +1919,8 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
|
||||
}
|
||||
}
|
||||
|
||||
static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
|
||||
int *buf_page_size, int *bt_page_size, u32 hem_type)
|
||||
static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
|
||||
u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
|
||||
{
|
||||
u64 obj_per_chunk;
|
||||
u64 bt_chunk_size = PAGE_SIZE;
|
||||
@ -2399,10 +2399,10 @@ static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
|
||||
u32 buf_chk_sz;
|
||||
dma_addr_t t;
|
||||
int func_num = 1;
|
||||
int pg_num_a;
|
||||
int pg_num_b;
|
||||
int pg_num;
|
||||
int size;
|
||||
u32 pg_num_a;
|
||||
u32 pg_num_b;
|
||||
u32 pg_num;
|
||||
u32 size;
|
||||
int i;
|
||||
|
||||
switch (type) {
|
||||
@ -2598,7 +2598,7 @@ static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev)
|
||||
struct hns_roce_cmq_desc desc;
|
||||
struct hns_roce_mbox_status *mb_st =
|
||||
(struct hns_roce_mbox_status *)desc.data;
|
||||
enum hns_roce_cmd_return_status status;
|
||||
int status;
|
||||
|
||||
hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true);
|
||||
|
||||
@ -2669,7 +2669,7 @@ static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
|
||||
}
|
||||
|
||||
static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
|
||||
unsigned long timeout)
|
||||
unsigned int timeout)
|
||||
{
|
||||
struct device *dev = hr_dev->dev;
|
||||
unsigned long end;
|
||||
@ -3067,7 +3067,7 @@ static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
|
||||
return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
|
||||
}
|
||||
|
||||
static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
|
||||
static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
|
||||
{
|
||||
struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
|
||||
|
||||
@ -3414,7 +3414,7 @@ static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
|
||||
int is_send;
|
||||
u16 wqe_ctr;
|
||||
u32 opcode;
|
||||
int qpn;
|
||||
u32 qpn;
|
||||
int ret;
|
||||
|
||||
/* Find cqe according to consumer index */
|
||||
|
||||
@ -53,7 +53,7 @@
|
||||
* GID[0][0], GID[1][0],.....GID[N - 1][0],
|
||||
* And so on
|
||||
*/
|
||||
int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
|
||||
u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
|
||||
{
|
||||
return gid_index * hr_dev->caps.num_ports + port;
|
||||
}
|
||||
|
||||
@ -510,7 +510,7 @@ int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
|
||||
ibdev_err(ibdev, "failed to map sg mtr, ret = %d.\n", ret);
|
||||
ret = 0;
|
||||
} else {
|
||||
mr->pbl_mtr.hem_cfg.buf_pg_shift = ilog2(ibmr->page_size);
|
||||
mr->pbl_mtr.hem_cfg.buf_pg_shift = (u32)ilog2(ibmr->page_size);
|
||||
ret = mr->npages;
|
||||
}
|
||||
|
||||
@ -829,12 +829,12 @@ static int mtr_get_pages(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
|
||||
}
|
||||
|
||||
int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
|
||||
dma_addr_t *pages, int page_cnt)
|
||||
dma_addr_t *pages, unsigned int page_cnt)
|
||||
{
|
||||
struct ib_device *ibdev = &hr_dev->ib_dev;
|
||||
struct hns_roce_buf_region *r;
|
||||
unsigned int i;
|
||||
int err;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Only use the first page address as root ba when hopnum is 0, this
|
||||
@ -871,13 +871,12 @@ int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
|
||||
int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr)
|
||||
{
|
||||
struct hns_roce_hem_cfg *cfg = &mtr->hem_cfg;
|
||||
int mtt_count, left;
|
||||
int start_index;
|
||||
int mtt_count;
|
||||
int total = 0;
|
||||
__le64 *mtts;
|
||||
int npage;
|
||||
u32 npage;
|
||||
u64 addr;
|
||||
int left;
|
||||
|
||||
if (!mtt_buf || mtt_max < 1)
|
||||
goto done;
|
||||
|
||||
@ -1322,22 +1322,22 @@ static inline void *get_wqe(struct hns_roce_qp *hr_qp, int offset)
|
||||
return hns_roce_buf_offset(hr_qp->mtr.kmem, offset);
|
||||
}
|
||||
|
||||
void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n)
|
||||
void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n)
|
||||
{
|
||||
return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift));
|
||||
}
|
||||
|
||||
void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n)
|
||||
void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n)
|
||||
{
|
||||
return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift));
|
||||
}
|
||||
|
||||
void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n)
|
||||
void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n)
|
||||
{
|
||||
return get_wqe(hr_qp, hr_qp->sge.offset + (n << hr_qp->sge.sge_shift));
|
||||
}
|
||||
|
||||
bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
|
||||
bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
|
||||
struct ib_cq *ib_cq)
|
||||
{
|
||||
struct hns_roce_cq *hr_cq;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user