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[MIPS] Fix 32-bit kernel by replacing 64-bit-only code.
dclz() expects its 64-bit argument being passed as a single register but on 32-bit kernels it'll actually be in a register pair. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -469,21 +469,6 @@ void bcm1480_kgdb_interrupt(struct pt_regs *regs)
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#endif /* CONFIG_KGDB */
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static inline int dclz(unsigned long long x)
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{
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int lz;
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__asm__ (
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" .set push \n"
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" .set mips64 \n"
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" dclz %0, %1 \n"
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" .set pop \n"
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: "=r" (lz)
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: "r" (x));
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return lz;
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}
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extern void bcm1480_timer_interrupt(struct pt_regs *regs);
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extern void bcm1480_mailbox_interrupt(struct pt_regs *regs);
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extern void bcm1480_kgdb_interrupt(struct pt_regs *regs);
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@ -536,9 +521,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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if (mask_h) {
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if (mask_h ^ 1)
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do_IRQ(63 - dclz(mask_h), regs);
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do_IRQ(fls64(mask_h) - 1, regs);
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else
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do_IRQ(127 - dclz(mask_l), regs);
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do_IRQ(63 + fls64(mask_l), regs);
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}
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}
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}
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@ -419,21 +419,6 @@ static void sb1250_kgdb_interrupt(struct pt_regs *regs)
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#endif /* CONFIG_KGDB */
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static inline int dclz(unsigned long long x)
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{
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int lz;
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__asm__ (
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" .set push \n"
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" .set mips64 \n"
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" dclz %0, %1 \n"
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" .set pop \n"
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: "=r" (lz)
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: "r" (x));
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return lz;
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}
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extern void sb1250_timer_interrupt(struct pt_regs *regs);
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extern void sb1250_mailbox_interrupt(struct pt_regs *regs);
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extern void sb1250_kgdb_interrupt(struct pt_regs *regs);
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@ -490,6 +475,6 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
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R_IMR_INTERRUPT_STATUS_BASE)));
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if (mask)
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do_IRQ(63 - dclz(mask), regs);
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do_IRQ(fls64(mask) - 1, regs);
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}
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}
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