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rtc: Add driver for Nuvoton ma35d1 rtc controller
The ma35d1 rtc controller provides real-time and calendar messaging capabilities. It supports programmable time tick and alarm match interrupts. The time and calendar messages are expressed in BCD format. This driver supports the built-in rtc controller of the ma35d1. It enables setting and reading the rtc time and configuring and reading the rtc alarm. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Link: https://lore.kernel.org/r/20230925070251.28-4-ychuang570808@gmail.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Jacky Huang
Alexandre Belloni
parent
3767bba698
commit
dc0684adf3
@ -1930,6 +1930,17 @@ config RTC_DRV_TI_K3
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This driver can also be built as a module, if so, the module
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will be called "rtc-ti-k3".
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config RTC_DRV_MA35D1
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tristate "Nuvoton MA35D1 RTC"
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depends on ARCH_MA35 || COMPILE_TEST
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select REGMAP_MMIO
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help
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If you say yes here you get support for the Nuvoton MA35D1
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On-Chip Real Time Clock.
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This driver can also be built as a module, if so, the module
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will be called "rtc-ma35d1".
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comment "HID Sensor RTC drivers"
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config RTC_DRV_HID_SENSOR_TIME
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@ -88,6 +88,7 @@ obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o
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obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o
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obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o
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obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o
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obj-$(CONFIG_RTC_DRV_MA35D1) += rtc-ma35d1.o
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obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o
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obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o
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obj-$(CONFIG_RTC_DRV_MAX6916) += rtc-max6916.o
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324
drivers/rtc/rtc-ma35d1.c
Normal file
324
drivers/rtc/rtc-ma35d1.c
Normal file
@ -0,0 +1,324 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* RTC driver for Nuvoton MA35D1
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*
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* Copyright (C) 2023 Nuvoton Technology Corp.
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*/
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#include <linux/bcd.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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/* MA35D1 RTC Control Registers */
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#define MA35_REG_RTC_INIT 0x00
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#define MA35_REG_RTC_SINFASTS 0x04
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#define MA35_REG_RTC_FREQADJ 0x08
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#define MA35_REG_RTC_TIME 0x0c
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#define MA35_REG_RTC_CAL 0x10
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#define MA35_REG_RTC_CLKFMT 0x14
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#define MA35_REG_RTC_WEEKDAY 0x18
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#define MA35_REG_RTC_TALM 0x1c
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#define MA35_REG_RTC_CALM 0x20
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#define MA35_REG_RTC_LEAPYEAR 0x24
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#define MA35_REG_RTC_INTEN 0x28
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#define MA35_REG_RTC_INTSTS 0x2c
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/* register MA35_REG_RTC_INIT */
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#define RTC_INIT_ACTIVE BIT(0)
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#define RTC_INIT_MAGIC_CODE 0xa5eb1357
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/* register MA35_REG_RTC_CLKFMT */
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#define RTC_CLKFMT_24HEN BIT(0)
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#define RTC_CLKFMT_DCOMPEN BIT(16)
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/* register MA35_REG_RTC_INTEN */
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#define RTC_INTEN_ALMIEN BIT(0)
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#define RTC_INTEN_UIEN BIT(1)
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#define RTC_INTEN_CLKFIEN BIT(24)
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#define RTC_INTEN_CLKSTIEN BIT(25)
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/* register MA35_REG_RTC_INTSTS */
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#define RTC_INTSTS_ALMIF BIT(0)
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#define RTC_INTSTS_UIF BIT(1)
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#define RTC_INTSTS_CLKFIF BIT(24)
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#define RTC_INTSTS_CLKSTIF BIT(25)
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#define RTC_INIT_TIMEOUT 250
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struct ma35_rtc {
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int irq_num;
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void __iomem *rtc_reg;
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struct rtc_device *rtcdev;
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};
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static u32 rtc_reg_read(struct ma35_rtc *p, u32 offset)
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{
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return __raw_readl(p->rtc_reg + offset);
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}
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static inline void rtc_reg_write(struct ma35_rtc *p, u32 offset, u32 value)
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{
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__raw_writel(value, p->rtc_reg + offset);
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}
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static irqreturn_t ma35d1_rtc_interrupt(int irq, void *data)
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{
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struct ma35_rtc *rtc = (struct ma35_rtc *)data;
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unsigned long events = 0, rtc_irq;
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rtc_irq = rtc_reg_read(rtc, MA35_REG_RTC_INTSTS);
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if (rtc_irq & RTC_INTSTS_ALMIF) {
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rtc_reg_write(rtc, MA35_REG_RTC_INTSTS, RTC_INTSTS_ALMIF);
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events |= RTC_AF | RTC_IRQF;
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}
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if (rtc_irq & RTC_INTSTS_UIF) {
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rtc_reg_write(rtc, MA35_REG_RTC_INTSTS, RTC_INTSTS_UIF);
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events |= RTC_UF | RTC_IRQF;
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}
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rtc_update_irq(rtc->rtcdev, 1, events);
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return IRQ_HANDLED;
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}
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static int ma35d1_rtc_init(struct ma35_rtc *rtc, u32 ms_timeout)
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{
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const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
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do {
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if (rtc_reg_read(rtc, MA35_REG_RTC_INIT) & RTC_INIT_ACTIVE)
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return 0;
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rtc_reg_write(rtc, MA35_REG_RTC_INIT, RTC_INIT_MAGIC_CODE);
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mdelay(1);
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} while (time_before(jiffies, timeout));
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return -ETIMEDOUT;
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}
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static int ma35d1_alarm_irq_enable(struct device *dev, u32 enabled)
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{
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struct ma35_rtc *rtc = dev_get_drvdata(dev);
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u32 reg_ien;
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reg_ien = rtc_reg_read(rtc, MA35_REG_RTC_INTEN);
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if (enabled)
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rtc_reg_write(rtc, MA35_REG_RTC_INTEN, reg_ien | RTC_INTEN_ALMIEN);
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else
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rtc_reg_write(rtc, MA35_REG_RTC_INTEN, reg_ien & ~RTC_INTEN_ALMIEN);
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return 0;
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}
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static int ma35d1_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct ma35_rtc *rtc = dev_get_drvdata(dev);
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u32 time, cal, wday;
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do {
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time = rtc_reg_read(rtc, MA35_REG_RTC_TIME);
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cal = rtc_reg_read(rtc, MA35_REG_RTC_CAL);
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wday = rtc_reg_read(rtc, MA35_REG_RTC_WEEKDAY);
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} while (time != rtc_reg_read(rtc, MA35_REG_RTC_TIME) ||
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cal != rtc_reg_read(rtc, MA35_REG_RTC_CAL));
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tm->tm_mday = bcd2bin(cal >> 0);
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tm->tm_wday = wday;
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tm->tm_mon = bcd2bin(cal >> 8);
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tm->tm_mon = tm->tm_mon - 1;
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tm->tm_year = bcd2bin(cal >> 16) + 100;
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tm->tm_sec = bcd2bin(time >> 0);
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tm->tm_min = bcd2bin(time >> 8);
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tm->tm_hour = bcd2bin(time >> 16);
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return rtc_valid_tm(tm);
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}
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static int ma35d1_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct ma35_rtc *rtc = dev_get_drvdata(dev);
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u32 val;
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val = bin2bcd(tm->tm_mday) << 0 | bin2bcd(tm->tm_mon + 1) << 8 |
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bin2bcd(tm->tm_year - 100) << 16;
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rtc_reg_write(rtc, MA35_REG_RTC_CAL, val);
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val = bin2bcd(tm->tm_sec) << 0 | bin2bcd(tm->tm_min) << 8 |
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bin2bcd(tm->tm_hour) << 16;
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rtc_reg_write(rtc, MA35_REG_RTC_TIME, val);
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val = tm->tm_wday;
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rtc_reg_write(rtc, MA35_REG_RTC_WEEKDAY, val);
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return 0;
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}
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static int ma35d1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct ma35_rtc *rtc = dev_get_drvdata(dev);
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u32 talm, calm;
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talm = rtc_reg_read(rtc, MA35_REG_RTC_TALM);
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calm = rtc_reg_read(rtc, MA35_REG_RTC_CALM);
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alrm->time.tm_mday = bcd2bin(calm >> 0);
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alrm->time.tm_mon = bcd2bin(calm >> 8);
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alrm->time.tm_mon = alrm->time.tm_mon - 1;
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alrm->time.tm_year = bcd2bin(calm >> 16) + 100;
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alrm->time.tm_sec = bcd2bin(talm >> 0);
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alrm->time.tm_min = bcd2bin(talm >> 8);
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alrm->time.tm_hour = bcd2bin(talm >> 16);
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return rtc_valid_tm(&alrm->time);
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}
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static int ma35d1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct ma35_rtc *rtc = dev_get_drvdata(dev);
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unsigned long val;
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val = bin2bcd(alrm->time.tm_mday) << 0 | bin2bcd(alrm->time.tm_mon + 1) << 8 |
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bin2bcd(alrm->time.tm_year - 100) << 16;
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rtc_reg_write(rtc, MA35_REG_RTC_CALM, val);
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val = bin2bcd(alrm->time.tm_sec) << 0 | bin2bcd(alrm->time.tm_min) << 8 |
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bin2bcd(alrm->time.tm_hour) << 16;
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rtc_reg_write(rtc, MA35_REG_RTC_TALM, val);
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ma35d1_alarm_irq_enable(dev, alrm->enabled);
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return 0;
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}
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static const struct rtc_class_ops ma35d1_rtc_ops = {
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.read_time = ma35d1_rtc_read_time,
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.set_time = ma35d1_rtc_set_time,
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.read_alarm = ma35d1_rtc_read_alarm,
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.set_alarm = ma35d1_rtc_set_alarm,
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.alarm_irq_enable = ma35d1_alarm_irq_enable,
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};
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static int ma35d1_rtc_probe(struct platform_device *pdev)
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{
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struct ma35_rtc *rtc;
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struct clk *clk;
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u32 regval;
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int ret;
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rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
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if (!rtc)
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return -ENOMEM;
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rtc->rtc_reg = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(rtc->rtc_reg))
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return PTR_ERR(rtc->rtc_reg);
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clk = of_clk_get(pdev->dev.of_node, 0);
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if (IS_ERR(clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(clk), "failed to find rtc clock\n");
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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if (!(rtc_reg_read(rtc, MA35_REG_RTC_INIT) & RTC_INIT_ACTIVE)) {
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ret = ma35d1_rtc_init(rtc, RTC_INIT_TIMEOUT);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "rtc init failed\n");
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}
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rtc->irq_num = platform_get_irq(pdev, 0);
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ret = devm_request_irq(&pdev->dev, rtc->irq_num, ma35d1_rtc_interrupt,
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IRQF_NO_SUSPEND, "ma35d1rtc", rtc);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "Failed to request rtc irq\n");
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platform_set_drvdata(pdev, rtc);
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device_init_wakeup(&pdev->dev, true);
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rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
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if (IS_ERR(rtc->rtcdev))
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return PTR_ERR(rtc->rtcdev);
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rtc->rtcdev->ops = &ma35d1_rtc_ops;
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rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000;
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rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099;
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ret = devm_rtc_register_device(rtc->rtcdev);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "Failed to register rtc device\n");
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regval = rtc_reg_read(rtc, MA35_REG_RTC_INTEN);
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regval |= RTC_INTEN_UIEN;
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rtc_reg_write(rtc, MA35_REG_RTC_INTEN, regval);
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return 0;
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}
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static int ma35d1_rtc_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct ma35_rtc *rtc = platform_get_drvdata(pdev);
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u32 regval;
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if (device_may_wakeup(&pdev->dev))
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enable_irq_wake(rtc->irq_num);
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regval = rtc_reg_read(rtc, MA35_REG_RTC_INTEN);
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regval &= ~RTC_INTEN_UIEN;
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rtc_reg_write(rtc, MA35_REG_RTC_INTEN, regval);
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return 0;
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}
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static int ma35d1_rtc_resume(struct platform_device *pdev)
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{
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struct ma35_rtc *rtc = platform_get_drvdata(pdev);
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u32 regval;
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if (device_may_wakeup(&pdev->dev))
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disable_irq_wake(rtc->irq_num);
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regval = rtc_reg_read(rtc, MA35_REG_RTC_INTEN);
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regval |= RTC_INTEN_UIEN;
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rtc_reg_write(rtc, MA35_REG_RTC_INTEN, regval);
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return 0;
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}
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static const struct of_device_id ma35d1_rtc_of_match[] = {
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{ .compatible = "nuvoton,ma35d1-rtc", },
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{},
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};
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MODULE_DEVICE_TABLE(of, ma35d1_rtc_of_match);
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static struct platform_driver ma35d1_rtc_driver = {
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.suspend = ma35d1_rtc_suspend,
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.resume = ma35d1_rtc_resume,
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.probe = ma35d1_rtc_probe,
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.driver = {
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.name = "rtc-ma35d1",
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.of_match_table = ma35d1_rtc_of_match,
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},
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};
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module_platform_driver(ma35d1_rtc_driver);
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MODULE_AUTHOR("Ming-Jen Chen <mjchen@nuvoton.com>");
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MODULE_DESCRIPTION("MA35D1 RTC driver");
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MODULE_LICENSE("GPL");
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