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dt-bindings: iommu: renesas,ipmmu-vmsa: convert to json-schema
Convert Renesas VMSA-Compatible IOMMU bindings documentation to json-schema. Note that original documentation doesn't mention renesas,ipmmu-vmsa for R-Mobile APE6. But, R-Mobile APE6 is similar to the R-Car Gen2. So, renesas,ipmmu-r8a73a4 belongs the renesas,ipmmu-vmsa section. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Rob Herring <robh@kernel.org>
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Yoshihiro Shimoda
Rob Herring
parent
e7728fcf7d
commit
dba496f361
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* Renesas VMSA-Compatible IOMMU
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The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
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It provides address translation for bus masters outside of the CPU, each
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connected to the IPMMU through a port called micro-TLB.
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Required Properties:
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- compatible: Must contain SoC-specific and generic entry below in case
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the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
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- "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
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- "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
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- "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU.
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- "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
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- "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU.
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- "renesas,ipmmu-r8a774b1" for the R8A774B1 (RZ/G2N) IPMMU.
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- "renesas,ipmmu-r8a774c0" for the R8A774C0 (RZ/G2E) IPMMU.
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- "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
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- "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
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- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
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- "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
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- "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
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- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
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- "renesas,ipmmu-r8a77965" for the R8A77965 (R-Car M3-N) IPMMU.
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- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
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- "renesas,ipmmu-r8a77980" for the R8A77980 (R-Car V3H) IPMMU.
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- "renesas,ipmmu-r8a77990" for the R8A77990 (R-Car E3) IPMMU.
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- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
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- "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
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IPMMU.
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- reg: Base address and size of the IPMMU registers.
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- interrupts: Specifiers for the MMU fault interrupts. For instances that
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support secure mode two interrupts must be specified, for non-secure and
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secure mode, in that order. For instances that don't support secure mode a
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single interrupt must be specified. Not required for cache IPMMUs.
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- #iommu-cells: Must be 1.
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Optional properties:
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- renesas,ipmmu-main: reference to the main IPMMU instance in two cells.
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The first cell is a phandle to the main IPMMU and the second cell is
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the interrupt bit number associated with the particular cache IPMMU device.
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The interrupt bit number needs to match the main IPMMU IMSSTR register.
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Only used by cache IPMMU instances.
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Each bus master connected to an IPMMU must reference the IPMMU in its device
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node with the following property:
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- iommus: A reference to the IPMMU in two cells. The first cell is a phandle
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to the IPMMU and the second cell the number of the micro-TLB that the
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device is connected to.
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Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
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ipmmu_mx: mmu@fe951000 {
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compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
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reg = <0 0xfe951000 0 0x1000>;
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interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
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<0 221 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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};
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vsp@fe928000 {
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...
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iommus = <&ipmmu_mx 13>;
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...
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};
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@ -0,0 +1,98 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas VMSA-Compatible IOMMU
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maintainers:
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- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
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description:
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The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
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It provides address translation for bus masters outside of the CPU, each
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connected to the IPMMU through a port called micro-TLB.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,ipmmu-r8a73a4 # R-Mobile APE6
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- renesas,ipmmu-r8a7743 # RZ/G1M
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- renesas,ipmmu-r8a7744 # RZ/G1N
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- renesas,ipmmu-r8a7745 # RZ/G1E
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- renesas,ipmmu-r8a7790 # R-Car H2
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- renesas,ipmmu-r8a7791 # R-Car M2-W
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- renesas,ipmmu-r8a7793 # R-Car M2-N
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- renesas,ipmmu-r8a7794 # R-Car E2
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- const: renesas,ipmmu-vmsa # R-Mobile APE6 or R-Car Gen2 or RZ/G1
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- items:
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- enum:
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- renesas,ipmmu-r8a774a1 # RZ/G2M
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- renesas,ipmmu-r8a774b1 # RZ/G2N
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- renesas,ipmmu-r8a774c0 # RZ/G2E
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- renesas,ipmmu-r8a7795 # R-Car H3
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- renesas,ipmmu-r8a7796 # R-Car M3-W
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- renesas,ipmmu-r8a77965 # R-Car M3-N
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- renesas,ipmmu-r8a77970 # R-Car V3M
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- renesas,ipmmu-r8a77980 # R-Car V3H
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- renesas,ipmmu-r8a77990 # R-Car E3
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- renesas,ipmmu-r8a77995 # R-Car D3
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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description:
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Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
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items:
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- description: non-secure mode
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- description: secure mode if supported
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'#iommu-cells':
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const: 1
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description:
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The number of the micro-TLB that the device is connected to.
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power-domains:
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maxItems: 1
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renesas,ipmmu-main:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Reference to the main IPMMU phandle plus 1 cell. The cell is
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the interrupt bit number associated with the particular cache IPMMU
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device. The interrupt bit number needs to match the main IPMMU IMSSTR
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register. Only used by cache IPMMU instances.
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required:
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- compatible
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- reg
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- '#iommu-cells'
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- power-domains
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oneOf:
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- required:
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- interrupts
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- required:
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- renesas,ipmmu-main
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7791-sysc.h>
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ipmmu_mx: iommu@fe951000 {
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compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
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reg = <0xfe951000 0x1000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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};
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