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sh_eth: Add support for r7s72100
The r7s72100 SoC includes a fast ethernet controller. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Simon Horman
David S. Miller
parent
504c8ca55c
commit
db893473d3
@ -143,6 +143,65 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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[FWALCR1] = 0x00b4,
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};
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static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
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[EDSR] = 0x0000,
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[EDMR] = 0x0400,
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[EDTRR] = 0x0408,
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[EDRRR] = 0x0410,
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[EESR] = 0x0428,
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[EESIPR] = 0x0430,
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[TDLAR] = 0x0010,
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[TDFAR] = 0x0014,
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[TDFXR] = 0x0018,
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[TDFFR] = 0x001c,
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[RDLAR] = 0x0030,
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[RDFAR] = 0x0034,
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[RDFXR] = 0x0038,
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[RDFFR] = 0x003c,
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[TRSCER] = 0x0438,
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[RMFCR] = 0x0440,
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[TFTR] = 0x0448,
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[FDR] = 0x0450,
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[RMCR] = 0x0458,
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[RPADIR] = 0x0460,
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[FCFTR] = 0x0468,
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[CSMR] = 0x04E4,
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[ECMR] = 0x0500,
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[RFLR] = 0x0508,
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[ECSR] = 0x0510,
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[ECSIPR] = 0x0518,
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[PIR] = 0x0520,
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[APR] = 0x0554,
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[MPR] = 0x0558,
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[PFTCR] = 0x055c,
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[PFRCR] = 0x0560,
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[TPAUSER] = 0x0564,
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[MAHR] = 0x05c0,
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[MALR] = 0x05c8,
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[CEFCR] = 0x0740,
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[FRECR] = 0x0748,
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[TSFRCR] = 0x0750,
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[TLFRCR] = 0x0758,
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[RFCR] = 0x0760,
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[MAFCR] = 0x0778,
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[ARSTR] = 0x0000,
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[TSU_CTRST] = 0x0004,
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[TSU_VTAG0] = 0x0058,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_ADRH0] = 0x0100,
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[TSU_ADRL0] = 0x0104,
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[TSU_ADRH31] = 0x01f8,
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[TSU_ADRL31] = 0x01fc,
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[TXNLCR0] = 0x0080,
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[TXALCR0] = 0x0084,
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[RXNLCR0] = 0x0088,
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[RXALCR0] = 0x008C,
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};
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static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0300,
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[RFLR] = 0x0308,
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@ -314,6 +373,11 @@ static bool sh_eth_is_gether(struct sh_eth_private *mdp)
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return mdp->reg_offset == sh_eth_offset_gigabit;
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}
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static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
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{
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return mdp->reg_offset == sh_eth_offset_fast_rz;
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}
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static void sh_eth_select_mii(struct net_device *ndev)
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{
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u32 value = 0x0;
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@ -697,6 +761,38 @@ static struct sh_eth_cpu_data r8a7740_data = {
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.shift_rd0 = 1,
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};
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/* R7S72100 */
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static struct sh_eth_cpu_data r7s72100_data = {
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.chip_reset = sh_eth_chip_reset,
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.set_duplex = sh_eth_set_duplex,
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.register_type = SH_ETH_REG_FAST_RZ,
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.ecsr_value = ECSR_ICD,
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.ecsipr_value = ECSIPR_ICDIP,
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.eesipr_value = 0xff7f009f,
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
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EESR_TDE | EESR_ECI,
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.fdr_value = 0x0000070f,
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.rmcr_value = RMCR_RNC,
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.no_psr = 1,
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.apr = 1,
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.mpr = 1,
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.tpauser = 1,
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.hw_swap = 1,
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.rpadir = 1,
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.rpadir_value = 2 << 16,
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.no_trimd = 1,
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.no_ade = 1,
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.hw_crc = 1,
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.tsu = 1,
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.shift_rd0 = 1,
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};
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static struct sh_eth_cpu_data sh7619_data = {
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.register_type = SH_ETH_REG_FAST_SH3_SH2,
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@ -763,7 +859,7 @@ static int sh_eth_reset(struct net_device *ndev)
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struct sh_eth_private *mdp = netdev_priv(ndev);
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int ret = 0;
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if (sh_eth_is_gether(mdp)) {
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if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
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sh_eth_write(ndev, EDSR_ENALL, EDSR);
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sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
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EDMR);
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@ -874,7 +970,7 @@ static void read_mac_address(struct net_device *ndev, unsigned char *mac)
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static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
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{
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if (sh_eth_is_gether(mdp))
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if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
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return EDTRR_TRNS_GETHER;
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else
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return EDTRR_TRNS_ETHER;
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@ -1037,7 +1133,8 @@ static void sh_eth_ring_format(struct net_device *ndev)
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/* Rx descriptor address set */
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if (i == 0) {
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sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
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if (sh_eth_is_gether(mdp))
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if (sh_eth_is_gether(mdp) ||
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sh_eth_is_rz_fast_ether(mdp))
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sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
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}
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}
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@ -1058,7 +1155,8 @@ static void sh_eth_ring_format(struct net_device *ndev)
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if (i == 0) {
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/* Tx descriptor address set */
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sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
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if (sh_eth_is_gether(mdp))
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if (sh_eth_is_gether(mdp) ||
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sh_eth_is_rz_fast_ether(mdp))
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sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
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}
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}
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@ -1305,9 +1403,9 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
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/* In case of almost all GETHER/ETHERs, the Receive Frame State
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* (RFS) bits in the Receive Descriptor 0 are from bit 9 to
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* bit 0. However, in case of the R8A7740's GETHER, the RFS
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* bits are from bit 25 to bit 16. So, the driver needs right
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* shifting by 16.
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* bit 0. However, in case of the R8A7740, R8A779x, and
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* R7S72100 the RFS bits are from bit 25 to bit 16. So, the
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* driver needs right shifting by 16.
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*/
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if (mdp->cd->shift_rd0)
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desc_status >>= 16;
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@ -2057,6 +2155,9 @@ static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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if (sh_eth_is_rz_fast_ether(mdp))
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return &ndev->stats;
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pm_runtime_get_sync(&mdp->pdev->dev);
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ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
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@ -2438,6 +2539,11 @@ static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
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/* SuperH's TSU register init function */
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static void sh_eth_tsu_init(struct sh_eth_private *mdp)
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{
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if (sh_eth_is_rz_fast_ether(mdp)) {
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sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
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return;
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}
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sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
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sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
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sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
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@ -2557,6 +2663,9 @@ static const u16 *sh_eth_get_register_offset(int register_type)
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case SH_ETH_REG_GIGABIT:
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reg_offset = sh_eth_offset_gigabit;
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break;
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case SH_ETH_REG_FAST_RZ:
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reg_offset = sh_eth_offset_fast_rz;
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break;
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case SH_ETH_REG_FAST_RCAR:
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reg_offset = sh_eth_offset_fast_rcar;
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break;
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@ -2795,6 +2904,7 @@ static struct platform_device_id sh_eth_id_table[] = {
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{ "sh7757-ether", (kernel_ulong_t)&sh7757_data },
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{ "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
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{ "sh7763-gether", (kernel_ulong_t)&sh7763_data },
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{ "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
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{ "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
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{ "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
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{ "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
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@ -155,6 +155,7 @@ enum {
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enum {
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SH_ETH_REG_GIGABIT,
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SH_ETH_REG_FAST_RZ,
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SH_ETH_REG_FAST_RCAR,
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SH_ETH_REG_FAST_SH4,
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SH_ETH_REG_FAST_SH3_SH2
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@ -169,7 +170,7 @@ enum {
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/* Register's bits
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*/
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/* EDSR : sh7734, sh7757, sh7763, and r8a7740 only */
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/* EDSR : sh7734, sh7757, sh7763, r8a7740, and r7s72100 only */
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enum EDSR_BIT {
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EDSR_ENT = 0x01, EDSR_ENR = 0x02,
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};
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