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pinctrl: meson: get rid of unneeded domain structures
The driver originally supported more domains (register ranges) per
pinctrl device, but since commit 9dab1868ec ("pinctrl: amlogic: Make
driver independent from two-domain configuration") each device gets
assigned a single domain and we instantiate multiple pinctrl devices
in the DT.
Therefore, now the 'meson_domain' and 'meson_domain_data' structures
don't have any reason to exist and can be removed to make the model
simpler to understand. This commit doesn't change behavior.
Tested on a Odroid-C2.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Beniamino Galvani
Linus Walleij
parent
1e23437563
commit
db80f0e158
@ -556,38 +556,28 @@ static struct meson_bank meson_gxbb_aobus_banks[] = {
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BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
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};
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static struct meson_domain_data meson_gxbb_periphs_domain_data = {
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.name = "periphs-banks",
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.banks = meson_gxbb_periphs_banks,
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.num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks),
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.pin_base = 14,
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.num_pins = 120,
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};
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static struct meson_domain_data meson_gxbb_aobus_domain_data = {
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.name = "aobus-banks",
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.banks = meson_gxbb_aobus_banks,
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.num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
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.pin_base = 0,
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.num_pins = 14,
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};
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struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
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.name = "periphs-banks",
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.pin_base = 14,
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.pins = meson_gxbb_periphs_pins,
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.groups = meson_gxbb_periphs_groups,
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.funcs = meson_gxbb_periphs_functions,
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.domain_data = &meson_gxbb_periphs_domain_data,
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.banks = meson_gxbb_periphs_banks,
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.num_pins = ARRAY_SIZE(meson_gxbb_periphs_pins),
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.num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
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.num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
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.num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks),
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};
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struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
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.name = "aobus-banks",
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.pin_base = 0,
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.pins = meson_gxbb_aobus_pins,
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.groups = meson_gxbb_aobus_groups,
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.funcs = meson_gxbb_aobus_functions,
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.domain_data = &meson_gxbb_aobus_domain_data,
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.banks = meson_gxbb_aobus_banks,
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.num_pins = ARRAY_SIZE(meson_gxbb_aobus_pins),
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.num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
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.num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
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.num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
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};
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@ -21,9 +21,8 @@
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* domain which can't be powered off; the bank also uses a set of
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* registers different from the other banks.
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*
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* For each of the two power domains (regular and always-on) there are
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* 4 different register ranges that control the following properties
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* of the pins:
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* For each pin controller there are 4 different register ranges that
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* control the following properties of the pins:
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* 1) pin muxing
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* 2) pull enable/disable
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* 3) pull up/down
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@ -33,8 +32,8 @@
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* direction are the same and thus there are only 3 register ranges.
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*
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* Every pinmux group can be enabled by a specific bit in the first
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* register range of the domain; when all groups for a given pin are
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* disabled the pin acts as a GPIO.
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* register range; when all groups for a given pin are disabled the
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* pin acts as a GPIO.
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*
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* For the pull and GPIO configuration every bank uses a contiguous
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* set of bits in the register sets described above; the same register
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@ -66,21 +65,21 @@
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/**
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* meson_get_bank() - find the bank containing a given pin
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*
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* @domain: the domain containing the pin
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* @pc: the pinctrl instance
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* @pin: the pin number
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* @bank: the found bank
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*
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* Return: 0 on success, a negative value on error
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*/
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static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
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static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
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struct meson_bank **bank)
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{
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int i;
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for (i = 0; i < domain->data->num_banks; i++) {
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if (pin >= domain->data->banks[i].first &&
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pin <= domain->data->banks[i].last) {
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*bank = &domain->data->banks[i];
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for (i = 0; i < pc->data->num_banks; i++) {
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if (pin >= pc->data->banks[i].first &&
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pin <= pc->data->banks[i].last) {
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*bank = &pc->data->banks[i];
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return 0;
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}
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}
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@ -88,33 +87,6 @@ static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
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return -EINVAL;
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}
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/**
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* meson_get_domain_and_bank() - find domain and bank containing a given pin
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*
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* @pc: Meson pin controller device
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* @pin: the pin number
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* @domain: the found domain
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* @bank: the found bank
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*
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* Return: 0 on success, a negative value on error
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*/
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static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
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struct meson_domain **domain,
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struct meson_bank **bank)
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{
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struct meson_domain *d;
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d = pc->domain;
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if (pin >= d->data->pin_base &&
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pin < d->data->pin_base + d->data->num_pins) {
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*domain = d;
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return meson_get_bank(d, pin, bank);
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}
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return -EINVAL;
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}
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/**
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* meson_calc_reg_and_bit() - calculate register and bit for a pin
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*
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@ -190,7 +162,6 @@ static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
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unsigned int pin, int sel_group)
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{
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struct meson_pmx_group *group;
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struct meson_domain *domain;
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int i, j;
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for (i = 0; i < pc->data->num_groups; i++) {
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@ -201,8 +172,7 @@ static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
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for (j = 0; j < group->num_pins; j++) {
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if (group->pins[j] == pin) {
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/* We have found a group using the pin */
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domain = pc->domain;
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regmap_update_bits(domain->reg_mux,
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regmap_update_bits(pc->reg_mux,
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group->reg * 4,
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BIT(group->bit), 0);
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}
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@ -216,7 +186,6 @@ static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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struct meson_pmx_func *func = &pc->data->funcs[func_num];
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struct meson_pmx_group *group = &pc->data->groups[group_num];
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struct meson_domain *domain = pc->domain;
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int i, ret = 0;
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dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
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@ -231,7 +200,7 @@ static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
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/* Function 0 (GPIO) doesn't need any additional setting */
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if (func_num)
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ret = regmap_update_bits(domain->reg_mux, group->reg * 4,
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ret = regmap_update_bits(pc->reg_mux, group->reg * 4,
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BIT(group->bit), BIT(group->bit));
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return ret;
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@ -287,14 +256,13 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
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unsigned long *configs, unsigned num_configs)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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struct meson_domain *domain;
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struct meson_bank *bank;
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enum pin_config_param param;
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unsigned int reg, bit;
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int i, ret;
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u16 arg;
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ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
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ret = meson_get_bank(pc, pin, &bank);
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if (ret)
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return ret;
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@ -307,7 +275,7 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
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dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
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ret = regmap_update_bits(domain->reg_pull, reg,
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ret = regmap_update_bits(pc->reg_pull, reg,
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BIT(bit), 0);
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if (ret)
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return ret;
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@ -317,13 +285,13 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
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meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
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®, &bit);
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ret = regmap_update_bits(domain->reg_pullen, reg,
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ret = regmap_update_bits(pc->reg_pullen, reg,
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BIT(bit), BIT(bit));
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
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ret = regmap_update_bits(domain->reg_pull, reg,
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ret = regmap_update_bits(pc->reg_pull, reg,
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BIT(bit), BIT(bit));
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if (ret)
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return ret;
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@ -333,13 +301,13 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
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meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
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®, &bit);
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ret = regmap_update_bits(domain->reg_pullen, reg,
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ret = regmap_update_bits(pc->reg_pullen, reg,
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BIT(bit), BIT(bit));
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
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ret = regmap_update_bits(domain->reg_pull, reg,
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ret = regmap_update_bits(pc->reg_pull, reg,
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BIT(bit), 0);
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if (ret)
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return ret;
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@ -354,18 +322,17 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
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static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
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{
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struct meson_domain *domain;
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struct meson_bank *bank;
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unsigned int reg, bit, val;
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int ret, conf;
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ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
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ret = meson_get_bank(pc, pin, &bank);
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit);
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ret = regmap_read(domain->reg_pullen, reg, &val);
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ret = regmap_read(pc->reg_pullen, reg, &val);
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if (ret)
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return ret;
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@ -374,7 +341,7 @@ static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
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} else {
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
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ret = regmap_read(domain->reg_pull, reg, &val);
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ret = regmap_read(pc->reg_pull, reg, &val);
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if (ret)
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return ret;
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@ -452,82 +419,82 @@ static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
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static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
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{
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struct meson_domain *domain = gpiochip_get_data(chip);
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struct meson_pinctrl *pc = gpiochip_get_data(chip);
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pinctrl_free_gpio(domain->data->pin_base + gpio);
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pinctrl_free_gpio(pc->data->pin_base + gpio);
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}
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static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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struct meson_domain *domain = gpiochip_get_data(chip);
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struct meson_pinctrl *pc = gpiochip_get_data(chip);
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unsigned int reg, bit, pin;
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struct meson_bank *bank;
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int ret;
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pin = domain->data->pin_base + gpio;
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ret = meson_get_bank(domain, pin, &bank);
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pin = pc->data->pin_base + gpio;
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ret = meson_get_bank(pc, pin, &bank);
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
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return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit));
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return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit));
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}
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static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
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int value)
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{
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struct meson_domain *domain = gpiochip_get_data(chip);
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struct meson_pinctrl *pc = gpiochip_get_data(chip);
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unsigned int reg, bit, pin;
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struct meson_bank *bank;
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int ret;
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pin = domain->data->pin_base + gpio;
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ret = meson_get_bank(domain, pin, &bank);
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pin = pc->data->pin_base + gpio;
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ret = meson_get_bank(pc, pin, &bank);
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
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ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0);
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ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0);
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
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return regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
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return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
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value ? BIT(bit) : 0);
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}
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static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
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{
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struct meson_domain *domain = gpiochip_get_data(chip);
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struct meson_pinctrl *pc = gpiochip_get_data(chip);
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unsigned int reg, bit, pin;
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struct meson_bank *bank;
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int ret;
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pin = domain->data->pin_base + gpio;
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ret = meson_get_bank(domain, pin, &bank);
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pin = pc->data->pin_base + gpio;
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ret = meson_get_bank(pc, pin, &bank);
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if (ret)
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return;
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meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
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regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
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regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
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value ? BIT(bit) : 0);
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}
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static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
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{
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struct meson_domain *domain = gpiochip_get_data(chip);
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struct meson_pinctrl *pc = gpiochip_get_data(chip);
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unsigned int reg, bit, val, pin;
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struct meson_bank *bank;
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int ret;
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pin = domain->data->pin_base + gpio;
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ret = meson_get_bank(domain, pin, &bank);
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pin = pc->data->pin_base + gpio;
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ret = meson_get_bank(pc, pin, &bank);
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit);
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regmap_read(domain->reg_gpio, reg, &val);
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regmap_read(pc->reg_gpio, reg, &val);
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return !!(val & BIT(bit));
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}
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@ -562,35 +529,32 @@ static const struct of_device_id meson_pinctrl_dt_match[] = {
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static int meson_gpiolib_register(struct meson_pinctrl *pc)
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{
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struct meson_domain *domain;
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int ret;
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domain = pc->domain;
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pc->chip.label = pc->data->name;
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pc->chip.parent = pc->dev;
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pc->chip.request = meson_gpio_request;
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pc->chip.free = meson_gpio_free;
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pc->chip.direction_input = meson_gpio_direction_input;
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pc->chip.direction_output = meson_gpio_direction_output;
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pc->chip.get = meson_gpio_get;
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pc->chip.set = meson_gpio_set;
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pc->chip.base = pc->data->pin_base;
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pc->chip.ngpio = pc->data->num_pins;
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pc->chip.can_sleep = false;
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pc->chip.of_node = pc->of_node;
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pc->chip.of_gpio_n_cells = 2;
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domain->chip.label = domain->data->name;
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domain->chip.parent = pc->dev;
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domain->chip.request = meson_gpio_request;
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domain->chip.free = meson_gpio_free;
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domain->chip.direction_input = meson_gpio_direction_input;
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domain->chip.direction_output = meson_gpio_direction_output;
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domain->chip.get = meson_gpio_get;
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domain->chip.set = meson_gpio_set;
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domain->chip.base = domain->data->pin_base;
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domain->chip.ngpio = domain->data->num_pins;
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domain->chip.can_sleep = false;
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domain->chip.of_node = domain->of_node;
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domain->chip.of_gpio_n_cells = 2;
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ret = gpiochip_add_data(&domain->chip, domain);
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ret = gpiochip_add_data(&pc->chip, pc);
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if (ret) {
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dev_err(pc->dev, "can't add gpio chip %s\n",
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domain->data->name);
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pc->data->name);
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goto fail;
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}
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|
||||
ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
|
||||
0, domain->data->pin_base,
|
||||
domain->chip.ngpio);
|
||||
ret = gpiochip_add_pin_range(&pc->chip, dev_name(pc->dev),
|
||||
0, pc->data->pin_base,
|
||||
pc->chip.ngpio);
|
||||
if (ret) {
|
||||
dev_err(pc->dev, "can't add pin range\n");
|
||||
goto fail;
|
||||
@ -598,7 +562,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc)
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
gpiochip_remove(&pc->domain->chip);
|
||||
gpiochip_remove(&pc->chip);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -637,58 +601,46 @@ static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
|
||||
static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct meson_domain *domain;
|
||||
int num_domains = 0;
|
||||
struct device_node *np, *gpio_np = NULL;
|
||||
|
||||
for_each_child_of_node(node, np) {
|
||||
if (!of_find_property(np, "gpio-controller", NULL))
|
||||
continue;
|
||||
num_domains++;
|
||||
if (gpio_np) {
|
||||
dev_err(pc->dev, "multiple gpio nodes\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
gpio_np = np;
|
||||
}
|
||||
|
||||
if (num_domains != 1) {
|
||||
dev_err(pc->dev, "wrong number of subnodes\n");
|
||||
if (!gpio_np) {
|
||||
dev_err(pc->dev, "no gpio node found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pc->domain = devm_kzalloc(pc->dev, sizeof(struct meson_domain), GFP_KERNEL);
|
||||
if (!pc->domain)
|
||||
return -ENOMEM;
|
||||
pc->of_node = gpio_np;
|
||||
|
||||
domain = pc->domain;
|
||||
domain->data = pc->data->domain_data;
|
||||
pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
|
||||
if (IS_ERR(pc->reg_mux)) {
|
||||
dev_err(pc->dev, "mux registers not found\n");
|
||||
return PTR_ERR(pc->reg_mux);
|
||||
}
|
||||
|
||||
for_each_child_of_node(node, np) {
|
||||
if (!of_find_property(np, "gpio-controller", NULL))
|
||||
continue;
|
||||
pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
|
||||
if (IS_ERR(pc->reg_pull)) {
|
||||
dev_err(pc->dev, "pull registers not found\n");
|
||||
return PTR_ERR(pc->reg_pull);
|
||||
}
|
||||
|
||||
domain->of_node = np;
|
||||
pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
|
||||
/* Use pull region if pull-enable one is not present */
|
||||
if (IS_ERR(pc->reg_pullen))
|
||||
pc->reg_pullen = pc->reg_pull;
|
||||
|
||||
domain->reg_mux = meson_map_resource(pc, np, "mux");
|
||||
if (IS_ERR(domain->reg_mux)) {
|
||||
dev_err(pc->dev, "mux registers not found\n");
|
||||
return PTR_ERR(domain->reg_mux);
|
||||
}
|
||||
|
||||
domain->reg_pull = meson_map_resource(pc, np, "pull");
|
||||
if (IS_ERR(domain->reg_pull)) {
|
||||
dev_err(pc->dev, "pull registers not found\n");
|
||||
return PTR_ERR(domain->reg_pull);
|
||||
}
|
||||
|
||||
domain->reg_pullen = meson_map_resource(pc, np, "pull-enable");
|
||||
/* Use pull region if pull-enable one is not present */
|
||||
if (IS_ERR(domain->reg_pullen))
|
||||
domain->reg_pullen = domain->reg_pull;
|
||||
|
||||
domain->reg_gpio = meson_map_resource(pc, np, "gpio");
|
||||
if (IS_ERR(domain->reg_gpio)) {
|
||||
dev_err(pc->dev, "gpio registers not found\n");
|
||||
return PTR_ERR(domain->reg_gpio);
|
||||
}
|
||||
|
||||
break;
|
||||
pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
|
||||
if (IS_ERR(pc->reg_gpio)) {
|
||||
dev_err(pc->dev, "gpio registers not found\n");
|
||||
return PTR_ERR(pc->reg_gpio);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -95,54 +95,17 @@ struct meson_bank {
|
||||
struct meson_reg_desc regs[NUM_REG];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct meson_domain_data - domain platform data
|
||||
*
|
||||
* @name: name of the domain
|
||||
* @banks: set of banks belonging to the domain
|
||||
* @num_banks: number of banks in the domain
|
||||
*/
|
||||
struct meson_domain_data {
|
||||
const char *name;
|
||||
struct meson_bank *banks;
|
||||
unsigned int num_banks;
|
||||
unsigned int pin_base;
|
||||
unsigned int num_pins;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct meson_domain
|
||||
*
|
||||
* @reg_mux: registers for mux settings
|
||||
* @reg_pullen: registers for pull-enable settings
|
||||
* @reg_pull: registers for pull settings
|
||||
* @reg_gpio: registers for gpio settings
|
||||
* @chip: gpio chip associated with the domain
|
||||
* @data; platform data for the domain
|
||||
* @node: device tree node for the domain
|
||||
*
|
||||
* A domain represents a set of banks controlled by the same set of
|
||||
* registers.
|
||||
*/
|
||||
struct meson_domain {
|
||||
struct regmap *reg_mux;
|
||||
struct regmap *reg_pullen;
|
||||
struct regmap *reg_pull;
|
||||
struct regmap *reg_gpio;
|
||||
|
||||
struct gpio_chip chip;
|
||||
struct meson_domain_data *data;
|
||||
struct device_node *of_node;
|
||||
};
|
||||
|
||||
struct meson_pinctrl_data {
|
||||
const char *name;
|
||||
const struct pinctrl_pin_desc *pins;
|
||||
struct meson_pmx_group *groups;
|
||||
struct meson_pmx_func *funcs;
|
||||
struct meson_domain_data *domain_data;
|
||||
unsigned int pin_base;
|
||||
unsigned int num_pins;
|
||||
unsigned int num_groups;
|
||||
unsigned int num_funcs;
|
||||
struct meson_bank *banks;
|
||||
unsigned int num_banks;
|
||||
};
|
||||
|
||||
struct meson_pinctrl {
|
||||
@ -150,7 +113,12 @@ struct meson_pinctrl {
|
||||
struct pinctrl_dev *pcdev;
|
||||
struct pinctrl_desc desc;
|
||||
struct meson_pinctrl_data *data;
|
||||
struct meson_domain *domain;
|
||||
struct regmap *reg_mux;
|
||||
struct regmap *reg_pullen;
|
||||
struct regmap *reg_pull;
|
||||
struct regmap *reg_gpio;
|
||||
struct gpio_chip chip;
|
||||
struct device_node *of_node;
|
||||
};
|
||||
|
||||
#define PIN(x, b) (b + x)
|
||||
|
||||
@ -931,38 +931,28 @@ static struct meson_bank meson8_aobus_banks[] = {
|
||||
BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
|
||||
};
|
||||
|
||||
static struct meson_domain_data meson8_cbus_domain_data = {
|
||||
.name = "cbus-banks",
|
||||
.banks = meson8_cbus_banks,
|
||||
.num_banks = ARRAY_SIZE(meson8_cbus_banks),
|
||||
.pin_base = 0,
|
||||
.num_pins = 120,
|
||||
};
|
||||
|
||||
static struct meson_domain_data meson8_aobus_domain_data = {
|
||||
.name = "ao-bank",
|
||||
.banks = meson8_aobus_banks,
|
||||
.num_banks = ARRAY_SIZE(meson8_aobus_banks),
|
||||
.pin_base = 120,
|
||||
.num_pins = 16,
|
||||
};
|
||||
|
||||
struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
|
||||
.name = "cbus-banks",
|
||||
.pin_base = 0,
|
||||
.pins = meson8_cbus_pins,
|
||||
.groups = meson8_cbus_groups,
|
||||
.funcs = meson8_cbus_functions,
|
||||
.domain_data = &meson8_cbus_domain_data,
|
||||
.banks = meson8_cbus_banks,
|
||||
.num_pins = ARRAY_SIZE(meson8_cbus_pins),
|
||||
.num_groups = ARRAY_SIZE(meson8_cbus_groups),
|
||||
.num_funcs = ARRAY_SIZE(meson8_cbus_functions),
|
||||
.num_banks = ARRAY_SIZE(meson8_cbus_banks),
|
||||
};
|
||||
|
||||
struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
|
||||
.name = "ao-bank",
|
||||
.pin_base = 120,
|
||||
.pins = meson8_aobus_pins,
|
||||
.groups = meson8_aobus_groups,
|
||||
.funcs = meson8_aobus_functions,
|
||||
.domain_data = &meson8_aobus_domain_data,
|
||||
.banks = meson8_aobus_banks,
|
||||
.num_pins = ARRAY_SIZE(meson8_aobus_pins),
|
||||
.num_groups = ARRAY_SIZE(meson8_aobus_groups),
|
||||
.num_funcs = ARRAY_SIZE(meson8_aobus_functions),
|
||||
.num_banks = ARRAY_SIZE(meson8_aobus_banks),
|
||||
};
|
||||
|
||||
@ -896,38 +896,28 @@ static struct meson_bank meson8b_aobus_banks[] = {
|
||||
BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
|
||||
};
|
||||
|
||||
static struct meson_domain_data meson8b_cbus_domain_data = {
|
||||
.name = "cbus-banks",
|
||||
.banks = meson8b_cbus_banks,
|
||||
.num_banks = ARRAY_SIZE(meson8b_cbus_banks),
|
||||
.pin_base = 0,
|
||||
.num_pins = 130,
|
||||
};
|
||||
|
||||
static struct meson_domain_data meson8b_aobus_domain_data = {
|
||||
.name = "aobus-banks",
|
||||
.banks = meson8b_aobus_banks,
|
||||
.num_banks = ARRAY_SIZE(meson8b_aobus_banks),
|
||||
.pin_base = 130,
|
||||
.num_pins = 16,
|
||||
};
|
||||
|
||||
struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
|
||||
.name = "cbus-banks",
|
||||
.pin_base = 0,
|
||||
.pins = meson8b_cbus_pins,
|
||||
.groups = meson8b_cbus_groups,
|
||||
.funcs = meson8b_cbus_functions,
|
||||
.domain_data = &meson8b_cbus_domain_data,
|
||||
.banks = meson8b_cbus_banks,
|
||||
.num_pins = ARRAY_SIZE(meson8b_cbus_pins),
|
||||
.num_groups = ARRAY_SIZE(meson8b_cbus_groups),
|
||||
.num_funcs = ARRAY_SIZE(meson8b_cbus_functions),
|
||||
.num_banks = ARRAY_SIZE(meson8b_cbus_banks),
|
||||
};
|
||||
|
||||
struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
|
||||
.name = "aobus-banks",
|
||||
.pin_base = 130,
|
||||
.pins = meson8b_aobus_pins,
|
||||
.groups = meson8b_aobus_groups,
|
||||
.funcs = meson8b_aobus_functions,
|
||||
.domain_data = &meson8b_aobus_domain_data,
|
||||
.banks = meson8b_aobus_banks,
|
||||
.num_pins = ARRAY_SIZE(meson8b_aobus_pins),
|
||||
.num_groups = ARRAY_SIZE(meson8b_aobus_groups),
|
||||
.num_funcs = ARRAY_SIZE(meson8b_aobus_functions),
|
||||
.num_banks = ARRAY_SIZE(meson8b_aobus_banks),
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user