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crypto: hisilicon/zip - support zip capability
Add function 'hisi_zip_alg_support' to get device configuration information from capability registers, instead of determining whether to register an algorithm based on hardware platform's version. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Weili Qian
Herbert Xu
parent
b1be70a8c9
commit
db700974b6
@ -84,4 +84,5 @@ struct hisi_zip_sqe {
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int zip_create_qps(struct hisi_qp **qps, int qp_num, int node);
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int hisi_zip_register_to_crypto(struct hisi_qm *qm);
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void hisi_zip_unregister_from_crypto(struct hisi_qm *qm);
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bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg);
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#endif
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@ -39,6 +39,9 @@
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#define HZIP_ALG_PRIORITY 300
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#define HZIP_SGL_SGE_NR 10
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#define HZIP_ALG_ZLIB GENMASK(1, 0)
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#define HZIP_ALG_GZIP GENMASK(3, 2)
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static const u8 zlib_head[HZIP_ZLIB_HEAD_SIZE] = {0x78, 0x9c};
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static const u8 gzip_head[HZIP_GZIP_HEAD_SIZE] = {
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0x1f, 0x8b, 0x08, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x03
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@ -756,6 +759,28 @@ static struct acomp_alg hisi_zip_acomp_zlib = {
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}
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};
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static int hisi_zip_register_zlib(struct hisi_qm *qm)
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{
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int ret;
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if (!hisi_zip_alg_support(qm, HZIP_ALG_ZLIB))
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return 0;
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ret = crypto_register_acomp(&hisi_zip_acomp_zlib);
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if (ret)
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dev_err(&qm->pdev->dev, "failed to register to zlib (%d)!\n", ret);
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return ret;
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}
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static void hisi_zip_unregister_zlib(struct hisi_qm *qm)
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{
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if (!hisi_zip_alg_support(qm, HZIP_ALG_ZLIB))
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return;
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crypto_unregister_acomp(&hisi_zip_acomp_zlib);
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}
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static struct acomp_alg hisi_zip_acomp_gzip = {
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.init = hisi_zip_acomp_init,
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.exit = hisi_zip_acomp_exit,
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@ -770,27 +795,45 @@ static struct acomp_alg hisi_zip_acomp_gzip = {
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}
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};
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int hisi_zip_register_to_crypto(struct hisi_qm *qm)
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static int hisi_zip_register_gzip(struct hisi_qm *qm)
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{
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int ret;
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ret = crypto_register_acomp(&hisi_zip_acomp_zlib);
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if (ret) {
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pr_err("failed to register to zlib (%d)!\n", ret);
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if (!hisi_zip_alg_support(qm, HZIP_ALG_GZIP))
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return 0;
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ret = crypto_register_acomp(&hisi_zip_acomp_gzip);
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if (ret)
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dev_err(&qm->pdev->dev, "failed to register to gzip (%d)!\n", ret);
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return ret;
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}
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ret = crypto_register_acomp(&hisi_zip_acomp_gzip);
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if (ret) {
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pr_err("failed to register to gzip (%d)!\n", ret);
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crypto_unregister_acomp(&hisi_zip_acomp_zlib);
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static void hisi_zip_unregister_gzip(struct hisi_qm *qm)
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{
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if (!hisi_zip_alg_support(qm, HZIP_ALG_GZIP))
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return;
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crypto_unregister_acomp(&hisi_zip_acomp_gzip);
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}
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int hisi_zip_register_to_crypto(struct hisi_qm *qm)
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{
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int ret = 0;
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ret = hisi_zip_register_zlib(qm);
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if (ret)
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return ret;
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ret = hisi_zip_register_gzip(qm);
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if (ret)
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hisi_zip_unregister_zlib(qm);
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return ret;
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}
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void hisi_zip_unregister_from_crypto(struct hisi_qm *qm)
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{
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crypto_unregister_acomp(&hisi_zip_acomp_gzip);
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crypto_unregister_acomp(&hisi_zip_acomp_zlib);
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hisi_zip_unregister_zlib(qm);
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hisi_zip_unregister_gzip(qm);
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}
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@ -20,18 +20,6 @@
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#define HZIP_QUEUE_NUM_V1 4096
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#define HZIP_CLOCK_GATE_CTRL 0x301004
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#define COMP0_ENABLE BIT(0)
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#define COMP1_ENABLE BIT(1)
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#define DECOMP0_ENABLE BIT(2)
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#define DECOMP1_ENABLE BIT(3)
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#define DECOMP2_ENABLE BIT(4)
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#define DECOMP3_ENABLE BIT(5)
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#define DECOMP4_ENABLE BIT(6)
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#define DECOMP5_ENABLE BIT(7)
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#define HZIP_ALL_COMP_DECOMP_EN (COMP0_ENABLE | COMP1_ENABLE | \
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DECOMP0_ENABLE | DECOMP1_ENABLE | \
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DECOMP2_ENABLE | DECOMP3_ENABLE | \
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DECOMP4_ENABLE | DECOMP5_ENABLE)
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#define HZIP_DECOMP_CHECK_ENABLE BIT(16)
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#define HZIP_FSM_MAX_CNT 0x301008
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@ -76,10 +64,6 @@
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#define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16
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#define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24
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#define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0)
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#define HZIP_COMP_CORE_NUM 2
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#define HZIP_DECOMP_CORE_NUM 6
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#define HZIP_CORE_NUM (HZIP_COMP_CORE_NUM + \
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HZIP_DECOMP_CORE_NUM)
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#define HZIP_SQE_SIZE 128
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#define HZIP_PF_DEF_Q_NUM 64
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#define HZIP_PF_DEF_Q_BASE 0
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@ -194,6 +178,21 @@ enum zip_cap_type {
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ZIP_RESET_MASK_CAP,
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ZIP_OOO_SHUTDOWN_MASK_CAP,
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ZIP_CE_MASK_CAP,
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ZIP_CLUSTER_NUM_CAP,
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ZIP_CORE_TYPE_NUM_CAP,
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ZIP_CORE_NUM_CAP,
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ZIP_CLUSTER_COMP_NUM_CAP,
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ZIP_CLUSTER_DECOMP_NUM_CAP,
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ZIP_DECOMP_ENABLE_BITMAP,
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ZIP_COMP_ENABLE_BITMAP,
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ZIP_DRV_ALG_BITMAP,
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ZIP_DEV_ALG_BITMAP,
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ZIP_CORE1_ALG_BITMAP,
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ZIP_CORE2_ALG_BITMAP,
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ZIP_CORE3_ALG_BITMAP,
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ZIP_CORE4_ALG_BITMAP,
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ZIP_CORE5_ALG_BITMAP,
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ZIP_CAP_MAX
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};
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static struct hisi_qm_cap_info zip_basic_cap_info[] = {
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@ -205,6 +204,21 @@ static struct hisi_qm_cap_info zip_basic_cap_info[] = {
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{ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE},
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{ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE},
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{ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},
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{ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1},
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{ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2},
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{ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5},
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{ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2},
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{ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3},
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{ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C},
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{ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3},
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{ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0xF, 0xF, 0xF},
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{ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0xFF},
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{ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5},
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{ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5},
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{ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},
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{ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},
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{ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},
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{ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0}
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};
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enum {
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@ -363,6 +377,17 @@ int zip_create_qps(struct hisi_qp **qps, int qp_num, int node)
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return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps);
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}
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bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg)
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{
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u32 cap_val;
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cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver);
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if ((alg & cap_val) == alg)
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return true;
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return false;
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}
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static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm)
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{
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u32 val;
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@ -421,6 +446,7 @@ static void hisi_zip_enable_clock_gate(struct hisi_qm *qm)
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static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
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{
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void __iomem *base = qm->io_base;
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u32 dcomp_bm, comp_bm;
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/* qm user domain */
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writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
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@ -458,8 +484,11 @@ static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
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}
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/* let's open all compression/decompression cores */
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writel(HZIP_DECOMP_CHECK_ENABLE | HZIP_ALL_COMP_DECOMP_EN,
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base + HZIP_CLOCK_GATE_CTRL);
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dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
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ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver);
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comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
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ZIP_COMP_ENABLE_BITMAP, qm->cap_ver);
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writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL);
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/* enable sqc,cqc writeback */
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writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
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@ -678,18 +707,23 @@ DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs);
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static int hisi_zip_core_debug_init(struct hisi_qm *qm)
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{
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u32 zip_core_num, zip_comp_core_num;
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struct device *dev = &qm->pdev->dev;
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struct debugfs_regset32 *regset;
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struct dentry *tmp_d;
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char buf[HZIP_BUF_SIZE];
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int i;
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for (i = 0; i < HZIP_CORE_NUM; i++) {
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if (i < HZIP_COMP_CORE_NUM)
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zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver);
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zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP,
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qm->cap_ver);
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for (i = 0; i < zip_core_num; i++) {
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if (i < zip_comp_core_num)
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scnprintf(buf, sizeof(buf), "comp_core%d", i);
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else
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scnprintf(buf, sizeof(buf), "decomp_core%d",
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i - HZIP_COMP_CORE_NUM);
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i - zip_comp_core_num);
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regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
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if (!regset)
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@ -822,10 +856,13 @@ static int hisi_zip_show_last_regs_init(struct hisi_qm *qm)
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int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs);
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struct qm_debug *debug = &qm->debug;
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void __iomem *io_base;
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u32 zip_core_num;
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int i, j, idx;
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debug->last_words = kcalloc(core_dfx_regs_num * HZIP_CORE_NUM +
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com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
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zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver);
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debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num,
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sizeof(unsigned int), GFP_KERNEL);
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if (!debug->last_words)
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return -ENOMEM;
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@ -834,7 +871,7 @@ static int hisi_zip_show_last_regs_init(struct hisi_qm *qm)
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debug->last_words[i] = readl_relaxed(io_base);
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}
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for (i = 0; i < HZIP_CORE_NUM; i++) {
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for (i = 0; i < zip_core_num; i++) {
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io_base = qm->io_base + core_offsets[i];
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for (j = 0; j < core_dfx_regs_num; j++) {
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idx = com_dfx_regs_num + i * core_dfx_regs_num + j;
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@ -861,6 +898,7 @@ static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)
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{
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int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs);
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int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs);
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u32 zip_core_num, zip_comp_core_num;
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struct qm_debug *debug = &qm->debug;
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char buf[HZIP_BUF_SIZE];
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void __iomem *base;
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@ -877,12 +915,15 @@ static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)
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hzip_com_dfx_regs[i].name, debug->last_words[i], val);
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}
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for (i = 0; i < HZIP_CORE_NUM; i++) {
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if (i < HZIP_COMP_CORE_NUM)
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zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver);
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zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP,
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qm->cap_ver);
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for (i = 0; i < zip_core_num; i++) {
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if (i < zip_comp_core_num)
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scnprintf(buf, sizeof(buf), "Comp_core-%d", i);
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else
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scnprintf(buf, sizeof(buf), "Decomp_core-%d",
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i - HZIP_COMP_CORE_NUM);
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i - zip_comp_core_num);
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base = qm->io_base + core_offsets[i];
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pci_info(qm->pdev, "==>%s:\n", buf);
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@ -892,7 +933,8 @@ static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)
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val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset);
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if (debug->last_words[idx] != val)
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pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n",
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hzip_dump_dfx_regs[j].name, debug->last_words[idx], val);
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hzip_dump_dfx_regs[j].name,
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debug->last_words[idx], val);
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}
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}
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}
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