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Allwinner DT changes for 5.4

Browse Source 
Our usual pile of patches for the next release, which include mostly:
   - More fixes thanks to the DT validation using the YAML bindings
   - IR receiver support on the H6
   - SPDIF support on the H6
   - I2C Support on the H6
   - CSI support on the A20
   - RTC support on the H6
   - New Boards: Lichee Zero Plus, Tanix TX6, A64-Olinuxino-eMMC
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Merge tag 'sunxi-dt-for-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Allwinner DT changes for 5.4

Our usual pile of patches for the next release, which include mostly:
  - More fixes thanks to the DT validation using the YAML bindings
  - IR receiver support on the H6
  - SPDIF support on the H6
  - I2C Support on the H6
  - CSI support on the A20
  - RTC support on the H6
  - New Boards: Lichee Zero Plus, Tanix TX6, A64-Olinuxino-eMMC

* tag 'sunxi-dt-for-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (40 commits)
  arm64: dts: allwinner: orange-pi-3: Enable WiFi
  ARM: dts: sunxi: Add missing watchdog clocks
  ARM: dts: sunxi: Add missing watchdog interrupts
  arm64: dts: allwinner: h6: Add support for RTC and fix the clock tree
  ARM: dts: sun7i: Add CSI0 controller
  arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)
  dt-bindings: arm: sunxi: Add compatible for A64 OlinuXino with eMMC
  ARM: dts: v3s: Change the timers compatible
  ARM: dts: h3: Change the timers compatible
  ARM: dts: a83t: Change the timers compatible
  ARM: dts: a23/a33: Change the timers compatible
  ARM: dts: sun6i: Add missing timers interrupts
  ARM: dts: sun5i: Add missing timers interrupts
  ARM: dts: sun4i: Add missing timers interrupts
  dt-bindings: mfd: Convert Allwinner GPADC bindings to a schema
  arm64: dts: allwinner: h6: Introduce Tanix TX6 board
  dt-bindings: arm: sunxi: Add compatible for Tanix TX6 board
  arm64: allwinner: h6: add I2C nodes
  dt-bindings: i2c: mv64xxx: Add compatible for the H6 i2c node.
  ARM: dts: sunxi: Add mdio bus sub-node to GMAC
  ...

Link: https://lore.kernel.org/r/d97e6252-9dd7-4cf5-a3cf-56f78b0ca455.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-09-03 15:55:50 +02:00
commit db2f7fe562
73 changed files with 937 additions and 289 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@ -353,6 +353,12 @@ properties:
- const: licheepi,licheepi-zero
- const: allwinner,sun8i-v3s
- description: Lichee Zero Plus (with S3, without eMMC/SPI Flash)
items:
- const: sipeed,lichee-zero-plus
- const: sochip,s3
- const: allwinner,sun8i-v3
- description: Linksprite PCDuino
items:
- const: linksprite,a10-pcduino
@ -568,6 +574,11 @@ properties:
- const: olimex,a64-olinuxino
- const: allwinner,sun50i-a64
- description: Olimex A64-OlinuXino (with eMMC)
items:
- const: olimex,a64-olinuxino-emmc
- const: allwinner,sun50i-a64
- description: Olimex A64 Teres-I
items:
- const: olimex,a64-teres-i
@ -671,6 +682,11 @@ properties:
- const: sinlinx,sina33
- const: allwinner,sun8i-a33
- description: Tanix TX6
items:
- const: oranth,tanix-tx6
- const: allwinner,sun50i-h6
- description: TBS A711 Tablet
items:
- const: tbs-biometrics,a711

3
Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
View File

@ -26,6 +26,9 @@ properties:
- items:
- const: allwinner,sun50i-a64-i2c
- const: allwinner,sun6i-a31-i2c
- items:
- const: allwinner,sun50i-h6-i2c
- const: allwinner,sun6i-a31-i2c
- const: marvell,mv64xxx-i2c
- const: marvell,mv78230-i2c

43
Documentation/devicetree/bindings/iio/adc/allwinner,sun8i-a33-ths.yaml Normal file
View File

@ -0,0 +1,43 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/allwinner,sun8i-a33-ths.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A33 Thermal Sensor Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
"#io-channel-cells":
const: 0
"#thermal-sensor-cells":
const: 0
compatible:
const: allwinner,sun8i-a33-ths
reg:
maxItems: 1
required:
- "#io-channel-cells"
- "#thermal-sensor-cells"
- compatible
- reg
additionalProperties: false
examples:
- |
ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
#thermal-sensor-cells = <0>;
#io-channel-cells = <0>;
};
...

76
Documentation/devicetree/bindings/mfd/allwinner,sun4i-a10-ts.yaml Normal file
View File

@ -0,0 +1,76 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/allwinner,sun4i-a10-ts.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Resistive Touchscreen Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
"#thermal-sensor-cells":
const: 0
compatible:
enum:
- allwinner,sun4i-a10-ts
- allwinner,sun5i-a13-ts
- allwinner,sun6i-a31-ts
reg:
maxItems: 1
interrupts:
maxItems: 1
allwinner,ts-attached:
$ref: /schemas/types.yaml#/definitions/flag
description: A touchscreen is attached to the controller
allwinner,tp-sensitive-adjust:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
maximum: 15
default: 15
description: Sensitivity of pen down detection
allwinner,filter-type:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
maximum: 3
default: 1
description: |
Select median and averaging filter. Sample used for median /
averaging filter:
0: 4/2
1: 5/3
2: 8/4
3: 16/8
required:
- "#thermal-sensor-cells"
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
rtp: rtp@1c25000 {
compatible = "allwinner,sun4i-a10-ts";
reg = <0x01c25000 0x100>;
interrupts = <29>;
allwinner,ts-attached;
#thermal-sensor-cells = <0>;
/* sensitive/noisy touch panel */
allwinner,tp-sensitive-adjust = <0>;
allwinner,filter-type = <3>;
};
...

59
Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
View File

@ -1,59 +0,0 @@
Allwinner SoCs' GPADC Device Tree bindings
------------------------------------------
The Allwinner SoCs all have an ADC that can also act as a thermal sensor
and sometimes as a touchscreen controller.
Required properties:
- compatible: "allwinner,sun8i-a33-ths",
- reg: mmio address range of the chip,
- #thermal-sensor-cells: shall be 0,
- #io-channel-cells: shall be 0,
Example:
ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
#thermal-sensor-cells = <0>;
#io-channel-cells = <0>;
};
sun4i, sun5i and sun6i SoCs are also supported via the older binding:
sun4i resistive touchscreen controller
--------------------------------------
Required properties:
- compatible: "allwinner,sun4i-a10-ts", "allwinner,sun5i-a13-ts" or
"allwinner,sun6i-a31-ts"
- reg: mmio address range of the chip
- interrupts: interrupt to which the chip is connected
- #thermal-sensor-cells: shall be 0
Optional properties:
- allwinner,ts-attached : boolean indicating that an actual touchscreen
is attached to the controller
- allwinner,tp-sensitive-adjust : integer (4 bits)
adjust sensitivity of pen down detection
between 0 (least sensitive) and 15
(defaults to 15)
- allwinner,filter-type : integer (2 bits)
select median and averaging filter
samples used for median / averaging filter
0: 4/2
1: 5/3
2: 8/4
3: 16/8
(defaults to 1)
Example:
rtp: rtp@1c25000 {
compatible = "allwinner,sun4i-a10-ts";
reg = <0x01c25000 0x100>;
interrupts = <29>;
allwinner,ts-attached;
#thermal-sensor-cells = <0>;
/* sensitive/noisy touch panel */
allwinner,tp-sensitive-adjust = <0>;
allwinner,filter-type = <3>;
};

1
arch/arm/boot/dts/Makefile
View File

@ -1117,6 +1117,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-s3-lichee-zero-plus.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \

2
arch/arm/boot/dts/sun4i-a10-a1000.dts
View File

@ -125,7 +125,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

2
arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
View File

@ -68,7 +68,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

2
arch/arm/boot/dts/sun4i-a10-cubieboard.dts
View File

@ -114,7 +114,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

2
arch/arm/boot/dts/sun4i-a10-hackberry.dts
View File

@ -80,7 +80,7 @@
};
&emac {
phy = <&phy0>;
phy-handle = <&phy0>;
status = "okay";
};

2
arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
View File

@ -58,7 +58,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

2
arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
View File

@ -94,7 +94,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

2
arch/arm/boot/dts/sun4i-a10-marsboard.dts
View File

@ -105,7 +105,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

2
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
View File

@ -112,7 +112,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

2
arch/arm/boot/dts/sun4i-a10-pcduino.dts
View File

@ -110,7 +110,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

9
arch/arm/boot/dts/sun4i-a10.dtsi
View File

@ -803,13 +803,20 @@
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
interrupts = <22>,
<23>,
<24>,
<25>,
<67>,
<68>;
clocks = <&osc24M>;
};
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
interrupts = <24>;
clocks = <&osc24M>;
};
rtc: rtc@1c20d00 {

2
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
View File

@ -98,7 +98,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_pa_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

2
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
View File

@ -91,7 +91,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_pd_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

2
arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
View File

@ -49,7 +49,7 @@
compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
panel: panel {
compatible = "bananapi,s070wv20-ct16", "simple-panel";
compatible = "bananapi,s070wv20-ct16";
power-supply = <&reg_vcc3v3>;
enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */
backlight = <&backlight>;

9
arch/arm/boot/dts/sun5i.dtsi
View File

@ -588,13 +588,20 @@
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
interrupts = <22>,
<23>,
<24>,
<25>,
<67>,
<68>;
clocks = <&ccu CLK_HOSC>;
};
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
interrupts = <24>;
clocks = <&osc24M>;
};
ir0: ir@1c21800 {

12
arch/arm/boot/dts/sun6i-a31-colombus.dts
View File

@ -76,13 +76,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -104,6 +100,12 @@
};
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;

18
arch/arm/boot/dts/sun6i-a31-hummingbird.dts
View File

@ -153,16 +153,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -199,6 +192,15 @@
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
};
};
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;

12
arch/arm/boot/dts/sun6i-a31-i7.dts
View File

@ -117,13 +117,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -142,6 +138,12 @@
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun6i-a31-m9.dts
View File

@ -84,14 +84,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <&reg_dldo1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {
@ -100,6 +96,12 @@
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;

12
arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
View File

@ -84,14 +84,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <&reg_dldo1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {
@ -100,6 +96,12 @@
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;

15
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@ -736,13 +736,16 @@
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
wdt1: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
spdif: spdif@1c21000 {
@ -939,8 +942,12 @@
snps,fixed-burst;
snps,force_sf_dma_mode;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
crypto: crypto-engine@1c15000 {
@ -1364,7 +1371,7 @@
};
ir: ir@1f02000 {
compatible = "allwinner,sun5i-a13-ir";
compatible = "allwinner,sun6i-a31-ir";
clocks = <&apb0_gates 1>, <&ir_clk>;
clock-names = "apb", "ir";
resets = <&apb0_rst 1>;

11
arch/arm/boot/dts/sun6i-a31s-cs908.dts
View File

@ -67,12 +67,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {
@ -81,6 +78,12 @@
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ohci1 {
status = "okay";
};

12
arch/arm/boot/dts/sun6i-a31s-sina31s.dts
View File

@ -115,14 +115,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <&reg_dldo1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -160,6 +156,12 @@
};
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;

18
arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
View File

@ -92,17 +92,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_dldo1>;
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {
@ -111,6 +104,15 @@
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; /* PA21 */
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
};
};
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
View File

@ -129,14 +129,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -171,6 +167,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-bananapi.dts
View File

@ -131,14 +131,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -171,6 +167,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-bananapro.dts
View File

@ -109,14 +109,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -143,6 +139,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
View File

@ -115,13 +115,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -161,6 +157,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ohci0 {
status = "okay";
};

12
arch/arm/boot/dts/sun7i-a20-cubietruck.dts
View File

@ -150,13 +150,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -194,6 +190,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

21
arch/arm/boot/dts/sun7i-a20-hummingbird.dts
View File

@ -100,19 +100,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_gmac_vdd>;
/* phy reset config */
snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
snps,reset-active-low;
/* wait 1s after reset, otherwise fail to read phy id */
snps,reset-delays-us = <0 10000 1000000>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -146,6 +137,16 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
reset-assert-us = <10000>;
/* wait 1s after reset, otherwise fail to read phy id */
reset-deassert-us = <1000000>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
View File

@ -115,14 +115,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -145,6 +141,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
View File

@ -76,13 +76,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -99,6 +95,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

4
arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
View File

@ -97,10 +97,12 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};

2
arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
View File

@ -123,8 +123,6 @@
phy-mode = "rgmii";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
fixed-link {
speed = <1000>;

12
arch/arm/boot/dts/sun7i-a20-m3.dts
View File

@ -82,13 +82,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -111,6 +107,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
View File

@ -111,13 +111,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -202,6 +198,12 @@
};
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

20
arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts
View File

@ -105,18 +105,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy3>;
phy-handle = <&phy3>;
phy-mode = "rgmii";
phy-supply = <&reg_vcc3v3>;
snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
status = "okay";
phy3: ethernet-phy@3 {
reg = <3>;
};
};
&hdmi {
@ -161,6 +153,16 @@
status = "okay";
};
&gmac_mdio {
phy3: ethernet-phy@3 {
reg = <3>;
reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
reset-assert-us = <10000>;
/* wait 1s after reset, otherwise fail to read phy id */
reset-deassert-us = <1000000>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
View File

@ -106,13 +106,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -149,6 +145,12 @@
};
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
View File

@ -111,13 +111,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -154,6 +150,12 @@
vref-supply = <&reg_vcc3v0>;
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
View File

@ -118,13 +118,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -215,6 +211,12 @@
};
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
View File

@ -120,14 +120,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -158,6 +154,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-orangepi.dts
View File

@ -96,14 +96,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -124,6 +120,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
View File

@ -114,13 +114,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -149,6 +145,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-pcduino3.dts
View File

@ -122,13 +122,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -149,6 +145,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

12
arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
View File

@ -81,13 +81,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -110,6 +106,12 @@
#include "axp209.dtsi"
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

35
arch/arm/boot/dts/sun7i-a20.dtsi
View File

@ -376,6 +376,17 @@
num-cs = <1>;
};
csi0: csi@1c09000 {
compatible = "allwinner,sun7i-a20-csi0";
reg = <0x01c09000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
clock-names = "bus", "mod", "isp", "ram";
resets = <&ccu RST_CSI0>;
status = "disabled";
};
emac: ethernet@1c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
@ -774,6 +785,20 @@
function = "clk_out_b";
};
/omit-if-no-ref/
csi0_8bits_pins: csi-8bits-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5",
"PE6", "PE7", "PE8", "PE9", "PE10",
"PE11";
function = "csi0";
};
/omit-if-no-ref/
csi0_clk_pin: csi-clk-pin {
pins = "PE1";
function = "csi0";
};
/omit-if-no-ref/
emac_pa_pins: emac-pa-pins {
pins = "PA0", "PA1", "PA2",
@ -1115,6 +1140,8 @@
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
rtc: rtc@1c20d00 {
@ -1437,8 +1464,12 @@
snps,fixed-burst;
snps,force_sf_dma_mode;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
gmac_mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
hstimer@1c60000 {

3
arch/arm/boot/dts/sun8i-a23-a33.dtsi
View File

@ -441,7 +441,7 @@
};
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
compatible = "allwinner,sun8i-a23-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@ -452,6 +452,7 @@
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
pwm: pwm@1c21400 {

2
arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
View File

@ -63,7 +63,7 @@
};
&panel {
compatible = "bananapi,s070wv20-ct16", "simple-panel";
compatible = "bananapi,s070wv20-ct16";
};
&tcon0_out {

25
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
View File

@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
@ -153,6 +164,10 @@
cpu-supply = <&reg_dcdc3>;
};
&de {
status = "okay";
};
&ehci0 {
/* GL830 USB-to-SATA bridge here */
status = "okay";
@ -172,6 +187,16 @@
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mdio {
rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";

14
arch/arm/boot/dts/sun8i-a83t.dtsi
View File

@ -314,10 +314,10 @@
display_clocks: clock@1000000 {
compatible = "allwinner,sun8i-a83t-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_PLL_DE>,
<&ccu CLK_BUS_DE>;
clock-names = "mod",
"bus";
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_PLL_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -806,7 +806,7 @@
};
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
compatible = "allwinner,sun8i-a23-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@ -1037,7 +1037,7 @@
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
phy-names = "phy";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
status = "disabled";
@ -1096,7 +1096,7 @@
r_cir: ir@1f02000 {
compatible = "allwinner,sun8i-a83t-ir",
"allwinner,sun5i-a13-ir";
"allwinner,sun6i-a31-ir";
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;

12
arch/arm/boot/dts/sun8i-r40.dtsi
View File

@ -119,10 +119,10 @@
compatible = "allwinner,sun8i-r40-de2-clk",
"allwinner,sun8i-h3-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_DE>,
<&ccu CLK_BUS_DE>;
clock-names = "mod",
"bus";
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -404,6 +404,8 @@
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
uart0: serial@1c28000 {
@ -808,7 +810,7 @@
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
phy-names = "phy";
status = "disabled";
ports {

53
arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts Normal file
View File

@ -0,0 +1,53 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
*/
/dts-v1/;
#include "sun8i-v3.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Sipeed Lichee Zero Plus";
compatible = "sipeed,lichee-zero-plus", "sochip,s3",
"allwinner,sun8i-v3";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&mmc0 {
broken-cd;
bus-width = <4>;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pb_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};

14
arch/arm/boot/dts/sun8i-v3.dtsi Normal file
View File

@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
*/
#include "sun8i-v3s.dtsi"
&ccu {
compatible = "allwinner,sun8i-v3-ccu";
};
&pio {
compatible = "allwinner,sun8i-v3-pinctrl";
};

14
arch/arm/boot/dts/sun8i-v3s.dtsi
View File

@ -106,10 +106,10 @@
display_clocks: clock@1000000 {
compatible = "allwinner,sun8i-v3s-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_DE>,
<&ccu CLK_BUS_DE>;
clock-names = "mod",
"bus";
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -327,10 +327,11 @@
};
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
compatible = "allwinner,sun8i-v3s-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
@ -338,6 +339,7 @@
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
lradc: lradc@1c22800 {

12
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
View File

@ -128,14 +128,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_cldo1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c3 {
@ -144,6 +140,12 @@
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;

4
arch/arm/boot/dts/sun9i-a80-optimus.dts
View File

@ -123,11 +123,13 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_cldo1>;
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};

10
arch/arm/boot/dts/sun9i-a80.dtsi
View File

@ -331,8 +331,12 @@
snps,fixed-burst;
snps,force_sf_dma_mode;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
ehci0: usb@a00000 {
@ -1167,7 +1171,7 @@
};
r_ir: ir@8002000 {
compatible = "allwinner,sun5i-a13-ir";
compatible = "allwinner,sun6i-a31-ir";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&r_ir_pins>;

15
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@ -114,10 +114,10 @@
display_clocks: clock@1000000 {
/* compatible is in per SoC .dtsi file */
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_DE>,
<&ccu CLK_BUS_DE>;
clock-names = "mod",
"bus";
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -484,7 +484,7 @@
};
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
compatible = "allwinner,sun8i-a23-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@ -574,6 +574,7 @@
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
spdif: spdif@1c21000 {
@ -765,7 +766,7 @@
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
phy-names = "phy";
status = "disabled";
ports {
@ -822,7 +823,7 @@
};
ir: ir@1f02000 {
compatible = "allwinner,sun5i-a13-ir";
compatible = "allwinner,sun6i-a31-ir";
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;

2
arch/arm64/boot/dts/allwinner/Makefile
View File

@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-emmc.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
@ -25,3 +26,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb

23
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts Normal file
View File

@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 Martin Ayotte <martinayotte@gmail.com>
* Copyright (C) 2019 Sunil Mohan Adapa <sunil@medhas.org>
*/
#include "sun50i-a64-olinuxino.dts"
/ {
model = "Olimex A64-Olinuxino-eMMC";
compatible = "olimex,a64-olinuxino-emmc", "allwinner,sun50i-a64";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};

4
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
View File

@ -190,6 +190,10 @@
status = "okay";
};
&r_ir {
status = "okay";
};
&r_rsb {
status = "okay";

29
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -228,10 +228,10 @@
display_clocks: clock@0 {
compatible = "allwinner,sun50i-a64-de2-clk";
reg = <0x0 0x100000>;
clocks = <&ccu CLK_DE>,
<&ccu CLK_BUS_DE>;
clock-names = "mod",
"bus";
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -1015,7 +1015,7 @@
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
phy-names = "phy";
status = "disabled";
ports {
@ -1094,6 +1094,19 @@
#size-cells = <0>;
};
r_ir: ir@1f02000 {
compatible = "allwinner,sun50i-a64-ir",
"allwinner,sun6i-a31-ir";
reg = <0x01f02000 0x400>;
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&r_ir_rx_pin>;
status = "disabled";
};
r_pwm: pwm@1f03800 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
@ -1121,6 +1134,11 @@
function = "s_i2c";
};
r_ir_rx_pin: r-ir-rx-pin {
pins = "PL11";
function = "s_cir_rx";
};
r_pwm_pin: r-pwm-pin {
pins = "PL10";
function = "s_pwm";
@ -1151,6 +1169,7 @@
"allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
};
};

27
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
View File

@ -25,6 +25,7 @@
connector {
compatible = "hdmi-connector";
type = "a";
ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
port {
hdmi_con_in: endpoint {
@ -51,6 +52,24 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
sound-spdif {
compatible = "simple-audio-card";
simple-audio-card,name = "sun50i-h6-spdif";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
};
&de {
@ -232,6 +251,10 @@
};
};
&r_ir {
status = "okay";
};
&r_pio {
/*
* PL0 and PL1 are used for PMIC I2C
@ -243,6 +266,10 @@
vcc-pm-supply = <&reg_aldo1>;
};
&spdif {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;

72
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
View File

@ -21,6 +21,18 @@
stdout-path = "serial0:115200n8";
};
connector {
compatible = "hdmi-connector";
ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
@ -44,12 +56,44 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_vcc33_wifi: vcc33-wifi {
/* Always on 3.3V regulator for WiFi and BT */
compatible = "regulator-fixed";
regulator-name = "vcc33-wifi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&reg_vcc5v>;
};
reg_vcc_wifi_io: vcc-wifi-io {
/* Always on 1.8V/300mA regulator for WiFi and BT IO */
compatible = "regulator-fixed";
regulator-name = "vcc-wifi-io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
vin-supply = <&reg_vcc33_wifi>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
post-power-on-delay-ms = <200>;
};
};
&cpu0 {
cpu-supply = <&reg_dcdca>;
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
@ -58,6 +102,16 @@
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mmc0 {
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@ -65,6 +119,23 @@
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_vcc33_wifi>;
vqmmc-supply = <&reg_vcc_wifi_io>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
brcm: sdio-wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&r_pio>;
interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
interrupt-names = "host-wake";
};
};
&ohci0 {
status = "okay";
};
@ -76,6 +147,7 @@
&pio {
vcc-pc-supply = <&reg_bldo2>;
vcc-pd-supply = <&reg_cldo1>;
vcc-pg-supply = <&reg_vcc_wifi_io>;
};
&r_i2c {

4
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
View File

@ -189,6 +189,10 @@
};
};
&r_ir {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;

4
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
View File

@ -255,6 +255,10 @@
};
};
&r_ir {
status = "okay";
};
&r_pio {
vcc-pm-supply = <&reg_aldo1>;
};

100
arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts Normal file
View File

@ -0,0 +1,100 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
*/
/dts-v1/;
#include "sun50i-h6.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Tanix TX6";
compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
connector {
compatible = "hdmi-connector";
ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci3 {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci3 {
status = "okay";
};
&r_ir {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usb2otg {
dr_mode = "host";
status = "okay";
};
&usb2phy {
status = "okay";
};

135
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
View File

@ -56,14 +56,6 @@
status = "disabled";
};
iosc: internal-osc-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-accuracy = <300000000>;
clock-output-names = "iosc";
};
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -71,11 +63,11 @@
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
ext_osc32k: ext_osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
clock-output-names = "ext_osc32k";
};
psci {
@ -197,7 +189,7 @@
ccu: clock@3001000 {
compatible = "allwinner,sun50i-h6-ccu";
reg = <0x03001000 0x1000>;
clocks = <&osc24M>, <&osc32k>, <&iosc>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -215,7 +207,7 @@
#dma-cells = <1>;
};
sid: sid@3006000 {
sid: efuse@3006000 {
compatible = "allwinner,sun50i-h6-sid";
reg = <0x03006000 0x400>;
};
@ -225,6 +217,7 @@
"allwinner,sun6i-a31-wdt";
reg = <0x030090a0 0x20>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
/* Broken on some H6 boards */
status = "disabled";
};
@ -236,7 +229,7 @@
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@ -256,6 +249,21 @@
function = "hdmi";
};
i2c0_pins: i2c0-pins {
pins = "PD25", "PD26";
function = "i2c0";
};
i2c1_pins: i2c1-pins {
pins = "PH5", "PH6";
function = "i2c1";
};
i2c2_pins: i2c2-pins {
pins = "PD23", "PD24";
function = "i2c2";
};
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
@ -282,6 +290,11 @@
bias-pull-up;
};
spdif_tx_pin: spdif-tx-pin {
pins = "PH7";
function = "spdif";
};
uart0_ph_pins: uart0-ph-pins {
pins = "PH0", "PH1";
function = "uart0";
@ -391,6 +404,48 @@
status = "disabled";
};
i2c0: i2c@5002000 {
compatible = "allwinner,sun50i-h6-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002000 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@5002400 {
compatible = "allwinner,sun50i-h6-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002400 0x400>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@5002800 {
compatible = "allwinner,sun50i-h6-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002800 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
emac: ethernet@5020000 {
compatible = "allwinner,sun50i-h6-emac",
"allwinner,sun50i-a64-emac";
@ -411,6 +466,21 @@
};
};
spdif: spdif@5093000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-h6-spdif";
reg = <0x05093000 0x400>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
clock-names = "apb", "spdif";
resets = <&ccu RST_BUS_SPDIF>;
dmas = <&dma 2>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx_pin>;
status = "disabled";
};
usb2otg: usb@5100000 {
compatible = "allwinner,sun50i-h6-musb",
"allwinner,sun8i-a33-musb";
@ -504,7 +574,7 @@
resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
reset-names = "ctrl", "hdcp";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
phy-names = "phy";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
status = "disabled";
@ -633,10 +703,20 @@
};
};
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h6-rtc";
reg = <0x07000000 0x400>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "osc32k", "osc32k-out", "iosc";
clocks = <&ext_osc32k>;
#clock-cells = <1>;
};
r_ccu: clock@7010000 {
compatible = "allwinner,sun50i-h6-r-ccu";
reg = <0x07010000 0x400>;
clocks = <&osc24M>, <&osc32k>, <&iosc>,
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
@ -648,6 +728,7 @@
"allwinner,sun6i-a31-wdt";
reg = <0x07020400 0x20>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
r_intc: interrupt-controller@7021000 {
@ -664,7 +745,7 @@
reg = <0x07022000 0x400>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@ -675,10 +756,30 @@
pins = "PL0", "PL1";
function = "s_i2c";
};
r_ir_rx_pin: r-ir-rx-pin {
pins = "PL9";
function = "s_cir_rx";
};
};
r_ir: ir@7040000 {
compatible = "allwinner,sun50i-h6-ir",
"allwinner,sun6i-a31-ir";
reg = <0x07040000 0x400>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1_IR>,
<&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_R_APB1_IR>;
pinctrl-names = "default";
pinctrl-0 = <&r_ir_rx_pin>;
status = "disabled";
};
r_i2c: i2c@7081400 {
compatible = "allwinner,sun6i-a31-i2c";
compatible = "allwinner,sun50i-h6-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x07081400 0x400>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB2_I2C>;