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Merge branch 'pci/controller/keystone'
- Enable BAR 0 only for v3.65a to avoid Completion Timeouts that cause a 45 second boot delay on the v4.90a-based AM654x SoC (Siddharth Vadapalli) - Avoid a NULL pointer dereference if DT failed to provide a host bridge memory window (Aleksandr Mishin) * pci/controller/keystone: PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) PCI: keystone: Fix NULL pointer dereference in case of DT error in ks_pcie_setup_rc_app_regs() PCI: keystone: Don't enable BAR 0 for AM654x PCI: keystone: Relocate ks_pcie_set/clear_dbi_mode()
This commit is contained in:
Bjorn Helgaas
commit
db2cc94fae
@ -34,6 +34,11 @@
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#define PCIE_DEVICEID_SHIFT 16
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/* Application registers */
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#define PID 0x000
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#define RTL GENMASK(15, 11)
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#define RTL_SHIFT 11
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#define AM6_PCI_PG1_RTL_VER 0x15
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#define CMD_STATUS 0x004
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#define LTSSM_EN_VAL BIT(0)
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#define OB_XLAT_EN_VAL BIT(1)
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@ -104,6 +109,8 @@
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#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
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#define PCI_DEVICE_ID_TI_AM654X 0xb00c
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struct ks_pcie_of_data {
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enum dw_pcie_device_mode mode;
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const struct dw_pcie_host_ops *host_ops;
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@ -245,8 +252,68 @@ static struct irq_chip ks_pcie_msi_irq_chip = {
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.irq_unmask = ks_pcie_msi_unmask,
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};
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/**
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* ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
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* @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
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* PCIe host controller driver information.
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*
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* Since modification of dbi_cs2 involves different clock domain, read the
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* status back to ensure the transition is complete.
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*/
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static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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val |= DBI_CS2;
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
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do {
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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} while (!(val & DBI_CS2));
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}
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/**
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* ks_pcie_clear_dbi_mode() - Disable DBI mode
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* @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
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* PCIe host controller driver information.
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*
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* Since modification of dbi_cs2 involves different clock domain, read the
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* status back to ensure the transition is complete.
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*/
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static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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val &= ~DBI_CS2;
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
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do {
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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} while (val & DBI_CS2);
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}
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static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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/* Configure and set up BAR0 */
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ks_pcie_set_dbi_mode(ks_pcie);
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/* Enable BAR0 */
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
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ks_pcie_clear_dbi_mode(ks_pcie);
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/*
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* For BAR0, just setting bus address for inbound writes (MSI) should
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* be sufficient. Use physical address to avoid any conflicts.
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*/
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
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pp->msi_irq_chip = &ks_pcie_msi_irq_chip;
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return dw_pcie_allocate_domains(pp);
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}
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@ -340,59 +407,22 @@ static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = {
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.xlate = irq_domain_xlate_onetwocell,
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};
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/**
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* ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers
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* @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
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* PCIe host controller driver information.
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*
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* Since modification of dbi_cs2 involves different clock domain, read the
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* status back to ensure the transition is complete.
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*/
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static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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val |= DBI_CS2;
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
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do {
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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} while (!(val & DBI_CS2));
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}
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/**
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* ks_pcie_clear_dbi_mode() - Disable DBI mode
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* @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone
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* PCIe host controller driver information.
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*
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* Since modification of dbi_cs2 involves different clock domain, read the
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* status back to ensure the transition is complete.
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*/
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static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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val &= ~DBI_CS2;
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
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do {
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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} while (val & DBI_CS2);
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}
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static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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static int ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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u32 num_viewport = ks_pcie->num_viewport;
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struct dw_pcie *pci = ks_pcie->pci;
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struct dw_pcie_rp *pp = &pci->pp;
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u64 start, end;
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struct resource_entry *entry;
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struct resource *mem;
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u64 start, end;
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int i;
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mem = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM)->res;
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entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
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if (!entry)
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return -ENODEV;
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mem = entry->res;
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start = mem->start;
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end = mem->end;
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@ -403,7 +433,7 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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ks_pcie_clear_dbi_mode(ks_pcie);
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if (ks_pcie->is_am6)
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return;
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return 0;
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val = ilog2(OB_WIN_SIZE);
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ks_pcie_app_writel(ks_pcie, OB_SIZE, val);
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@ -420,6 +450,8 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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val |= OB_XLAT_EN_VAL;
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
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return 0;
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}
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static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus,
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@ -445,44 +477,10 @@ static struct pci_ops ks_child_pcie_ops = {
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.write = pci_generic_config_write,
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};
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/**
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* ks_pcie_v3_65_add_bus() - keystone add_bus post initialization
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* @bus: A pointer to the PCI bus structure.
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*
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* This sets BAR0 to enable inbound access for MSI_IRQ register
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*/
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static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)
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{
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struct dw_pcie_rp *pp = bus->sysdata;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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if (!pci_is_root_bus(bus))
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return 0;
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/* Configure and set up BAR0 */
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ks_pcie_set_dbi_mode(ks_pcie);
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/* Enable BAR0 */
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
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ks_pcie_clear_dbi_mode(ks_pcie);
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/*
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* For BAR0, just setting bus address for inbound writes (MSI) should
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* be sufficient. Use physical address to avoid any conflicts.
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*/
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
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return 0;
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}
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static struct pci_ops ks_pcie_ops = {
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.map_bus = dw_pcie_own_conf_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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.add_bus = ks_pcie_v3_65_add_bus,
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};
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/**
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@ -525,7 +523,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci)
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static void ks_pcie_quirk(struct pci_dev *dev)
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{
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struct pci_bus *bus = dev->bus;
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struct keystone_pcie *ks_pcie;
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struct device *bridge_dev;
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struct pci_dev *bridge;
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u32 val;
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static const struct pci_device_id rc_pci_devids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
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.class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
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@ -537,6 +539,11 @@ static void ks_pcie_quirk(struct pci_dev *dev)
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.class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
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{ 0, },
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};
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static const struct pci_device_id am6_pci_devids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X),
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.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
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{ 0, },
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};
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if (pci_is_root_bus(bus))
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bridge = dev;
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@ -558,10 +565,36 @@ static void ks_pcie_quirk(struct pci_dev *dev)
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*/
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if (pci_match_id(rc_pci_devids, bridge)) {
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if (pcie_get_readrq(dev) > 256) {
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dev_info(&dev->dev, "limiting MRRS to 256\n");
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dev_info(&dev->dev, "limiting MRRS to 256 bytes\n");
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pcie_set_readrq(dev, 256);
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}
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}
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/*
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* Memory transactions fail with PCI controller in AM654 PG1.0
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* when MRRS is set to more than 128 bytes. Force the MRRS to
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* 128 bytes in all downstream devices.
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*/
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if (pci_match_id(am6_pci_devids, bridge)) {
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bridge_dev = pci_get_host_bridge_device(dev);
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if (!bridge_dev && !bridge_dev->parent)
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return;
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ks_pcie = dev_get_drvdata(bridge_dev->parent);
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if (!ks_pcie)
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return;
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val = ks_pcie_app_readl(ks_pcie, PID);
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val &= RTL;
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val >>= RTL_SHIFT;
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if (val != AM6_PCI_PG1_RTL_VER)
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return;
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if (pcie_get_readrq(dev) > 128) {
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dev_info(&dev->dev, "limiting MRRS to 128 bytes\n");
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pcie_set_readrq(dev, 128);
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}
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}
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}
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);
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@ -814,7 +847,10 @@ static int __init ks_pcie_host_init(struct dw_pcie_rp *pp)
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return ret;
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ks_pcie_stop_link(pci);
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ks_pcie_setup_rc_app_regs(ks_pcie);
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ret = ks_pcie_setup_rc_app_regs(ks_pcie);
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if (ret)
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return ret;
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writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
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pci->dbi_base + PCI_IO_BASE);
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