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clk: starfive: Add StarFive JH7110 Video-Output clock driver
Add driver for the StarFive JH7110 Video-Output clock controller. And these clock controllers should power on and enable the clocks from SYSCRG first before registering. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Xingyu Wu
Conor Dooley
parent
81279f5d08
commit
dae5448a32
@ -64,3 +64,11 @@ config CLK_STARFIVE_JH7110_ISP
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help
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Say yes here to support the Image-Signal-Process clock controller
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on the StarFive JH7110 SoC.
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config CLK_STARFIVE_JH7110_VOUT
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tristate "StarFive JH7110 Video-Output clock support"
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depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU
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default m if ARCH_STARFIVE
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help
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Say yes here to support the Video-Output clock controller
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on the StarFive JH7110 SoC.
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@ -9,3 +9,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
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239
drivers/clk/starfive/clk-starfive-jh7110-vout.c
Normal file
239
drivers/clk/starfive/clk-starfive-jh7110-vout.c
Normal file
@ -0,0 +1,239 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* StarFive JH7110 Video-Output Clock Driver
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*
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* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include "clk-starfive-jh7110.h"
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/* external clocks */
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#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
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#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
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#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
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#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
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#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
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#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
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#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
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static struct clk_bulk_data jh7110_vout_top_clks[] = {
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{ .id = "vout_src" },
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{ .id = "vout_top_ahb" }
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};
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static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
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/* divider */
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JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
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JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
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JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
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JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
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/* dc8200 */
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JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
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JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
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JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
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JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
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JH7110_VOUTCLK_DC8200_PIX,
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JH7110_VOUTCLK_HDMITX0_PIXELCLK),
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JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
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JH7110_VOUTCLK_DC8200_PIX,
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JH7110_VOUTCLK_HDMITX0_PIXELCLK),
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/* LCD */
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JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
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JH7110_VOUTCLK_DC8200_PIX0,
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JH7110_VOUTCLK_DC8200_PIX1),
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/* dsiTx */
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JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
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JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
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JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
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JH7110_VOUTCLK_DC8200_PIX,
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JH7110_VOUTCLK_HDMITX0_PIXELCLK),
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JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
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/* mipitx DPHY */
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JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
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JH7110_VOUTCLK_TX_ESC),
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/* hdmi */
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JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
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JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
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JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
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JH7110_VOUTCLK_I2STX0_BCLK),
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JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
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};
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static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
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{
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struct reset_control *top_rst;
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/* The reset should be shared and other Vout modules will use its. */
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top_rst = devm_reset_control_get_shared(priv->dev, NULL);
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if (IS_ERR(top_rst))
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return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
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return reset_control_deassert(top_rst);
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}
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static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
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{
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struct jh71x0_clk_priv *priv = data;
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unsigned int idx = clkspec->args[0];
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if (idx < JH7110_VOUTCLK_END)
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return &priv->reg[idx].hw;
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return ERR_PTR(-EINVAL);
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}
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#ifdef CONFIG_PM
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static int jh7110_voutcrg_suspend(struct device *dev)
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{
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struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
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clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
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return 0;
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}
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static int jh7110_voutcrg_resume(struct device *dev)
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{
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struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
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return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
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}
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static const struct dev_pm_ops jh7110_voutcrg_pm_ops = {
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RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL)
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};
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#endif
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static int jh7110_voutcrg_probe(struct platform_device *pdev)
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{
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struct jh71x0_clk_priv *priv;
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struct jh7110_top_sysclk *top;
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unsigned int idx;
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int ret;
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priv = devm_kzalloc(&pdev->dev,
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struct_size(priv, reg, JH7110_VOUTCLK_END),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
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if (!top)
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return -ENOMEM;
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spin_lock_init(&priv->rmw_lock);
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priv->dev = &pdev->dev;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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top->top_clks = jh7110_vout_top_clks;
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top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);
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ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
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if (ret)
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return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
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dev_set_drvdata(priv->dev, top);
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/* enable power domain and clocks */
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pm_runtime_enable(priv->dev);
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ret = pm_runtime_get_sync(priv->dev);
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if (ret < 0)
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return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
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ret = jh7110_vout_top_rst_init(priv);
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if (ret)
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goto err_exit;
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for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) {
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u32 max = jh7110_voutclk_data[idx].max;
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struct clk_parent_data parents[4] = {};
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struct clk_init_data init = {
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.name = jh7110_voutclk_data[idx].name,
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.ops = starfive_jh71x0_clk_ops(max),
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.parent_data = parents,
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.num_parents =
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((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
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.flags = jh7110_voutclk_data[idx].flags,
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};
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struct jh71x0_clk *clk = &priv->reg[idx];
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unsigned int i;
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const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
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"vout_src",
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"vout_top_ahb",
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"vout_top_axi",
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"vout_top_hdmitx0_mclk",
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"i2stx0_bclk",
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"hdmitx0_pixelclk"
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};
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for (i = 0; i < init.num_parents; i++) {
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unsigned int pidx = jh7110_voutclk_data[idx].parents[i];
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if (pidx < JH7110_VOUTCLK_END)
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parents[i].hw = &priv->reg[pidx].hw;
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else if (pidx < JH7110_VOUTCLK_EXT_END)
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parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];
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}
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clk->hw.init = &init;
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clk->idx = idx;
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clk->max_div = max & JH71X0_CLK_DIV_MASK;
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ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
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if (ret)
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goto err_exit;
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}
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ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv);
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if (ret)
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goto err_exit;
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ret = jh7110_reset_controller_register(priv, "rst-vo", 4);
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if (ret)
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goto err_exit;
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return 0;
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err_exit:
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pm_runtime_put_sync(priv->dev);
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pm_runtime_disable(priv->dev);
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return ret;
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}
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static int jh7110_voutcrg_remove(struct platform_device *pdev)
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{
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static const struct of_device_id jh7110_voutcrg_match[] = {
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{ .compatible = "starfive,jh7110-voutcrg" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
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static struct platform_driver jh7110_voutcrg_driver = {
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.probe = jh7110_voutcrg_probe,
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.remove = jh7110_voutcrg_remove,
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.driver = {
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.name = "clk-starfive-jh7110-vout",
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.of_match_table = jh7110_voutcrg_match,
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.pm = pm_ptr(&jh7110_voutcrg_pm_ops),
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},
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};
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module_platform_driver(jh7110_voutcrg_driver);
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MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
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MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver");
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MODULE_LICENSE("GPL");
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