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drm/i915/bxt: PORT_PLL_REF_SEL bit should be set for all BXT variations

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This patch is to correct one thing in this commit:

commit 25a5670533
Author: Dongwon Kim <dongwon.kim@intel.com>
Date:   Wed Mar 16 18:06:13 2016 -0700

    drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit

This reversed bit polarity is actually common
for all BXT and APL SoCs. Therefore, revision checking
in the original commit should be removed to make
the bit set regardless of revision ID of GFX block.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460673463-14453-1-git-send-email-dongwon.kim@intel.com
This commit is contained in:
Dongwon Kim 2016-04-14 15:37:43 -07:00 committed by Imre Deak
parent 8f6d855c4b
commit da6110bcbc
1 changed files with 2 additions and 10 deletions
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12
drivers/gpu/drm/i915/intel_dpll_mgr.c
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@ -1295,17 +1295,9 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
uint32_t temp;
enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
/*
* Definition of each bit polarity has been changed
* after A1 stepping
*/
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
temp &= ~PORT_PLL_REF_SEL;
else
temp |= PORT_PLL_REF_SEL;
/* Non-SSC reference */
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
temp |= PORT_PLL_REF_SEL;
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
/* Disable 10 bit clock */