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dt-bindings: mtd: Convert Qcom NANDc binding to YAML
Convert Qcom NANDc devicetree binding to YAML. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210402150128.29128-2-manivannan.sadhasivam@linaro.org
This commit is contained in:
Manivannan Sadhasivam
Miquel Raynal
parent
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commit
da386f7f23
196
Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
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196
Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm NAND controller
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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properties:
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compatible:
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enum:
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- qcom,ipq806x-nand
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- qcom,ipq4019-nand
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- qcom,ipq6018-nand
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- qcom,ipq8074-nand
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- qcom,sdx55-nand
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Core Clock
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- description: Always ON Clock
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clock-names:
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items:
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- const: core
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- const: aon
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"#address-cells": true
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"#size-cells": true
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patternProperties:
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"^nand@[a-f0-9]$":
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type: object
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properties:
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nand-bus-width:
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const: 8
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nand-ecc-strength:
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enum: [1, 4, 8]
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nand-ecc-step-size:
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enum:
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- 512
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allOf:
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- $ref: "nand-controller.yaml#"
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- if:
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properties:
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compatible:
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contains:
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const: qcom,ipq806x-nand
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then:
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properties:
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dmas:
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items:
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- description: rxtx DMA channel
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dma-names:
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items:
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- const: rxtx
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qcom,cmd-crci:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Must contain the ADM command type CRCI block instance number
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specified for the NAND controller on the given platform
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qcom,data-crci:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Must contain the ADM data type CRCI block instance number
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specified for the NAND controller on the given platform
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,ipq4019-nand
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- qcom,ipq6018-nand
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- qcom,ipq8074-nand
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- qcom,sdx55-nand
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then:
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properties:
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dmas:
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items:
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- description: tx DMA channel
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- description: rx DMA channel
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- description: cmd DMA channel
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dma-names:
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items:
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- const: tx
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- const: rx
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- const: cmd
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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nand-controller@1ac00000 {
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compatible = "qcom,ipq806x-nand";
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reg = <0x1ac00000 0x800>;
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clocks = <&gcc EBI2_CLK>,
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<&gcc EBI2_AON_CLK>;
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clock-names = "core", "aon";
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dmas = <&adm_dma 3>;
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dma-names = "rxtx";
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qcom,cmd-crci = <15>;
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qcom,data-crci = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "boot-nand";
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reg = <0 0x58a0000>;
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};
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partition@58a0000 {
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label = "fs-nand";
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reg = <0x58a0000 0x4000000>;
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};
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};
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};
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};
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#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
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nand-controller@79b0000 {
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compatible = "qcom,ipq4019-nand";
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reg = <0x79b0000 0x1000>;
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clocks = <&gcc GCC_QPIC_CLK>,
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<&gcc GCC_QPIC_AHB_CLK>;
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clock-names = "core", "aon";
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dmas = <&qpicbam 0>,
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<&qpicbam 1>,
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<&qpicbam 2>;
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dma-names = "tx", "rx", "cmd";
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "boot-nand";
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reg = <0 0x58a0000>;
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};
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partition@58a0000 {
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label = "fs-nand";
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reg = <0x58a0000 0x4000000>;
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};
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};
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};
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};
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...
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@ -1,142 +0,0 @@
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* Qualcomm NAND controller
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Required properties:
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- compatible: must be one of the following:
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* "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
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SoC and it uses ADM DMA
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* "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
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IPQ4019 SoC and it uses BAM DMA
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* "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
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IPQ6018 SoC and it uses BAM DMA
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* "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
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IPQ8074 SoC and it uses BAM DMA
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* "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
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SDX55 SoC and it uses BAM DMA
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- reg: MMIO address range
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- clocks: must contain core clock and always on clock
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- clock-names: must contain "core" for the core clock and "aon" for the
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always on clock
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EBI2 specific properties:
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- dmas: DMA specifier, consisting of a phandle to the ADM DMA
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controller node and the channel number to be used for
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NAND. Refer to dma.txt and qcom_adm.txt for more details
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- dma-names: must be "rxtx"
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- qcom,cmd-crci: must contain the ADM command type CRCI block instance
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number specified for the NAND controller on the given
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platform
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- qcom,data-crci: must contain the ADM data type CRCI block instance
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number specified for the NAND controller on the given
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platform
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QPIC specific properties:
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- dmas: DMA specifier, consisting of a phandle to the BAM DMA
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and the channel number to be used for NAND. Refer to
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dma.txt, qcom_bam_dma.txt for more details
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- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
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- #address-cells: <1> - subnodes give the chip-select number
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- #size-cells: <0>
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* NAND chip-select
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Each controller may contain one or more subnodes to represent enabled
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chip-selects which (may) contain NAND flash chips. Their properties are as
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follows.
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Required properties:
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- reg: a single integer representing the chip-select
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number (e.g., 0, 1, 2, etc.)
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- #address-cells: see partition.txt
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- #size-cells: see partition.txt
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Optional properties:
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- nand-bus-width: see nand-controller.yaml
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- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
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be used according to chip requirement and available
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OOB size.
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Each nandcs device node may optionally contain a 'partitions' sub-node, which
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further contains sub-nodes describing the flash partition mapping. See
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partition.txt for more detail.
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Example:
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nand-controller@1ac00000 {
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compatible = "qcom,ipq806x-nand";
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reg = <0x1ac00000 0x800>;
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clocks = <&gcc EBI2_CLK>,
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<&gcc EBI2_AON_CLK>;
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clock-names = "core", "aon";
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dmas = <&adm_dma 3>;
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dma-names = "rxtx";
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qcom,cmd-crci = <15>;
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qcom,data-crci = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "boot-nand";
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reg = <0 0x58a0000>;
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};
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partition@58a0000 {
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label = "fs-nand";
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reg = <0x58a0000 0x4000000>;
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};
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};
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};
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};
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nand-controller@79b0000 {
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compatible = "qcom,ipq4019-nand";
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reg = <0x79b0000 0x1000>;
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clocks = <&gcc GCC_QPIC_CLK>,
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<&gcc GCC_QPIC_AHB_CLK>;
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clock-names = "core", "aon";
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dmas = <&qpicbam 0>,
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<&qpicbam 1>,
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<&qpicbam 2>;
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dma-names = "tx", "rx", "cmd";
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "boot-nand";
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reg = <0 0x58a0000>;
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};
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partition@58a0000 {
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label = "fs-nand";
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reg = <0x58a0000 0x4000000>;
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};
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};
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};
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};
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