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extcon: sm5502: Add support for SM5504
SM5504 is another MUIC from Silicon Mitus that is fairly similar to SM5502. They seem to use the same register set, but: - SM5504 has some additional bits in SM5502_REG_CONTROL - SM5504 has a quite different set of interrupts - SM5504 reports USB OTG as dev_type1 = BIT(0) instead of BIT(7) Overall it's minor and we can support this by defining a separate struct sm5502_type for SM5504. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
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f33c056dea
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@ -154,7 +154,7 @@ config EXTCON_RT8973A
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from abnormal high input voltage (up to 28V).
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config EXTCON_SM5502
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tristate "Silicon Mitus SM5502 EXTCON support"
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tristate "Silicon Mitus SM5502/SM5504 EXTCON support"
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depends on I2C
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select IRQ_DOMAIN
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select REGMAP_I2C
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@ -66,6 +66,7 @@ struct sm5502_type {
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struct reg_data *reg_data;
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unsigned int num_reg_data;
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unsigned int otg_dev_type1;
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int (*parse_irq)(struct sm5502_muic_info *info, int irq_type);
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};
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@ -97,6 +98,33 @@ static struct reg_data sm5502_reg_data[] = {
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},
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};
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/* Default value of SM5504 register to bring up MUIC device. */
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static struct reg_data sm5504_reg_data[] = {
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{
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.reg = SM5502_REG_RESET,
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.val = SM5502_REG_RESET_MASK,
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.invert = true,
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}, {
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.reg = SM5502_REG_INTMASK1,
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.val = SM5504_REG_INTM1_ATTACH_MASK
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| SM5504_REG_INTM1_DETACH_MASK,
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.invert = false,
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}, {
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.reg = SM5502_REG_INTMASK2,
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.val = SM5504_REG_INTM2_RID_CHG_MASK
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| SM5504_REG_INTM2_UVLO_MASK
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| SM5504_REG_INTM2_POR_MASK,
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.invert = true,
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}, {
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.reg = SM5502_REG_CONTROL,
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.val = SM5502_REG_CONTROL_MANUAL_SW_MASK
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| SM5504_REG_CONTROL_CHGTYP_MASK
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| SM5504_REG_CONTROL_USBCHDEN_MASK
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| SM5504_REG_CONTROL_ADC_EN_MASK,
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.invert = true,
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},
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};
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/* List of detectable cables */
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static const unsigned int sm5502_extcon_cable[] = {
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EXTCON_USB,
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@ -205,6 +233,55 @@ static const struct regmap_irq_chip sm5502_muic_irq_chip = {
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.num_irqs = ARRAY_SIZE(sm5502_irqs),
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};
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/* List of supported interrupt for SM5504 */
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static struct muic_irq sm5504_muic_irqs[] = {
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{ SM5504_IRQ_INT1_ATTACH, "muic-attach" },
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{ SM5504_IRQ_INT1_DETACH, "muic-detach" },
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{ SM5504_IRQ_INT1_CHG_DET, "muic-chg-det" },
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{ SM5504_IRQ_INT1_DCD_OUT, "muic-dcd-out" },
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{ SM5504_IRQ_INT1_OVP_EVENT, "muic-ovp-event" },
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{ SM5504_IRQ_INT1_CONNECT, "muic-connect" },
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{ SM5504_IRQ_INT1_ADC_CHG, "muic-adc-chg" },
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{ SM5504_IRQ_INT2_RID_CHG, "muic-rid-chg" },
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{ SM5504_IRQ_INT2_UVLO, "muic-uvlo" },
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{ SM5504_IRQ_INT2_POR, "muic-por" },
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{ SM5504_IRQ_INT2_OVP_FET, "muic-ovp-fet" },
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{ SM5504_IRQ_INT2_OCP_LATCH, "muic-ocp-latch" },
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{ SM5504_IRQ_INT2_OCP_EVENT, "muic-ocp-event" },
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{ SM5504_IRQ_INT2_OVP_OCP_EVENT, "muic-ovp-ocp-event" },
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};
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/* Define interrupt list of SM5504 to register regmap_irq */
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static const struct regmap_irq sm5504_irqs[] = {
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/* INT1 interrupts */
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{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_ATTACH_MASK, },
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{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_DETACH_MASK, },
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{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_CHG_DET_MASK, },
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{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_DCD_OUT_MASK, },
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{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_OVP_MASK, },
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{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_CONNECT_MASK, },
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{ .reg_offset = 0, .mask = SM5504_IRQ_INT1_ADC_CHG_MASK, },
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/* INT2 interrupts */
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{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_RID_CHG_MASK,},
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{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_UVLO_MASK, },
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{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_POR_MASK, },
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{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_OVP_FET_MASK, },
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{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_OCP_LATCH_MASK, },
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{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_OCP_EVENT_MASK, },
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{ .reg_offset = 1, .mask = SM5504_IRQ_INT2_OVP_OCP_EVENT_MASK, },
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};
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static const struct regmap_irq_chip sm5504_muic_irq_chip = {
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.name = "sm5504",
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.status_base = SM5502_REG_INT1,
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.mask_base = SM5502_REG_INTMASK1,
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.mask_invert = false,
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.num_regs = 2,
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.irqs = sm5504_irqs,
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.num_irqs = ARRAY_SIZE(sm5504_irqs),
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};
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/* Define regmap configuration of SM5502 for I2C communication */
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static bool sm5502_muic_volatile_reg(struct device *dev, unsigned int reg)
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{
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@ -308,11 +385,9 @@ static unsigned int sm5502_muic_get_cable_type(struct sm5502_muic_info *info)
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return ret;
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}
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switch (dev_type1) {
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case SM5502_REG_DEV_TYPE1_USB_OTG_MASK:
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if (dev_type1 == info->type->otg_dev_type1) {
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cable_type = SM5502_MUIC_ADC_GROUND_USB_OTG;
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break;
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default:
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} else {
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dev_dbg(info->dev,
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"cannot identify the cable type: adc(0x%x), dev_type1(0x%x)\n",
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adc, dev_type1);
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@ -365,6 +440,11 @@ static unsigned int sm5502_muic_get_cable_type(struct sm5502_muic_info *info)
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return ret;
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}
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if (dev_type1 == info->type->otg_dev_type1) {
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cable_type = SM5502_MUIC_ADC_OPEN_USB_OTG;
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break;
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}
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switch (dev_type1) {
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case SM5502_REG_DEV_TYPE1_USB_SDP_MASK:
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cable_type = SM5502_MUIC_ADC_OPEN_USB;
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@ -372,9 +452,6 @@ static unsigned int sm5502_muic_get_cable_type(struct sm5502_muic_info *info)
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case SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK:
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cable_type = SM5502_MUIC_ADC_OPEN_TA;
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break;
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case SM5502_REG_DEV_TYPE1_USB_OTG_MASK:
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cable_type = SM5502_MUIC_ADC_OPEN_USB_OTG;
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break;
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default:
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dev_dbg(info->dev,
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"cannot identify the cable type: adc(0x%x)\n",
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@ -504,6 +581,34 @@ static int sm5502_parse_irq(struct sm5502_muic_info *info, int irq_type)
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return 0;
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}
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static int sm5504_parse_irq(struct sm5502_muic_info *info, int irq_type)
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{
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switch (irq_type) {
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case SM5504_IRQ_INT1_ATTACH:
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info->irq_attach = true;
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break;
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case SM5504_IRQ_INT1_DETACH:
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info->irq_detach = true;
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break;
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case SM5504_IRQ_INT1_CHG_DET:
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case SM5504_IRQ_INT1_DCD_OUT:
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case SM5504_IRQ_INT1_OVP_EVENT:
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case SM5504_IRQ_INT1_CONNECT:
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case SM5504_IRQ_INT1_ADC_CHG:
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case SM5504_IRQ_INT2_RID_CHG:
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case SM5504_IRQ_INT2_UVLO:
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case SM5504_IRQ_INT2_POR:
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case SM5504_IRQ_INT2_OVP_FET:
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case SM5504_IRQ_INT2_OCP_LATCH:
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case SM5504_IRQ_INT2_OCP_EVENT:
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case SM5504_IRQ_INT2_OVP_OCP_EVENT:
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default:
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break;
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}
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return 0;
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}
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static irqreturn_t sm5502_muic_irq_handler(int irq, void *data)
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{
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struct sm5502_muic_info *info = data;
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@ -676,11 +781,23 @@ static const struct sm5502_type sm5502_data = {
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.irq_chip = &sm5502_muic_irq_chip,
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.reg_data = sm5502_reg_data,
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.num_reg_data = ARRAY_SIZE(sm5502_reg_data),
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.otg_dev_type1 = SM5502_REG_DEV_TYPE1_USB_OTG_MASK,
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.parse_irq = sm5502_parse_irq,
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};
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static const struct sm5502_type sm5504_data = {
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.muic_irqs = sm5504_muic_irqs,
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.num_muic_irqs = ARRAY_SIZE(sm5504_muic_irqs),
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.irq_chip = &sm5504_muic_irq_chip,
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.reg_data = sm5504_reg_data,
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.num_reg_data = ARRAY_SIZE(sm5504_reg_data),
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.otg_dev_type1 = SM5504_REG_DEV_TYPE1_USB_OTG_MASK,
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.parse_irq = sm5504_parse_irq,
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};
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static const struct of_device_id sm5502_dt_match[] = {
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{ .compatible = "siliconmitus,sm5502-muic", .data = &sm5502_data },
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{ .compatible = "siliconmitus,sm5504-muic", .data = &sm5504_data },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sm5502_dt_match);
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@ -712,6 +829,7 @@ static SIMPLE_DEV_PM_OPS(sm5502_muic_pm_ops,
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static const struct i2c_device_id sm5502_i2c_id[] = {
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{ "sm5502", (kernel_ulong_t)&sm5502_data },
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{ "sm5504", (kernel_ulong_t)&sm5504_data },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, sm5502_i2c_id);
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@ -89,6 +89,13 @@ enum sm5502_reg {
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#define SM5502_REG_CONTROL_RAW_DATA_MASK (0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT)
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#define SM5502_REG_CONTROL_SW_OPEN_MASK (0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT)
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#define SM5504_REG_CONTROL_CHGTYP_SHIFT 5
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#define SM5504_REG_CONTROL_USBCHDEN_SHIFT 6
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#define SM5504_REG_CONTROL_ADC_EN_SHIFT 7
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#define SM5504_REG_CONTROL_CHGTYP_MASK (0x1 << SM5504_REG_CONTROL_CHGTYP_SHIFT)
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#define SM5504_REG_CONTROL_USBCHDEN_MASK (0x1 << SM5504_REG_CONTROL_USBCHDEN_SHIFT)
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#define SM5504_REG_CONTROL_ADC_EN_MASK (0x1 << SM5504_REG_CONTROL_ADC_EN_SHIFT)
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#define SM5502_REG_INTM1_ATTACH_SHIFT 0
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#define SM5502_REG_INTM1_DETACH_SHIFT 1
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#define SM5502_REG_INTM1_KP_SHIFT 2
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@ -119,6 +126,36 @@ enum sm5502_reg {
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#define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT)
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#define SM5502_REG_INTM2_MHL_MASK (0x1 << SM5502_REG_INTM2_MHL_SHIFT)
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#define SM5504_REG_INTM1_ATTACH_SHIFT 0
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#define SM5504_REG_INTM1_DETACH_SHIFT 1
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#define SM5504_REG_INTM1_CHG_DET_SHIFT 2
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#define SM5504_REG_INTM1_DCD_OUT_SHIFT 3
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#define SM5504_REG_INTM1_OVP_EVENT_SHIFT 4
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#define SM5504_REG_INTM1_CONNECT_SHIFT 5
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#define SM5504_REG_INTM1_ADC_CHG_SHIFT 6
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#define SM5504_REG_INTM1_ATTACH_MASK (0x1 << SM5504_REG_INTM1_ATTACH_SHIFT)
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#define SM5504_REG_INTM1_DETACH_MASK (0x1 << SM5504_REG_INTM1_DETACH_SHIFT)
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#define SM5504_REG_INTM1_CHG_DET_MASK (0x1 << SM5504_REG_INTM1_CHG_DET_SHIFT)
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#define SM5504_REG_INTM1_DCD_OUT_MASK (0x1 << SM5504_REG_INTM1_DCD_OUT_SHIFT)
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#define SM5504_REG_INTM1_OVP_EVENT_MASK (0x1 << SM5504_REG_INTM1_OVP_EVENT_SHIFT)
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#define SM5504_REG_INTM1_CONNECT_MASK (0x1 << SM5504_REG_INTM1_CONNECT_SHIFT)
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#define SM5504_REG_INTM1_ADC_CHG_MASK (0x1 << SM5504_REG_INTM1_ADC_CHG_SHIFT)
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#define SM5504_REG_INTM2_RID_CHG_SHIFT 0
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#define SM5504_REG_INTM2_UVLO_SHIFT 1
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#define SM5504_REG_INTM2_POR_SHIFT 2
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#define SM5504_REG_INTM2_OVP_FET_SHIFT 4
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#define SM5504_REG_INTM2_OCP_LATCH_SHIFT 5
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#define SM5504_REG_INTM2_OCP_EVENT_SHIFT 6
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#define SM5504_REG_INTM2_OVP_OCP_EVENT_SHIFT 7
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#define SM5504_REG_INTM2_RID_CHG_MASK (0x1 << SM5504_REG_INTM2_RID_CHG_SHIFT)
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#define SM5504_REG_INTM2_UVLO_MASK (0x1 << SM5504_REG_INTM2_UVLO_SHIFT)
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#define SM5504_REG_INTM2_POR_MASK (0x1 << SM5504_REG_INTM2_POR_SHIFT)
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#define SM5504_REG_INTM2_OVP_FET_MASK (0x1 << SM5504_REG_INTM2_OVP_FET_SHIFT)
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#define SM5504_REG_INTM2_OCP_LATCH_MASK (0x1 << SM5504_REG_INTM2_OCP_LATCH_SHIFT)
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#define SM5504_REG_INTM2_OCP_EVENT_MASK (0x1 << SM5504_REG_INTM2_OCP_EVENT_SHIFT)
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#define SM5504_REG_INTM2_OVP_OCP_EVENT_MASK (0x1 << SM5504_REG_INTM2_OVP_OCP_EVENT_SHIFT)
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#define SM5502_REG_ADC_SHIFT 0
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#define SM5502_REG_ADC_MASK (0x1f << SM5502_REG_ADC_SHIFT)
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@ -195,6 +232,9 @@ enum sm5502_reg {
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#define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT)
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#define SM5502_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT)
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#define SM5504_REG_DEV_TYPE1_USB_OTG_SHIFT 0
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#define SM5504_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5504_REG_DEV_TYPE1_USB_OTG_SHIFT)
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#define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT 0
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#define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT 1
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#define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT 2
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@ -273,4 +313,42 @@ enum sm5502_irq {
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#define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK BIT(4)
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#define SM5502_IRQ_INT2_MHL_MASK BIT(5)
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/* SM5504 Interrupts */
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enum sm5504_irq {
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/* INT1 */
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SM5504_IRQ_INT1_ATTACH,
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SM5504_IRQ_INT1_DETACH,
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SM5504_IRQ_INT1_CHG_DET,
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SM5504_IRQ_INT1_DCD_OUT,
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SM5504_IRQ_INT1_OVP_EVENT,
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SM5504_IRQ_INT1_CONNECT,
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SM5504_IRQ_INT1_ADC_CHG,
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/* INT2 */
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SM5504_IRQ_INT2_RID_CHG,
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SM5504_IRQ_INT2_UVLO,
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SM5504_IRQ_INT2_POR,
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SM5504_IRQ_INT2_OVP_FET,
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SM5504_IRQ_INT2_OCP_LATCH,
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SM5504_IRQ_INT2_OCP_EVENT,
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SM5504_IRQ_INT2_OVP_OCP_EVENT,
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SM5504_IRQ_NUM,
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};
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#define SM5504_IRQ_INT1_ATTACH_MASK BIT(0)
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#define SM5504_IRQ_INT1_DETACH_MASK BIT(1)
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#define SM5504_IRQ_INT1_CHG_DET_MASK BIT(2)
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#define SM5504_IRQ_INT1_DCD_OUT_MASK BIT(3)
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#define SM5504_IRQ_INT1_OVP_MASK BIT(4)
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#define SM5504_IRQ_INT1_CONNECT_MASK BIT(5)
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#define SM5504_IRQ_INT1_ADC_CHG_MASK BIT(6)
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#define SM5504_IRQ_INT2_RID_CHG_MASK BIT(0)
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#define SM5504_IRQ_INT2_UVLO_MASK BIT(1)
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#define SM5504_IRQ_INT2_POR_MASK BIT(2)
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#define SM5504_IRQ_INT2_OVP_FET_MASK BIT(4)
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#define SM5504_IRQ_INT2_OCP_LATCH_MASK BIT(5)
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#define SM5504_IRQ_INT2_OCP_EVENT_MASK BIT(6)
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#define SM5504_IRQ_INT2_OVP_OCP_EVENT_MASK BIT(7)
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#endif /* __LINUX_EXTCON_SM5502_H */
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