ARM: entry: re-allocate registers in irq entry assembly macros

This avoids the irq entry assembly corrupting r5, thereby allowing it
to be preserved through to the svc exit code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2011-06-26 10:34:02 +01:00
parent f2741b78b6
commit d9600c99c5
2 changed files with 12 additions and 12 deletions

View File

@ -4,8 +4,8 @@
* Interrupt handling. Preserves r7, r8, r9
*/
.macro arch_irq_handler_default
get_irqnr_preamble r5, lr
1: get_irqnr_and_base r0, r6, r5, lr
get_irqnr_preamble r6, lr
1: get_irqnr_and_base r0, r2, r6, lr
movne r1, sp
@
@ routine called with r0 = irq number, r1 = struct pt_regs *
@ -17,17 +17,17 @@
/*
* XXX
*
* this macro assumes that irqstat (r6) and base (r5) are
* this macro assumes that irqstat (r2) and base (r6) are
* preserved from get_irqnr_and_base above
*/
ALT_SMP(test_for_ipi r0, r6, r5, lr)
ALT_SMP(test_for_ipi r0, r2, r6, lr)
ALT_UP_B(9997f)
movne r1, sp
adrne lr, BSYM(1b)
bne do_IPI
#ifdef CONFIG_LOCAL_TIMERS
test_for_ltirq r0, r6, r5, lr
test_for_ltirq r0, r2, r6, lr
movne r0, sp
adrne lr, BSYM(1b)
bne do_local_timer
@ -40,7 +40,7 @@
.align 5
.global \symbol_name
\symbol_name:
mov r4, lr
mov r8, lr
arch_irq_handler_default
mov pc, r4
mov pc, r8
.endm

View File

@ -29,16 +29,16 @@
#include <asm/entry-macro-multi.S>
/*
* Interrupt handling. Preserves r7, r8, r9
* Interrupt handling.
*/
.macro irq_handler
#ifdef CONFIG_MULTI_IRQ_HANDLER
ldr r5, =handle_arch_irq
ldr r1, =handle_arch_irq
mov r0, sp
ldr r5, [r5]
ldr r1, [r1]
adr lr, BSYM(9997f)
teq r5, #0
movne pc, r5
teq r1, #0
movne pc, r1
#endif
arch_irq_handler_default
9997: