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riscv: kprobes: simulate c.beqz and c.bnez
kprobes currently rejects instruction c.beqz and c.bnez. Implement them. Signed-off-by: Nam Cao <namcaov@gmail.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/1d879dba4e4ee9a82e27625d6483b5c9cfed684f.1690704360.git.namcaov@gmail.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -30,13 +30,13 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)
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*/
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#ifdef CONFIG_RISCV_ISA_C
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RISCV_INSN_REJECTED(c_jal, insn);
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RISCV_INSN_REJECTED(c_beqz, insn);
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RISCV_INSN_REJECTED(c_bnez, insn);
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RISCV_INSN_REJECTED(c_ebreak, insn);
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RISCV_INSN_SET_SIMULATE(c_j, insn);
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RISCV_INSN_SET_SIMULATE(c_jr, insn);
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RISCV_INSN_SET_SIMULATE(c_jalr, insn);
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RISCV_INSN_SET_SIMULATE(c_beqz, insn);
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RISCV_INSN_SET_SIMULATE(c_bnez, insn);
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#endif
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RISCV_INSN_SET_SIMULATE(jal, insn);
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@ -249,3 +249,47 @@ bool __kprobes simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *r
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{
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return simulate_c_jr_jalr(opcode, addr, regs, true);
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}
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static bool __kprobes simulate_c_bnez_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs,
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bool is_bnez)
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{
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/*
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* 15 13 12 10 9 7 6 2 1 0
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* | funct3 | offset[8|4:3] | rs1' | offset[7:6|2:1|5] | op |
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* 3 3 3 5 2
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*/
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s32 offset;
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u32 rs1;
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unsigned long rs1_val;
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rs1 = 0x8 | ((opcode >> 7) & 0x7);
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if (!rv_insn_reg_get_val(regs, rs1, &rs1_val))
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return false;
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if ((rs1_val != 0 && is_bnez) || (rs1_val == 0 && !is_bnez)) {
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offset = ((opcode >> 3) & 0x3) << 1;
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offset |= ((opcode >> 10) & 0x3) << 3;
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offset |= ((opcode >> 2) & 0x1) << 5;
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offset |= ((opcode >> 5) & 0x3) << 6;
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offset |= ((opcode >> 12) & 0x1) << 8;
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offset = sign_extend32(offset, 8);
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} else {
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offset = 2;
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}
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instruction_pointer_set(regs, addr + offset);
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return true;
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}
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bool __kprobes simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs)
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{
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return simulate_c_bnez_beqz(opcode, addr, regs, true);
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}
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bool __kprobes simulate_c_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs)
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{
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return simulate_c_bnez_beqz(opcode, addr, regs, false);
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}
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@ -27,5 +27,7 @@ bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_c_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs);
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#endif /* _RISCV_KERNEL_PROBES_SIMULATE_INSN_H */
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