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Merge series "Add Renesas RPC-IF support" from Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>:
Hello! Here's a set of 2 patches against Linus' repo. Renesas Reduced Pin Count Interface (RPC-IF) allows a SPI flash or HyperFlash connected to the SoC to be accessed via the external address space read mode or the manual mode. The memory controller driver for RPC-IF registers either SPI or HyperFLash subdevice, depending on the contents of the device tree subnode; it also provides the abstract "back end" API that can be used by the "front end" SPI/MTD drivers to talk to the real hardware... Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>. [1/2] dt-bindings: memory: document Renesas RPC-IF bindings [2/2] memory: add Renesas RPC-IF driver MBR, Sergei
This commit is contained in:
Mark Brown
commit
d93529962d
@ -0,0 +1,88 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas Reduced Pin Count Interface (RPC-IF)
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maintainers:
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- Sergei Shtylyov <sergei.shtylyov@gmail.com>
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description: |
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Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
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be accessed via the external address space read mode or the manual mode.
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The flash chip itself should be represented by a subnode of the RPC-IF node.
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The flash interface is selected based on the "compatible" property of this
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subnode:
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- if it contains "jedec,spi-nor", then SPI is used;
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- if it contains "cfi-flash", then HyperFlash is used.
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allOf:
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- $ref: "/schemas/spi/spi-controller.yaml#"
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properties:
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compatible:
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items:
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- enum:
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- renesas,r8a77970-rpc-if # R-Car V3M
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- renesas,r8a77980-rpc-if # R-Car V3H
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- renesas,r8a77995-rpc-if # R-Car D3
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- const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 device
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reg:
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items:
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- description: RPC-IF registers
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- description: direct mapping read mode area
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- description: write buffer area
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reg-names:
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items:
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- const: regs
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- const: dirmap
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- const: wbuf
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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patternProperties:
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"flash@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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enum:
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- cfi-flash
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- jedec,spi-nor
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examples:
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- |
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include <dt-bindings/power/r8a77995-sysc.h>
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spi@ee200000 {
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compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if";
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reg = <0xee200000 0x200>,
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<0x08000000 0x4000000>,
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<0xee208000 0x100>;
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reg-names = "regs", "dirmap", "wbuf";
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clocks = <&cpg CPG_MOD 917>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 917>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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@ -174,6 +174,15 @@ config PL353_SMC
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This driver is for the ARM PL351/PL353 Static Memory
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Controller(SMC) module.
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config RENESAS_RPCIF
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tristate "Renesas RPC-IF driver"
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depends on ARCH_RENESAS
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select REGMAP_MMIO
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help
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This supports Renesas R-Car Gen3 RPC-IF which provides either SPI
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host or HyperFlash. You'll have to select individual components
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under the corresponding menu.
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source "drivers/memory/samsung/Kconfig"
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source "drivers/memory/tegra/Kconfig"
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@ -22,6 +22,7 @@ obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o
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obj-$(CONFIG_MTK_SMI) += mtk-smi.o
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obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
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obj-$(CONFIG_PL353_SMC) += pl353-smc.o
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obj-$(CONFIG_RENESAS_RPCIF) += renesas-rpc-if.o
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obj-$(CONFIG_SAMSUNG_MC) += samsung/
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obj-$(CONFIG_TEGRA_MC) += tegra/
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603
drivers/memory/renesas-rpc-if.c
Normal file
603
drivers/memory/renesas-rpc-if.c
Normal file
@ -0,0 +1,603 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RPC-IF core driver
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*
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* Copyright (C) 2018-2019 Renesas Solutions Corp.
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* Copyright (C) 2019 Macronix International Co., Ltd.
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* Copyright (C) 2019-2020 Cogent Embedded, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <memory/renesas-rpc-if.h>
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#define RPCIF_CMNCR 0x0000 /* R/W */
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#define RPCIF_CMNCR_MD BIT(31)
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#define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */
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#define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
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#define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
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#define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
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#define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
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#define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \
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RPCIF_CMNCR_MOIIO1(3) | \
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RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
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#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
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#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
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#define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
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#define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
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RPCIF_CMNCR_IO3FV(3))
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#define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
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#define RPCIF_SSLDR 0x0004 /* R/W */
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#define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
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#define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
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#define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
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#define RPCIF_DRCR 0x000C /* R/W */
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#define RPCIF_DRCR_SSLN BIT(24)
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#define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
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#define RPCIF_DRCR_RCF BIT(9)
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#define RPCIF_DRCR_RBE BIT(8)
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#define RPCIF_DRCR_SSLE BIT(0)
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#define RPCIF_DRCMR 0x0010 /* R/W */
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#define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
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#define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
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#define RPCIF_DREAR 0x0014 /* R/W */
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#define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
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#define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
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#define RPCIF_DROPR 0x0018 /* R/W */
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#define RPCIF_DRENR 0x001C /* R/W */
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#define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
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#define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
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#define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
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#define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
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#define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
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#define RPCIF_DRENR_DME BIT(15)
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#define RPCIF_DRENR_CDE BIT(14)
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#define RPCIF_DRENR_OCDE BIT(12)
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#define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
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#define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
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#define RPCIF_SMCR 0x0020 /* R/W */
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#define RPCIF_SMCR_SSLKP BIT(8)
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#define RPCIF_SMCR_SPIRE BIT(2)
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#define RPCIF_SMCR_SPIWE BIT(1)
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#define RPCIF_SMCR_SPIE BIT(0)
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#define RPCIF_SMCMR 0x0024 /* R/W */
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#define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
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#define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
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#define RPCIF_SMADR 0x0028 /* R/W */
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#define RPCIF_SMOPR 0x002C /* R/W */
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#define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
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#define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
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#define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
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#define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
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#define RPCIF_SMENR 0x0030 /* R/W */
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#define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
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#define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
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#define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
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#define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
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#define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
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#define RPCIF_SMENR_DME BIT(15)
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#define RPCIF_SMENR_CDE BIT(14)
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#define RPCIF_SMENR_OCDE BIT(12)
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#define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
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#define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
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#define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
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#define RPCIF_SMRDR0 0x0038 /* R */
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#define RPCIF_SMRDR1 0x003C /* R */
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#define RPCIF_SMWDR0 0x0040 /* W */
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#define RPCIF_SMWDR1 0x0044 /* W */
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#define RPCIF_CMNSR 0x0048 /* R */
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#define RPCIF_CMNSR_SSLF BIT(1)
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#define RPCIF_CMNSR_TEND BIT(0)
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#define RPCIF_DRDMCR 0x0058 /* R/W */
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#define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
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#define RPCIF_DRDRENR 0x005C /* R/W */
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#define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
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#define RPCIF_DRDRENR_ADDRE BIT(8)
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#define RPCIF_DRDRENR_OPDRE BIT(4)
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#define RPCIF_DRDRENR_DRDRE BIT(0)
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#define RPCIF_SMDMCR 0x0060 /* R/W */
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#define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
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#define RPCIF_SMDRENR 0x0064 /* R/W */
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#define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
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#define RPCIF_SMDRENR_ADDRE BIT(8)
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#define RPCIF_SMDRENR_OPDRE BIT(4)
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#define RPCIF_SMDRENR_SPIDRE BIT(0)
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#define RPCIF_PHYCNT 0x007C /* R/W */
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#define RPCIF_PHYCNT_CAL BIT(31)
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#define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
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#define RPCIF_PHYCNT_EXDS BIT(21)
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#define RPCIF_PHYCNT_OCT BIT(20)
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#define RPCIF_PHYCNT_DDRCAL BIT(19)
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#define RPCIF_PHYCNT_HS BIT(18)
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#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
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#define RPCIF_PHYCNT_WBUF2 BIT(4)
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#define RPCIF_PHYCNT_WBUF BIT(2)
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#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
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#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
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#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
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#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
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#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
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#define RPCIF_PHYINT 0x0088 /* R/W */
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#define RPCIF_PHYINT_WPVAL BIT(1)
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#define RPCIF_DIRMAP_SIZE 0x4000000
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static const struct regmap_range rpcif_volatile_ranges[] = {
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regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
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regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
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regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
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};
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static const struct regmap_access_table rpcif_volatile_table = {
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.yes_ranges = rpcif_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
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};
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static const struct regmap_config rpcif_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.fast_io = true,
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.max_register = RPCIF_PHYINT,
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.volatile_table = &rpcif_volatile_table,
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};
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int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res;
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void __iomem *base;
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rpc->dev = dev;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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rpc->regmap = devm_regmap_init_mmio(&pdev->dev, base,
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&rpcif_regmap_config);
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if (IS_ERR(rpc->regmap)) {
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dev_err(&pdev->dev,
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"failed to init regmap for rpcif, error %ld\n",
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PTR_ERR(rpc->regmap));
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return PTR_ERR(rpc->regmap);
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
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rpc->size = resource_size(res);
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rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(rpc->dirmap))
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rpc->dirmap = NULL;
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rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(rpc->rstc))
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return PTR_ERR(rpc->rstc);
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return 0;
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}
|
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EXPORT_SYMBOL(rpcif_sw_init);
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void rpcif_enable_rpm(struct rpcif *rpc)
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{
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pm_runtime_enable(rpc->dev);
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}
|
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EXPORT_SYMBOL(rpcif_enable_rpm);
|
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void rpcif_disable_rpm(struct rpcif *rpc)
|
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{
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pm_runtime_put_sync(rpc->dev);
|
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}
|
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EXPORT_SYMBOL(rpcif_disable_rpm);
|
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|
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void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
|
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{
|
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u32 dummy;
|
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pm_runtime_get_sync(rpc->dev);
|
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/*
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* NOTE: The 0x260 are undocumented bits, but they must be set.
|
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* RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
|
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* 0x0 : the delay is biggest,
|
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* 0x1 : the delay is 2nd biggest,
|
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* On H3 ES1.x, the value should be 0, while on others,
|
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* the value should be 7.
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*/
|
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regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
|
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RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
|
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|
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/*
|
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* NOTE: The 0x1511144 are undocumented bits, but they must be set
|
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* for RPCIF_PHYOFFSET1.
|
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* The 0x31 are undocumented bits, but they must be set
|
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* for RPCIF_PHYOFFSET2.
|
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*/
|
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regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 |
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RPCIF_PHYOFFSET1_DDRTMG(3));
|
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regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 |
|
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RPCIF_PHYOFFSET2_OCTTMG(4));
|
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|
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if (hyperflash)
|
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regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
|
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RPCIF_PHYINT_WPVAL, 0);
|
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|
||||
regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
|
||||
RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
|
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RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
|
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/* Set RCF after BSZ update */
|
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regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
|
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/* Dummy read according to spec */
|
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regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
|
||||
regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
|
||||
RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
|
||||
|
||||
pm_runtime_put(rpc->dev);
|
||||
|
||||
rpc->bus_size = hyperflash ? 2 : 1;
|
||||
}
|
||||
EXPORT_SYMBOL(rpcif_hw_init);
|
||||
|
||||
static int wait_msg_xfer_end(struct rpcif *rpc)
|
||||
{
|
||||
u32 sts;
|
||||
|
||||
return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
|
||||
sts & RPCIF_CMNSR_TEND, 0,
|
||||
USEC_PER_SEC);
|
||||
}
|
||||
|
||||
static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
|
||||
{
|
||||
if (rpc->bus_size == 2)
|
||||
nbytes /= 2;
|
||||
nbytes = clamp(nbytes, 1U, 4U);
|
||||
return GENMASK(3, 4 - nbytes);
|
||||
}
|
||||
|
||||
static u8 rpcif_bit_size(u8 buswidth)
|
||||
{
|
||||
return buswidth > 4 ? 2 : ilog2(buswidth);
|
||||
}
|
||||
|
||||
void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
|
||||
size_t *len)
|
||||
{
|
||||
rpc->smcr = 0;
|
||||
rpc->smadr = 0;
|
||||
rpc->enable = 0;
|
||||
rpc->command = 0;
|
||||
rpc->option = 0;
|
||||
rpc->dummy = 0;
|
||||
rpc->ddr = 0;
|
||||
rpc->xferlen = 0;
|
||||
|
||||
if (op->cmd.buswidth) {
|
||||
rpc->enable = RPCIF_SMENR_CDE |
|
||||
RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
|
||||
rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
|
||||
if (op->cmd.ddr)
|
||||
rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
|
||||
}
|
||||
if (op->ocmd.buswidth) {
|
||||
rpc->enable |= RPCIF_SMENR_OCDE |
|
||||
RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
|
||||
rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
|
||||
}
|
||||
|
||||
if (op->addr.buswidth) {
|
||||
rpc->enable |=
|
||||
RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
|
||||
if (op->addr.nbytes == 4)
|
||||
rpc->enable |= RPCIF_SMENR_ADE(0xF);
|
||||
else
|
||||
rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
|
||||
2, 3 - op->addr.nbytes));
|
||||
if (op->addr.ddr)
|
||||
rpc->ddr |= RPCIF_SMDRENR_ADDRE;
|
||||
|
||||
if (offs && len)
|
||||
rpc->smadr = *offs;
|
||||
else
|
||||
rpc->smadr = op->addr.val;
|
||||
}
|
||||
|
||||
if (op->dummy.buswidth) {
|
||||
rpc->enable |= RPCIF_SMENR_DME;
|
||||
rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
|
||||
op->dummy.buswidth);
|
||||
}
|
||||
|
||||
if (op->option.buswidth) {
|
||||
rpc->enable |= RPCIF_SMENR_OPDE(
|
||||
rpcif_bits_set(rpc, op->option.nbytes)) |
|
||||
RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
|
||||
if (op->option.ddr)
|
||||
rpc->ddr |= RPCIF_SMDRENR_OPDRE;
|
||||
rpc->option = op->option.val;
|
||||
}
|
||||
|
||||
rpc->dir = op->data.dir;
|
||||
if (op->data.buswidth) {
|
||||
u32 nbytes;
|
||||
|
||||
rpc->buffer = op->data.buf.in;
|
||||
switch (op->data.dir) {
|
||||
case RPCIF_DATA_IN:
|
||||
rpc->smcr = RPCIF_SMCR_SPIRE;
|
||||
break;
|
||||
case RPCIF_DATA_OUT:
|
||||
rpc->smcr = RPCIF_SMCR_SPIWE;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
if (op->data.ddr)
|
||||
rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
|
||||
|
||||
if (offs && len)
|
||||
nbytes = *len;
|
||||
else
|
||||
nbytes = op->data.nbytes;
|
||||
rpc->xferlen = nbytes;
|
||||
|
||||
rpc->enable |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)) |
|
||||
RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(rpcif_prepare);
|
||||
|
||||
int rpcif_manual_xfer(struct rpcif *rpc)
|
||||
{
|
||||
u32 smenr, smcr, pos = 0, max = 4;
|
||||
int ret = 0;
|
||||
|
||||
if (rpc->bus_size == 2)
|
||||
max = 8;
|
||||
|
||||
pm_runtime_get_sync(rpc->dev);
|
||||
|
||||
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
|
||||
RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
|
||||
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
|
||||
RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
|
||||
regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
|
||||
regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
|
||||
regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
|
||||
regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
|
||||
smenr = rpc->enable;
|
||||
|
||||
switch (rpc->dir) {
|
||||
case RPCIF_DATA_OUT:
|
||||
while (pos < rpc->xferlen) {
|
||||
u32 nbytes = rpc->xferlen - pos;
|
||||
u32 data[2];
|
||||
|
||||
smcr = rpc->smcr | RPCIF_SMCR_SPIE;
|
||||
if (nbytes > max) {
|
||||
nbytes = max;
|
||||
smcr |= RPCIF_SMCR_SSLKP;
|
||||
}
|
||||
|
||||
memcpy(data, rpc->buffer + pos, nbytes);
|
||||
if (nbytes > 4) {
|
||||
regmap_write(rpc->regmap, RPCIF_SMWDR1,
|
||||
data[0]);
|
||||
regmap_write(rpc->regmap, RPCIF_SMWDR0,
|
||||
data[1]);
|
||||
} else if (nbytes > 2) {
|
||||
regmap_write(rpc->regmap, RPCIF_SMWDR0,
|
||||
data[0]);
|
||||
} else {
|
||||
regmap_write(rpc->regmap, RPCIF_SMWDR0,
|
||||
data[0] << 16);
|
||||
}
|
||||
|
||||
regmap_write(rpc->regmap, RPCIF_SMADR,
|
||||
rpc->smadr + pos);
|
||||
regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
|
||||
regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
|
||||
ret = wait_msg_xfer_end(rpc);
|
||||
if (ret)
|
||||
goto err_out;
|
||||
|
||||
pos += nbytes;
|
||||
smenr = rpc->enable &
|
||||
~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
|
||||
}
|
||||
break;
|
||||
case RPCIF_DATA_IN:
|
||||
/*
|
||||
* RPC-IF spoils the data for the commands without an address
|
||||
* phase (like RDID) in the manual mode, so we'll have to work
|
||||
* around this issue by using the external address space read
|
||||
* mode instead.
|
||||
*/
|
||||
if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
|
||||
u32 dummy;
|
||||
|
||||
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
|
||||
RPCIF_CMNCR_MD, 0);
|
||||
regmap_write(rpc->regmap, RPCIF_DRCR,
|
||||
RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
|
||||
regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
|
||||
regmap_write(rpc->regmap, RPCIF_DREAR,
|
||||
RPCIF_DREAR_EAC(1));
|
||||
regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
|
||||
regmap_write(rpc->regmap, RPCIF_DRENR,
|
||||
smenr & ~RPCIF_SMENR_SPIDE(0xF));
|
||||
regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
|
||||
regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
|
||||
memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
|
||||
regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
|
||||
/* Dummy read according to spec */
|
||||
regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
|
||||
break;
|
||||
}
|
||||
while (pos < rpc->xferlen) {
|
||||
u32 nbytes = rpc->xferlen - pos;
|
||||
u32 data[2];
|
||||
|
||||
if (nbytes > max)
|
||||
nbytes = max;
|
||||
|
||||
regmap_write(rpc->regmap, RPCIF_SMADR,
|
||||
rpc->smadr + pos);
|
||||
regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
|
||||
regmap_write(rpc->regmap, RPCIF_SMCR,
|
||||
rpc->smcr | RPCIF_SMCR_SPIE);
|
||||
ret = wait_msg_xfer_end(rpc);
|
||||
if (ret)
|
||||
goto err_out;
|
||||
|
||||
if (nbytes > 4) {
|
||||
regmap_read(rpc->regmap, RPCIF_SMRDR1,
|
||||
&data[0]);
|
||||
regmap_read(rpc->regmap, RPCIF_SMRDR0,
|
||||
&data[1]);
|
||||
} else if (nbytes > 2) {
|
||||
regmap_read(rpc->regmap, RPCIF_SMRDR0,
|
||||
&data[0]);
|
||||
} else {
|
||||
regmap_read(rpc->regmap, RPCIF_SMRDR0,
|
||||
&data[0]);
|
||||
data[0] >>= 16;
|
||||
}
|
||||
memcpy(rpc->buffer + pos, data, nbytes);
|
||||
|
||||
pos += nbytes;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
|
||||
regmap_write(rpc->regmap, RPCIF_SMCR,
|
||||
rpc->smcr | RPCIF_SMCR_SPIE);
|
||||
ret = wait_msg_xfer_end(rpc);
|
||||
if (ret)
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
exit:
|
||||
pm_runtime_put(rpc->dev);
|
||||
return ret;
|
||||
|
||||
err_out:
|
||||
ret = reset_control_reset(rpc->rstc);
|
||||
rpcif_hw_init(rpc, rpc->bus_size == 2);
|
||||
goto exit;
|
||||
}
|
||||
EXPORT_SYMBOL(rpcif_manual_xfer);
|
||||
|
||||
ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
|
||||
{
|
||||
loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
|
||||
size_t size = RPCIF_DIRMAP_SIZE - from;
|
||||
|
||||
if (len > size)
|
||||
len = size;
|
||||
|
||||
pm_runtime_get_sync(rpc->dev);
|
||||
|
||||
regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
|
||||
regmap_write(rpc->regmap, RPCIF_DRCR, 0);
|
||||
regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
|
||||
regmap_write(rpc->regmap, RPCIF_DREAR,
|
||||
RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
|
||||
regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
|
||||
regmap_write(rpc->regmap, RPCIF_DRENR,
|
||||
rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
|
||||
regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
|
||||
regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
|
||||
|
||||
memcpy_fromio(buf, rpc->dirmap + from, len);
|
||||
|
||||
pm_runtime_put(rpc->dev);
|
||||
|
||||
return len;
|
||||
}
|
||||
EXPORT_SYMBOL(rpcif_dirmap_read);
|
||||
|
||||
static int rpcif_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct platform_device *vdev;
|
||||
struct device_node *flash;
|
||||
const char *name;
|
||||
|
||||
flash = of_get_next_child(pdev->dev.of_node, NULL);
|
||||
if (!flash) {
|
||||
dev_warn(&pdev->dev, "no flash node found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_device_is_compatible(flash, "jedec,spi-nor")) {
|
||||
name = "rpc-if-spi";
|
||||
} else if (of_device_is_compatible(flash, "cfi-flash")) {
|
||||
name = "rpc-if-hyperflash";
|
||||
} else {
|
||||
dev_warn(&pdev->dev, "unknown flash type\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
vdev = platform_device_alloc(name, pdev->id);
|
||||
if (!vdev)
|
||||
return -ENOMEM;
|
||||
vdev->dev.parent = &pdev->dev;
|
||||
platform_set_drvdata(pdev, vdev);
|
||||
return platform_device_add(vdev);
|
||||
}
|
||||
|
||||
static int rpcif_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct platform_device *vdev = platform_get_drvdata(pdev);
|
||||
|
||||
platform_device_unregister(vdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rpcif_of_match[] = {
|
||||
{ .compatible = "renesas,rcar-gen3-rpc-if", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rpcif_of_match);
|
||||
|
||||
static struct platform_driver rpcif_driver = {
|
||||
.probe = rpcif_probe,
|
||||
.remove = rpcif_remove,
|
||||
.driver = {
|
||||
.name = "rpc-if",
|
||||
.of_match_table = rpcif_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rpcif_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Renesas RPC-IF core driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
87
include/memory/renesas-rpc-if.h
Normal file
87
include/memory/renesas-rpc-if.h
Normal file
@ -0,0 +1,87 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Renesas RPC-IF core driver
|
||||
*
|
||||
* Copyright (C) 2018~2019 Renesas Solutions Corp.
|
||||
* Copyright (C) 2019 Macronix International Co., Ltd.
|
||||
* Copyright (C) 2019-2020 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __RENESAS_RPC_IF_H
|
||||
#define __RENESAS_RPC_IF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
enum rpcif_data_dir {
|
||||
RPCIF_NO_DATA,
|
||||
RPCIF_DATA_IN,
|
||||
RPCIF_DATA_OUT,
|
||||
};
|
||||
|
||||
struct rpcif_op {
|
||||
struct {
|
||||
u8 buswidth;
|
||||
u8 opcode;
|
||||
bool ddr;
|
||||
} cmd, ocmd;
|
||||
|
||||
struct {
|
||||
u8 nbytes;
|
||||
u8 buswidth;
|
||||
bool ddr;
|
||||
u64 val;
|
||||
} addr;
|
||||
|
||||
struct {
|
||||
u8 ncycles;
|
||||
u8 buswidth;
|
||||
} dummy;
|
||||
|
||||
struct {
|
||||
u8 nbytes;
|
||||
u8 buswidth;
|
||||
bool ddr;
|
||||
u32 val;
|
||||
} option;
|
||||
|
||||
struct {
|
||||
u8 buswidth;
|
||||
unsigned int nbytes;
|
||||
enum rpcif_data_dir dir;
|
||||
bool ddr;
|
||||
union {
|
||||
void *in;
|
||||
const void *out;
|
||||
} buf;
|
||||
} data;
|
||||
};
|
||||
|
||||
struct rpcif {
|
||||
struct device *dev;
|
||||
void __iomem *dirmap;
|
||||
struct regmap *regmap;
|
||||
struct reset_control *rstc;
|
||||
size_t size;
|
||||
enum rpcif_data_dir dir;
|
||||
u8 bus_size;
|
||||
void *buffer;
|
||||
u32 xferlen;
|
||||
u32 smcr;
|
||||
u32 smadr;
|
||||
u32 command; /* DRCMR or SMCMR */
|
||||
u32 option; /* DROPR or SMOPR */
|
||||
u32 enable; /* DRENR or SMENR */
|
||||
u32 dummy; /* DRDMCR or SMDMCR */
|
||||
u32 ddr; /* DRDRENR or SMDRENR */
|
||||
};
|
||||
|
||||
int rpcif_sw_init(struct rpcif *rpc, struct device *dev);
|
||||
void rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
|
||||
void rpcif_enable_rpm(struct rpcif *rpc);
|
||||
void rpcif_disable_rpm(struct rpcif *rpc);
|
||||
void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
|
||||
size_t *len);
|
||||
int rpcif_manual_xfer(struct rpcif *rpc);
|
||||
ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf);
|
||||
|
||||
#endif // __RENESAS_RPC_IF_H
|
||||
Loading…
Reference in New Issue
Block a user