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pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
The TDSELCTRL register is responsible for configuring the SDHI/MMC clock return path delay and may be adjusted by the bootloader. Retain the value across suspend/resume to prevent hardware instability after resume. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -5547,10 +5547,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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enum ioctrl_regs {
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POCCTRL,
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TDSELCTRL,
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};
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static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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[POCCTRL] = { 0xe6060380, },
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[TDSELCTRL] = { 0xe60603c0, },
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{ /* sentinel */ },
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};
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@ -5897,10 +5897,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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enum ioctrl_regs {
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POCCTRL,
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TDSELCTRL,
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};
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static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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[POCCTRL] = { 0xe6060380, },
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[TDSELCTRL] = { 0xe60603c0, },
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{ /* sentinel */ },
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};
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@ -5855,10 +5855,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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enum ioctrl_regs {
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POCCTRL,
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TDSELCTRL,
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};
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static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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[POCCTRL] = { 0xe6060380, },
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[TDSELCTRL] = { 0xe60603c0, },
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{ /* sentinel */ },
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};
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@ -6012,10 +6012,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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enum ioctrl_regs {
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POCCTRL,
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TDSELCTRL,
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};
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static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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[POCCTRL] = { 0xe6060380, },
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[TDSELCTRL] = { 0xe60603c0, },
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{ /* sentinel */ },
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};
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@ -2409,12 +2409,14 @@ enum ioctrl_regs {
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POCCTRL0,
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POCCTRL1,
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POCCTRL2,
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TDSELCTRL,
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};
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static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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[POCCTRL0] = { 0xe6060380 },
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[POCCTRL1] = { 0xe6060384 },
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[POCCTRL2] = { 0xe6060388 },
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[TDSELCTRL] = { 0xe60603c0, },
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{ /* sentinel */ },
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};
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@ -2832,6 +2832,7 @@ enum ioctrl_regs {
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POCCTRL1,
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POCCTRL2,
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POCCTRL3,
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TDSELCTRL,
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};
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static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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@ -2839,6 +2840,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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[POCCTRL1] = { 0xe6060384, },
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[POCCTRL2] = { 0xe6060388, },
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[POCCTRL3] = { 0xe606038c, },
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[TDSELCTRL] = { 0xe60603c0, },
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{ /* sentinel */ },
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};
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@ -4996,10 +4996,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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enum ioctrl_regs {
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POCCTRL0,
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TDSELCTRL,
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};
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static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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[POCCTRL0] = { 0xe6060380, },
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[TDSELCTRL] = { 0xe60603c0, },
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{ /* sentinel */ },
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};
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@ -2833,6 +2833,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
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return bit;
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}
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enum ioctrl_regs {
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TDSELCTRL,
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};
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static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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[TDSELCTRL] = { 0xe60603c0, },
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{ /* sentinel */ },
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};
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static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
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.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
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};
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@ -2852,6 +2861,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
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.nr_functions = ARRAY_SIZE(pinmux_functions),
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.cfg_regs = pinmux_config_regs,
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.ioctrl_regs = pinmux_ioctrl_regs,
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.pinmux_data = pinmux_data,
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.pinmux_data_size = ARRAY_SIZE(pinmux_data),
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