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clk: rockchip: fix mmc get phase

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If the mmc clock has no rate, it can be assumed to be constant.
In such case, there is no measurable phase shift. Just return 0
in this case instead of returning an error.

Fixes: 2760878662 ("clk: Bail out when calculating phase fails during clk registration")
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20200303192956.64410-1-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Jerome Brunet 2020-03-03 20:29:56 +01:00 committed by Stephen Boyd
parent c3944ec8c6
commit d894992502
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-mmc-phase.c
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@ -51,9 +51,9 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
u16 degrees;
u32 delay_num = 0;
/* See the comment for rockchip_mmc_set_phase below */
/* Constant signal, no measurable phase shift */
if (!rate)
return -EINVAL;
return 0;
raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);