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cxgb4: handle interrupt raised when FW crashes
Handle TIMER0INT when FW crashes. Check for PCIE_FW[FW_EVAL] and if it says "Device FW Crashed", then treat it as fatal. Else, non-fatal. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -4040,6 +4040,7 @@ static void cim_intr_handler(struct adapter *adapter)
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{ MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
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{ MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
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{ TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
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{ TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
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{ TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
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{ TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
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{ TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
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{ 0 }
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{ 0 }
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};
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};
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static const struct intr_info cim_upintr_info[] = {
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static const struct intr_info cim_upintr_info[] = {
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@ -4074,11 +4075,27 @@ static void cim_intr_handler(struct adapter *adapter)
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{ 0 }
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{ 0 }
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};
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};
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u32 val, fw_err;
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int fat;
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int fat;
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if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
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fw_err = t4_read_reg(adapter, PCIE_FW_A);
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if (fw_err & PCIE_FW_ERR_F)
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t4_report_fw_error(adapter);
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t4_report_fw_error(adapter);
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/* When the Firmware detects an internal error which normally
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* wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
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* in order to make sure the Host sees the Firmware Crash. So
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* if we have a Timer0 interrupt and don't see a Firmware Crash,
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* ignore the Timer0 interrupt.
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*/
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val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
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if (val & TIMER0INT_F)
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if (!(fw_err & PCIE_FW_ERR_F) ||
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(PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
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t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
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TIMER0INT_F);
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fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
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fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
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cim_intr_info) +
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cim_intr_info) +
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t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
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t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
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@ -1077,6 +1077,10 @@
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#define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
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#define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
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#define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U)
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#define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U)
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#define TIMER0INT_S 2
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#define TIMER0INT_V(x) ((x) << TIMER0INT_S)
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#define TIMER0INT_F TIMER0INT_V(1U)
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#define PREFDROPINT_S 1
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#define PREFDROPINT_S 1
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#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
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#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
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#define PREFDROPINT_F PREFDROPINT_V(1U)
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#define PREFDROPINT_F PREFDROPINT_V(1U)
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@ -3088,6 +3088,10 @@ struct fw_debug_cmd {
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#define FW_DEBUG_CMD_TYPE_G(x) \
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#define FW_DEBUG_CMD_TYPE_G(x) \
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(((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
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(((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
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enum pcie_fw_eval {
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PCIE_FW_EVAL_CRASH = 0,
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};
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#define PCIE_FW_ERR_S 31
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#define PCIE_FW_ERR_S 31
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#define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S)
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#define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S)
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#define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U)
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#define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U)
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