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Merge branch 'am65-cpsw-rx-dscp-prio-map'
Roger Quadros says: ==================== net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX Configure default DSCP to User Priority mapping registers as per: https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 and https://datatracker.ietf.org/doc/html/rfc8622#section-11 Also update Priority to Thread maping to be compliant with IEEE802.1Q-2014. Priority Code Point (PCP) 2 is higher priority than PCP 0 (Best Effort). PCP 1 (Background) is lower priority than PCP 0 (Best Effort). --- Changes in v4: - Updated default DSCP to User Priority mapping as per https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 and https://datatracker.ietf.org/doc/html/rfc8622#section-11 - Link to v3: https://lore.kernel.org/r/20241109-am65-cpsw-multi-rx-dscp-v3-0-1cfb76928490@kernel.org Changes in v3: - Added Reviewed-by tag to patch 1 - Added macros for DSCP PRI field size and DSCP PRI per register - Drop unnecessary readl() in am65_cpsw_port_set_dscp_map() - Link to v2: https://lore.kernel.org/r/20241107-am65-cpsw-multi-rx-dscp-v2-0-9e9cd1920035@kernel.org Changes in v2: - Updated references to more recent standard IEEE802.1Q-2014. - Dropped reference to web link which might change in the future. - Typo fix in commit log. - Link to v1: https://lore.kernel.org/r/20241105-am65-cpsw-multi-rx-dscp-v1-0-38db85333c88@kernel.org ==================== Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
d7ef9eeef0
@ -71,6 +71,8 @@
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#define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020
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#define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024
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#define AM65_CPSW_PORTN_REG_CTL 0x004
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#define AM65_CPSW_PORTN_REG_DSCP_MAP 0x120
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#define AM65_CPSW_PORTN_REG_SA_L 0x308
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#define AM65_CPSW_PORTN_REG_SA_H 0x30c
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#define AM65_CPSW_PORTN_REG_TS_CTL 0x310
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@ -94,6 +96,10 @@
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/* AM65_CPSW_PORT_REG_PRI_CTL */
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#define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8)
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/* AM65_CPSW_PN_REG_CTL */
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#define AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN BIT(1)
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#define AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN BIT(2)
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/* AM65_CPSW_PN_TS_CTL register fields */
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#define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4)
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#define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5)
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@ -176,6 +182,99 @@ static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave,
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writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L);
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}
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#define AM65_CPSW_DSCP_MAX GENMASK(5, 0)
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#define AM65_CPSW_PRI_MAX GENMASK(2, 0)
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#define AM65_CPSW_DSCP_PRI_PER_REG 8
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#define AM65_CPSW_DSCP_PRI_SIZE 4 /* in bits */
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static int am65_cpsw_port_set_dscp_map(struct am65_cpsw_port *slave, u8 dscp, u8 pri)
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{
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int reg_ofs;
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int bit_ofs;
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u32 val;
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if (dscp > AM65_CPSW_DSCP_MAX)
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return -EINVAL;
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if (pri > AM65_CPSW_PRI_MAX)
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return -EINVAL;
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/* 32-bit register offset to this dscp */
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reg_ofs = (dscp / AM65_CPSW_DSCP_PRI_PER_REG) * 4;
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/* bit field offset to this dscp */
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bit_ofs = AM65_CPSW_DSCP_PRI_SIZE * (dscp % AM65_CPSW_DSCP_PRI_PER_REG);
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val = readl(slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs);
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val &= ~(AM65_CPSW_PRI_MAX << bit_ofs); /* clear */
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val |= pri << bit_ofs; /* set */
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writel(val, slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs);
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return 0;
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}
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static void am65_cpsw_port_enable_dscp_map(struct am65_cpsw_port *slave)
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{
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int dscp, pri;
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u32 val;
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/* Default DSCP to User Priority mapping as per:
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* https://datatracker.ietf.org/doc/html/rfc8325#section-4.3
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* and
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* https://datatracker.ietf.org/doc/html/rfc8622#section-11
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*/
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for (dscp = 0; dscp <= AM65_CPSW_DSCP_MAX; dscp++) {
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switch (dscp) {
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case 56: /* CS7 */
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case 48: /* CS6 */
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pri = 7;
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break;
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case 46: /* EF */
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case 44: /* VA */
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pri = 6;
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break;
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case 40: /* CS5 */
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pri = 5;
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break;
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case 34: /* AF41 */
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case 36: /* AF42 */
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case 38: /* AF43 */
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case 32: /* CS4 */
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case 26: /* AF31 */
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case 28: /* AF32 */
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case 30: /* AF33 */
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case 24: /* CS3 */
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pri = 4;
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break;
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case 18: /* AF21 */
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case 20: /* AF22 */
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case 22: /* AF23 */
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pri = 3;
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break;
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case 16: /* CS2 */
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case 10: /* AF11 */
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case 12: /* AF12 */
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case 14: /* AF13 */
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case 0: /* DF */
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pri = 0;
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break;
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case 8: /* CS1 */
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case 1: /* LE */
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pri = 1;
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break;
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default:
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pri = 0;
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break;
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}
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am65_cpsw_port_set_dscp_map(slave, dscp, pri);
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}
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/* enable port IPV4 and IPV6 DSCP for this port */
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val = readl(slave->port_base + AM65_CPSW_PORTN_REG_CTL);
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val |= AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN |
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AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN;
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writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL);
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}
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static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port)
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{
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cpsw_sl_reset(port->slave.mac_sl, 100);
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@ -916,6 +1015,7 @@ static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev)
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common->usage_count++;
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am65_cpsw_port_set_sl_mac(port, ndev->dev_addr);
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am65_cpsw_port_enable_dscp_map(port);
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if (common->is_emac_mode)
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am65_cpsw_init_port_emac_ale(port);
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@ -1704,26 +1704,34 @@ static void cpsw_ale_policer_reset(struct cpsw_ale *ale)
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void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch)
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{
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int pri, idx;
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/* IEEE802.1D-2004, Standard for Local and metropolitan area networks
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* Table G-2 - Traffic type acronyms
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* Table G-3 - Defining traffic types
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* User priority values 1 and 2 effectively communicate a lower
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* priority than 0. In the below table 0 is assigned to higher priority
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* thread than 1 and 2 wherever possible.
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* The below table maps which thread the user priority needs to be
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/* Reference:
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* IEEE802.1Q-2014, Standard for Local and metropolitan area networks
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* Table I-2 - Traffic type acronyms
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* Table I-3 - Defining traffic types
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* Section I.4 Traffic types and priority values, states:
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* "0 is thus used both for default priority and for Best Effort, and
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* Background is associated with a priority value of 1. This means
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* that the value 1 effectively communicates a lower priority than 0."
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*
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* In the table below, Priority Code Point (PCP) 0 is assigned
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* to a higher priority thread than PCP 1 wherever possible.
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* The table maps which thread the PCP traffic needs to be
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* sent to for a given number of threads (RX channels). Upper threads
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* have higher priority.
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* e.g. if number of threads is 8 then user priority 0 will map to
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* pri_thread_map[8-1][0] i.e. thread 2
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* pri_thread_map[8-1][0] i.e. thread 1
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*/
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int pri_thread_map[8][8] = { { 0, 0, 0, 0, 0, 0, 0, 0, },
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int pri_thread_map[8][8] = { /* BK,BE,EE,CA,VI,VO,IC,NC */
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{ 0, 0, 0, 0, 0, 0, 0, 0, },
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{ 0, 0, 0, 0, 1, 1, 1, 1, },
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{ 0, 0, 0, 0, 1, 1, 2, 2, },
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{ 1, 0, 0, 1, 2, 2, 3, 3, },
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{ 1, 0, 0, 1, 2, 3, 4, 4, },
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{ 1, 0, 0, 2, 3, 4, 5, 5, },
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{ 1, 0, 0, 2, 3, 4, 5, 6, },
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{ 2, 0, 1, 3, 4, 5, 6, 7, } };
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{ 0, 0, 1, 1, 2, 2, 3, 3, },
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{ 0, 0, 1, 1, 2, 2, 3, 4, },
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{ 1, 0, 2, 2, 3, 3, 4, 5, },
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{ 1, 0, 2, 3, 4, 4, 5, 6, },
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{ 1, 0, 2, 3, 4, 5, 6, 7 } };
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cpsw_ale_policer_reset(ale);
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