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MIPS: BMIPS: Add special cache handling in c-r4k.c
BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit, so it isn't necessary to raise IPIs to keep both CPUs coherent. BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$ fills from D$. But a special sequence with 2 SYNCs and 32 NOPs is needed to ensure coherency. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8165/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -917,6 +917,18 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
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}
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}
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static void b5k_instruction_hazard(void)
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{
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__sync();
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__sync();
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__asm__ __volatile__(
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" nop; nop; nop; nop; nop; nop; nop; nop\n"
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" nop; nop; nop; nop; nop; nop; nop; nop\n"
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" nop; nop; nop; nop; nop; nop; nop; nop\n"
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" nop; nop; nop; nop; nop; nop; nop; nop\n"
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: : : "memory");
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}
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static char *way_string[] = { NULL, "direct mapped", "2-way",
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"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
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};
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@ -1683,6 +1695,37 @@ void r4k_cache_init(void)
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coherency_setup();
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board_cache_error_setup = r4k_cache_error_setup;
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/*
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* Per-CPU overrides
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*/
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switch (current_cpu_type()) {
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case CPU_BMIPS4350:
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case CPU_BMIPS4380:
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/* No IPI is needed because all CPUs share the same D$ */
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flush_data_cache_page = r4k_blast_dcache_page;
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break;
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case CPU_BMIPS5000:
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/* We lose our superpowers if L2 is disabled */
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if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
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break;
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/* I$ fills from D$ just by emptying the write buffers */
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flush_cache_page = (void *)b5k_instruction_hazard;
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flush_cache_range = (void *)b5k_instruction_hazard;
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flush_cache_sigtramp = (void *)b5k_instruction_hazard;
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local_flush_data_cache_page = (void *)b5k_instruction_hazard;
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flush_data_cache_page = (void *)b5k_instruction_hazard;
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flush_icache_range = (void *)b5k_instruction_hazard;
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local_flush_icache_range = (void *)b5k_instruction_hazard;
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/* Cache aliases are handled in hardware; allow HIGHMEM */
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current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
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/* Optimization: an L2 flush implicitly flushes the L1 */
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current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
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break;
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}
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}
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static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
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