korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-27 22:24:11 +08:00
Code Issues Packages Projects Releases Wiki Activity

One fix for a broken driver on Renesas RZ/A1 SoCs with bootloaders that don't

Browse Source 
turn all the clks on and another fix for stm32f4 SoCs where we have multiple
 drivers attaching to the same DT node.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iQIcBAABCAAGBQJYb9ZVAAoJEK0CiJfG5JUlO2UQANIrI8mPjzrneEa0tCTNg2sj
 ZL8tIAJ8xs3I4Mwnr7NTHVSWTlsuetKVrxck4/Oq5wGbeoFcnpFALWB+kwH2yIVX
 GTrwIiv0NRFM5RFjve1jx7vpSxUu7VbU3bV1Ym3fhjD/Eo3qhAskJmp8lsAWVmKt
 1hVqcUFfxn613qsmJxUoIj6o5ZWY8XUoloZaO/nz3zBwQpcy+1Fje+/VjE2xdVuH
 Rh0RyTek3Pbt2hWZpyWUIzxWWNRneFL7ks1JFx+eInX/TerMKDFXBe7Op4fy3B4g
 0Ko1ZGoLf8ufICSbNVEQa3O0/cdCfVR/qEg4V0zO48aWsLQJVdT4mzsINTCeBBz+
 Vj18gaCShB8Q5tmgEbHQBKtysgV9EqJUjs7l6f41RVS0MHUC/V9Mnmgg26w1BAkG
 JChNsdFIaFAvMgHpprhER+a7LA81bJBj//k7LfFrJKJlWZoDLLtKsp8dKEgA2VjN
 el89fsk3acZSQLNTNbKBDEVEiCRhHQV5oXFESfHRVHZAYRNxSaCoC/yNeYfL+6ip
 lCv8GVIH5Uqkz8w2PqAIKzBxoyP1dUih0k6xvjCBKyIcJix/2QriOU13ZdBMp2tL
 7wni0M4yJceueY5v3BxwxzVDGN36WCc+ivzjrRDhjZDoK8joAtdTvpL5K2YkQzFz
 tZokD8QMNLdfMGJMXyyG
 =5ciP
 -----END PGP SIGNATURE-----

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "One fix for a broken driver on Renesas RZ/A1 SoCs with bootloaders
  that don't turn all the clks on and another fix for stm32f4 SoCs where
  we have multiple drivers attaching to the same DT node"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method
  clk: renesas: mstp: Support 8-bit registers for r7s72100
This commit is contained in:
Linus Torvalds 2017-01-06 15:35:27 -08:00
commit d72f0ded89
2 changed files with 24 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/clk-stm32f4.c
View File

@ -768,5 +768,5 @@ fail:
kfree(clks);
iounmap(base);
}
CLK_OF_DECLARE(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
CLK_OF_DECLARE(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);

27
drivers/clk/renesas/clk-mstp.c
View File

@ -37,12 +37,14 @@
* @smstpcr: module stop control register
* @mstpsr: module stop status register (optional)
* @lock: protects writes to SMSTPCR
* @width_8bit: registers are 8-bit, not 32-bit
*/
struct mstp_clock_group {
struct clk_onecell_data data;
void __iomem *smstpcr;
void __iomem *mstpsr;
spinlock_t lock;
bool width_8bit;
};
/**
@ -59,6 +61,18 @@ struct mstp_clock {
#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
u32 __iomem *reg)
{
return group->width_8bit ? readb(reg) : clk_readl(reg);
}
static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
u32 __iomem *reg)
{
group->width_8bit ? writeb(val, reg) : clk_writel(val, reg);
}
static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
{
struct mstp_clock *clock = to_mstp_clock(hw);
@ -70,12 +84,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
spin_lock_irqsave(&group->lock, flags);
value = clk_readl(group->smstpcr);
value = cpg_mstp_read(group, group->smstpcr);
if (enable)
value &= ~bitmask;
else
value |= bitmask;
clk_writel(value, group->smstpcr);
cpg_mstp_write(group, value, group->smstpcr);
spin_unlock_irqrestore(&group->lock, flags);
@ -83,7 +97,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
return 0;
for (i = 1000; i > 0; --i) {
if (!(clk_readl(group->mstpsr) & bitmask))
if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
break;
cpu_relax();
}
@ -114,9 +128,9 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
u32 value;
if (group->mstpsr)
value = clk_readl(group->mstpsr);
value = cpg_mstp_read(group, group->mstpsr);
else
value = clk_readl(group->smstpcr);
value = cpg_mstp_read(group, group->smstpcr);
return !(value & BIT(clock->bit_index));
}
@ -188,6 +202,9 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
return;
}
if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
group->width_8bit = true;
for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
clks[i] = ERR_PTR(-ENOENT);