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clk: qcom: gcc-msm8998: Move parent names and mapping below GPLLs
Prepare for a future patch where we use .hw pointers to these GPLL clocks in the parent mapping instead of name references. This requires the GPLL clocks to be decared before parent_data arrays. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210911121340.261920-2-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -25,98 +25,6 @@
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#include "reset.h"
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#include "gdsc.h"
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enum {
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P_AUD_REF_CLK,
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P_CORE_BI_PLL_TEST_SE,
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P_GPLL0_OUT_MAIN,
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P_GPLL4_OUT_MAIN,
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P_PLL0_EARLY_DIV_CLK_SRC,
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P_SLEEP_CLK,
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P_XO,
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};
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static const struct parent_map gcc_parent_map_0[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_PLL0_EARLY_DIV_CLK_SRC, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_0[] = {
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"xo",
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"gpll0_out_main",
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"gpll0_out_main",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_1[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_1[] = {
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"xo",
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"gpll0_out_main",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_2[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_SLEEP_CLK, 5 },
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{ P_PLL0_EARLY_DIV_CLK_SRC, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_2[] = {
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"xo",
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"gpll0_out_main",
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"core_pi_sleep_clk",
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"gpll0_out_main",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_3[] = {
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{ P_XO, 0 },
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{ P_SLEEP_CLK, 5 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_3[] = {
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"xo",
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"core_pi_sleep_clk",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_4[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_GPLL4_OUT_MAIN, 5 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_4[] = {
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"xo",
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"gpll0_out_main",
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"gpll4_out_main",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_5[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_AUD_REF_CLK, 2 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_5[] = {
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"xo",
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"gpll0_out_main",
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"aud_ref_clk",
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"core_bi_pll_test_se",
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};
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static struct clk_fixed_factor xo = {
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.mult = 1,
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.div = 1,
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@ -438,6 +346,98 @@ static struct clk_alpha_pll_postdiv gpll4_out_test = {
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},
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};
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enum {
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P_AUD_REF_CLK,
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P_CORE_BI_PLL_TEST_SE,
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P_GPLL0_OUT_MAIN,
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P_GPLL4_OUT_MAIN,
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P_PLL0_EARLY_DIV_CLK_SRC,
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P_SLEEP_CLK,
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P_XO,
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};
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static const struct parent_map gcc_parent_map_0[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_PLL0_EARLY_DIV_CLK_SRC, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_0[] = {
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"xo",
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"gpll0_out_main",
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"gpll0_out_main",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_1[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_1[] = {
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"xo",
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"gpll0_out_main",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_2[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_SLEEP_CLK, 5 },
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{ P_PLL0_EARLY_DIV_CLK_SRC, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_2[] = {
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"xo",
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"gpll0_out_main",
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"core_pi_sleep_clk",
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"gpll0_out_main",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_3[] = {
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{ P_XO, 0 },
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{ P_SLEEP_CLK, 5 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_3[] = {
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"xo",
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"core_pi_sleep_clk",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_4[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_GPLL4_OUT_MAIN, 5 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_4[] = {
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"xo",
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"gpll0_out_main",
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"gpll4_out_main",
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"core_bi_pll_test_se",
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};
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static const struct parent_map gcc_parent_map_5[] = {
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{ P_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 1 },
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{ P_AUD_REF_CLK, 2 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gcc_parent_names_5[] = {
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"xo",
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"gpll0_out_main",
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"aud_ref_clk",
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"core_bi_pll_test_se",
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};
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static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
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