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net: stmmac: Add Flexible RX Parser support in XGMAC
XGMAC cores also support the Flexible RX Parser feature. Add the support for it in the XGMAC core. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jose Abreu
David S. Miller
parent
56e58d6c8a
commit
d6e1c12cf9
@ -112,6 +112,9 @@
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#define XGMAC_HWFEAT_RXQCNT GENMASK(3, 0)
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#define XGMAC_HW_FEATURE3 0x00000128
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#define XGMAC_HWFEAT_ASP GENMASK(15, 14)
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#define XGMAC_HWFEAT_FRPES GENMASK(12, 11)
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#define XGMAC_HWFEAT_FRPPB GENMASK(10, 9)
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#define XGMAC_HWFEAT_FRPSEL BIT(3)
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#define XGMAC_MAC_DPP_FSM_INT_STATUS 0x00000150
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#define XGMAC_MAC_FSM_CONTROL 0x00000158
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#define XGMAC_PRTYEN BIT(1)
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@ -145,6 +148,7 @@
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/* MTL Registers */
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#define XGMAC_MTL_OPMODE 0x00001000
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#define XGMAC_FRPE BIT(15)
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#define XGMAC_ETSALG GENMASK(6, 5)
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#define XGMAC_WRR (0x0 << 5)
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#define XGMAC_WFQ (0x1 << 5)
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@ -160,6 +164,15 @@
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#define XGMAC_TC_PRTY_MAP1 0x00001044
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#define XGMAC_PSTC(x) GENMASK((x) * 8 + 7, (x) * 8)
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#define XGMAC_PSTC_SHIFT(x) ((x) * 8)
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#define XGMAC_MTL_RXP_CONTROL_STATUS 0x000010a0
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#define XGMAC_RXPI BIT(31)
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#define XGMAC_NPE GENMASK(23, 16)
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#define XGMAC_NVE GENMASK(7, 0)
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#define XGMAC_MTL_RXP_IACC_CTRL_ST 0x000010b0
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#define XGMAC_STARTBUSY BIT(31)
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#define XGMAC_WRRDN BIT(16)
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#define XGMAC_ADDR GENMASK(9, 0)
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#define XGMAC_MTL_RXP_IACC_DATA 0x000010b4
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#define XGMAC_MTL_ECC_CONTROL 0x000010c0
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#define XGMAC_MTL_SAFETY_INT_STATUS 0x000010c4
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#define XGMAC_MEUIS BIT(1)
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@ -808,6 +808,195 @@ static int dwxgmac3_safety_feat_dump(struct stmmac_safety_stats *stats,
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return 0;
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}
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static int dwxgmac3_rxp_disable(void __iomem *ioaddr)
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{
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u32 val = readl(ioaddr + XGMAC_MTL_OPMODE);
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val &= ~XGMAC_FRPE;
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writel(val, ioaddr + XGMAC_MTL_OPMODE);
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return 0;
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}
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static void dwxgmac3_rxp_enable(void __iomem *ioaddr)
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{
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u32 val;
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val = readl(ioaddr + XGMAC_MTL_OPMODE);
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val |= XGMAC_FRPE;
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writel(val, ioaddr + XGMAC_MTL_OPMODE);
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}
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static int dwxgmac3_rxp_update_single_entry(void __iomem *ioaddr,
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struct stmmac_tc_entry *entry,
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int pos)
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{
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int ret, i;
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for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) {
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int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i;
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u32 val;
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/* Wait for ready */
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ret = readl_poll_timeout(ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST,
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val, !(val & XGMAC_STARTBUSY), 1, 10000);
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if (ret)
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return ret;
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/* Write data */
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val = *((u32 *)&entry->val + i);
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writel(val, ioaddr + XGMAC_MTL_RXP_IACC_DATA);
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/* Write pos */
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val = real_pos & XGMAC_ADDR;
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writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
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/* Write OP */
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val |= XGMAC_WRRDN;
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writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
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/* Start Write */
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val |= XGMAC_STARTBUSY;
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writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
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/* Wait for done */
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ret = readl_poll_timeout(ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST,
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val, !(val & XGMAC_STARTBUSY), 1, 10000);
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if (ret)
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return ret;
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}
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return 0;
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}
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static struct stmmac_tc_entry *
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dwxgmac3_rxp_get_next_entry(struct stmmac_tc_entry *entries,
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unsigned int count, u32 curr_prio)
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{
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struct stmmac_tc_entry *entry;
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u32 min_prio = ~0x0;
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int i, min_prio_idx;
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bool found = false;
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for (i = count - 1; i >= 0; i--) {
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entry = &entries[i];
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/* Do not update unused entries */
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if (!entry->in_use)
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continue;
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/* Do not update already updated entries (i.e. fragments) */
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if (entry->in_hw)
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continue;
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/* Let last entry be updated last */
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if (entry->is_last)
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continue;
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/* Do not return fragments */
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if (entry->is_frag)
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continue;
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/* Check if we already checked this prio */
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if (entry->prio < curr_prio)
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continue;
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/* Check if this is the minimum prio */
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if (entry->prio < min_prio) {
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min_prio = entry->prio;
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min_prio_idx = i;
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found = true;
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}
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}
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if (found)
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return &entries[min_prio_idx];
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return NULL;
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}
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static int dwxgmac3_rxp_config(void __iomem *ioaddr,
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struct stmmac_tc_entry *entries,
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unsigned int count)
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{
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struct stmmac_tc_entry *entry, *frag;
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int i, ret, nve = 0;
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u32 curr_prio = 0;
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u32 old_val, val;
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/* Force disable RX */
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old_val = readl(ioaddr + XGMAC_RX_CONFIG);
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val = old_val & ~XGMAC_CONFIG_RE;
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writel(val, ioaddr + XGMAC_RX_CONFIG);
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/* Disable RX Parser */
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ret = dwxgmac3_rxp_disable(ioaddr);
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if (ret)
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goto re_enable;
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/* Set all entries as NOT in HW */
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for (i = 0; i < count; i++) {
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entry = &entries[i];
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entry->in_hw = false;
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}
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/* Update entries by reverse order */
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while (1) {
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entry = dwxgmac3_rxp_get_next_entry(entries, count, curr_prio);
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if (!entry)
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break;
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curr_prio = entry->prio;
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frag = entry->frag_ptr;
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/* Set special fragment requirements */
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if (frag) {
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entry->val.af = 0;
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entry->val.rf = 0;
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entry->val.nc = 1;
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entry->val.ok_index = nve + 2;
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}
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ret = dwxgmac3_rxp_update_single_entry(ioaddr, entry, nve);
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if (ret)
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goto re_enable;
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entry->table_pos = nve++;
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entry->in_hw = true;
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if (frag && !frag->in_hw) {
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ret = dwxgmac3_rxp_update_single_entry(ioaddr, frag, nve);
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if (ret)
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goto re_enable;
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frag->table_pos = nve++;
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frag->in_hw = true;
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}
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}
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if (!nve)
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goto re_enable;
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/* Update all pass entry */
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for (i = 0; i < count; i++) {
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entry = &entries[i];
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if (!entry->is_last)
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continue;
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ret = dwxgmac3_rxp_update_single_entry(ioaddr, entry, nve);
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if (ret)
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goto re_enable;
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entry->table_pos = nve++;
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}
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/* Assume n. of parsable entries == n. of valid entries */
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val = (nve << 16) & XGMAC_NPE;
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val |= nve & XGMAC_NVE;
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writel(val, ioaddr + XGMAC_MTL_RXP_CONTROL_STATUS);
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/* Enable RX Parser */
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dwxgmac3_rxp_enable(ioaddr);
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re_enable:
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/* Re-enable RX */
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writel(old_val, ioaddr + XGMAC_RX_CONFIG);
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return ret;
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}
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const struct stmmac_ops dwxgmac210_ops = {
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.core_init = dwxgmac2_core_init,
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.set_mac = dwxgmac2_set_mac,
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@ -843,6 +1032,7 @@ const struct stmmac_ops dwxgmac210_ops = {
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.set_mac_loopback = dwxgmac2_set_mac_loopback,
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.rss_configure = dwxgmac2_rss_configure,
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.update_vlan_hash = dwxgmac2_update_vlan_hash,
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.rxp_config = dwxgmac3_rxp_config,
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};
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int dwxgmac2_setup(struct stmmac_priv *priv)
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@ -403,6 +403,9 @@ static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
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/* MAC HW feature 3 */
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hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
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dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14;
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dma_cap->frpes = (hw_cap & XGMAC_HWFEAT_FRPES) >> 11;
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dma_cap->frpbs = (hw_cap & XGMAC_HWFEAT_FRPPB) >> 9;
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dma_cap->frpsel = (hw_cap & XGMAC_HWFEAT_FRPSEL) >> 3;
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}
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static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
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