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perf/x86/intel/uncore: Add Broadwell-EP uncore support
The uncore subsystem for Broadwell-EP is similar to Haswell-EP. There are some differences in pci device IDs, box number and constraints. This patch extends the Broadwell-DE codes to support Broadwell-EP. Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/1449176411-9499-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Kan Liang
Ingo Molnar
parent
d3bcd64bbc
commit
d6980ef325
@ -966,6 +966,7 @@ static int __init uncore_pci_init(void)
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case 63: /* Haswell-EP */
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ret = hswep_uncore_pci_init();
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break;
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case 79: /* BDX-EP */
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case 86: /* BDX-DE */
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ret = bdx_uncore_pci_init();
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break;
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@ -1287,6 +1288,7 @@ static int __init uncore_cpu_init(void)
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case 63: /* Haswell-EP */
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hswep_uncore_cpu_init();
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break;
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case 79: /* BDX-EP */
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case 86: /* BDX-DE */
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bdx_uncore_cpu_init();
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break;
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@ -2338,7 +2338,7 @@ int hswep_uncore_pci_init(void)
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}
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/* end of Haswell-EP uncore support */
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/* BDX-DE uncore support */
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/* BDX uncore support */
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static struct intel_uncore_type bdx_uncore_ubox = {
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.name = "ubox",
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@ -2360,13 +2360,14 @@ static struct event_constraint bdx_uncore_cbox_constraints[] = {
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UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x3e, 0x1),
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EVENT_CONSTRAINT_END
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};
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static struct intel_uncore_type bdx_uncore_cbox = {
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.name = "cbox",
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.num_counters = 4,
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.num_boxes = 8,
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.num_boxes = 24,
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.perf_ctr_bits = 48,
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.event_ctl = HSWEP_C0_MSR_PMON_CTL0,
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.perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
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@ -2379,9 +2380,24 @@ static struct intel_uncore_type bdx_uncore_cbox = {
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.format_group = &hswep_uncore_cbox_format_group,
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};
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static struct intel_uncore_type bdx_uncore_sbox = {
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.name = "sbox",
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.num_counters = 4,
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.num_boxes = 4,
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.perf_ctr_bits = 48,
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.event_ctl = HSWEP_S0_MSR_PMON_CTL0,
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.perf_ctr = HSWEP_S0_MSR_PMON_CTR0,
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.event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
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.box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL,
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.msr_offset = HSWEP_SBOX_MSR_OFFSET,
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.ops = &hswep_uncore_sbox_msr_ops,
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.format_group = &hswep_uncore_sbox_format_group,
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};
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static struct intel_uncore_type *bdx_msr_uncores[] = {
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&bdx_uncore_ubox,
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&bdx_uncore_cbox,
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&bdx_uncore_sbox,
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&hswep_uncore_pcu,
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NULL,
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};
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@ -2396,7 +2412,7 @@ void bdx_uncore_cpu_init(void)
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static struct intel_uncore_type bdx_uncore_ha = {
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.name = "ha",
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.num_counters = 4,
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.num_boxes = 1,
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.num_boxes = 2,
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.perf_ctr_bits = 48,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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@ -2404,7 +2420,7 @@ static struct intel_uncore_type bdx_uncore_ha = {
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static struct intel_uncore_type bdx_uncore_imc = {
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.name = "imc",
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.num_counters = 5,
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.num_boxes = 2,
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.num_boxes = 8,
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.perf_ctr_bits = 48,
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.fixed_ctr_bits = 48,
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.fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
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@ -2424,6 +2440,19 @@ static struct intel_uncore_type bdx_uncore_irp = {
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.format_group = &snbep_uncore_format_group,
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};
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static struct intel_uncore_type bdx_uncore_qpi = {
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.name = "qpi",
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.num_counters = 4,
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.num_boxes = 3,
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.perf_ctr_bits = 48,
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.perf_ctr = SNBEP_PCI_PMON_CTR0,
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.event_ctl = SNBEP_PCI_PMON_CTL0,
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.event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_PCI_PMON_BOX_CTL,
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.num_shared_regs = 1,
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.ops = &snbep_uncore_qpi_ops,
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.format_group = &snbep_uncore_qpi_format_group,
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};
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static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
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UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
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@ -2432,6 +2461,8 @@ static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
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UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
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EVENT_CONSTRAINT_END
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};
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@ -2445,18 +2476,65 @@ static struct intel_uncore_type bdx_uncore_r2pcie = {
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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static struct event_constraint bdx_uncore_r3qpi_constraints[] = {
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UNCORE_EVENT_CONSTRAINT(0x01, 0x7),
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UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
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UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
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UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
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UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
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UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
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UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
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EVENT_CONSTRAINT_END
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};
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static struct intel_uncore_type bdx_uncore_r3qpi = {
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.name = "r3qpi",
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.num_counters = 3,
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.num_boxes = 3,
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.perf_ctr_bits = 48,
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.constraints = bdx_uncore_r3qpi_constraints,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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enum {
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BDX_PCI_UNCORE_HA,
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BDX_PCI_UNCORE_IMC,
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BDX_PCI_UNCORE_IRP,
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BDX_PCI_UNCORE_QPI,
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BDX_PCI_UNCORE_R2PCIE,
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BDX_PCI_UNCORE_R3QPI,
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};
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static struct intel_uncore_type *bdx_pci_uncores[] = {
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[BDX_PCI_UNCORE_HA] = &bdx_uncore_ha,
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[BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc,
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[BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp,
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[BDX_PCI_UNCORE_QPI] = &bdx_uncore_qpi,
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[BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie,
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[BDX_PCI_UNCORE_R3QPI] = &bdx_uncore_r3qpi,
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NULL,
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};
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@ -2465,6 +2543,10 @@ static const struct pci_device_id bdx_uncore_pci_ids[] = {
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0),
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},
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{ /* Home Agent 1 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f38),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 1),
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},
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{ /* MC0 Channel 0 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
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@ -2473,14 +2555,74 @@ static const struct pci_device_id bdx_uncore_pci_ids[] = {
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
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},
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{ /* MC0 Channel 2 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb4),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 2),
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},
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{ /* MC0 Channel 3 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb5),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 3),
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},
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{ /* MC1 Channel 0 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd0),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 4),
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},
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{ /* MC1 Channel 1 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd1),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 5),
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},
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{ /* MC1 Channel 2 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd4),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 6),
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},
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{ /* MC1 Channel 3 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd5),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 7),
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},
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{ /* IRP */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0),
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},
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{ /* QPI0 Port 0 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f32),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 0),
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},
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{ /* QPI0 Port 1 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f33),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 1),
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},
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{ /* QPI1 Port 2 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3a),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 2),
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},
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{ /* R2PCIe */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0),
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},
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{ /* R3QPI0 Link 0 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f36),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 0),
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},
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{ /* R3QPI0 Link 1 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f37),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 1),
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},
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{ /* R3QPI1 Link 2 */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3e),
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.driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 2),
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},
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{ /* QPI Port 0 filter */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f86),
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.driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 0),
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},
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{ /* QPI Port 1 filter */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f96),
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.driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1),
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},
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{ /* QPI Port 2 filter */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46),
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.driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2),
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},
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{ /* end: all zeroes */ }
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};
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@ -2500,4 +2642,4 @@ int bdx_uncore_pci_init(void)
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return 0;
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}
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/* end of BDX-DE uncore support */
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/* end of BDX uncore support */
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