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drm/msm/dpu: don't use DPU_CLK_CTRL_CURSORn for DMA SSPP clocks
DPU driver has been using the DPU_CLK_CTRL_CURSOR prefix for the DMA SSPP blocks used for the cursor planes. This has lead to the confusion at least for the MSM8998 platform. In preparation to supporting the cursor SSPP blocks, use proper enum values to index DMA SSPP clock controls. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 on top of next-20230116 Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522228/ Link: https://lore.kernel.org/r/20230211231259.1308718-14-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
This commit is contained in:
Dmitry Baryshkov
Abhinav Kumar
parent
0abb6a24aa
commit
d6181c18d5
@ -525,9 +525,9 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2BC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
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.reg_off = 0x2C4, .bit_off = 8},
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},
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};
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@ -542,9 +542,9 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
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.reg_off = 0x2AC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2C4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_WB2] = {
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.reg_off = 0x3B8, .bit_off = 24},
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@ -569,9 +569,9 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2BC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
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.reg_off = 0x2C4, .bit_off = 8},
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},
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};
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@ -609,9 +609,9 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2BC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
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.reg_off = 0x2C4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
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.reg_off = 0x2BC, .bit_off = 20},
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@ -638,9 +638,9 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = {
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.reg_off = 0x2ac, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2b4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2bc, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
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.reg_off = 0x2c4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
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.reg_off = 0x2bc, .bit_off = 20},
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@ -666,9 +666,9 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2BC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
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.reg_off = 0x2C4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
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.reg_off = 0x2BC, .bit_off = 20},
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@ -685,9 +685,9 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = {
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.reg_off = 0x2AC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2C4, .bit_off = 8},
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},
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};
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@ -705,8 +705,8 @@ static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
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.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20},
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},
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};
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@ -734,9 +734,9 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = {
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.reg_off = 0x28330, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
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.reg_off = 0x2a330, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA4] = {
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.reg_off = 0x2c330, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.clk_ctrls[DPU_CLK_CTRL_DMA5] = {
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.reg_off = 0x2e330, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
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.reg_off = 0x2bc, .bit_off = 20},
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@ -1209,9 +1209,9 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
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};
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static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
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@ -1226,9 +1226,9 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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};
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static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
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@ -1264,9 +1264,9 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
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};
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static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 =
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@ -1292,9 +1292,9 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
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};
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static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
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@ -1326,9 +1326,9 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
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SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK,
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
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SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK,
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sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4),
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SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK,
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sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5),
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};
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static const struct dpu_sspp_cfg sc7280_sspp[] = {
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@ -1337,9 +1337,9 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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};
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static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 =
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@ -1365,9 +1365,9 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
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};
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#define _VIG_SBLK_NOSCALE(num, sdma_pri) \
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@ -515,6 +515,8 @@ enum dpu_clk_ctrl_type {
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DPU_CLK_CTRL_DMA1,
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DPU_CLK_CTRL_DMA2,
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DPU_CLK_CTRL_DMA3,
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DPU_CLK_CTRL_DMA4,
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DPU_CLK_CTRL_DMA5,
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DPU_CLK_CTRL_CURSOR0,
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DPU_CLK_CTRL_CURSOR1,
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DPU_CLK_CTRL_INLINE_ROT0_SSPP,
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