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i2c: omap: ensure writes to dev->buf_len are ordered
if we allow compiler reorder our writes, we could fall into a situation where dev->buf_len is reset for no apparent reason. This bug was found with a simple script which would transfer data to an i2c client from 1 to 1024 bytes (a simple for loop), when we got to transfer sizes bigger than the fifo size, dev->buf_len was reset to zero before we had an oportunity to handle XDR Interrupt. Because dev->buf_len was zero, we entered omap_i2c_transmit_data() to transfer zero bytes, which would mean we would just silently exit omap_i2c_transmit_data() without actually writing anything to DATA register. That would cause XDR IRQ to trigger forever and we would never transfer the remaining bytes. After adding the memory barrier, we also drop resetting dev->buf_len to zero in omap_i2c_xfer_msg() because both omap_i2c_transmit_data() and omap_i2c_receive_data() will act until dev->buf_len reaches zero, rendering the other write in omap_i2c_xfer_msg() redundant. This patch has been tested with pandaboard for a few iterations of the script mentioned above. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
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@ -524,6 +524,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
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dev->buf = msg->buf;
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dev->buf = msg->buf;
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dev->buf_len = msg->len;
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dev->buf_len = msg->len;
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/* make sure writes to dev->buf_len are ordered */
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barrier();
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omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
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omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
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/* Clear the FIFO Buffers */
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/* Clear the FIFO Buffers */
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@ -581,7 +584,6 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
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*/
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*/
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timeout = wait_for_completion_timeout(&dev->cmd_complete,
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timeout = wait_for_completion_timeout(&dev->cmd_complete,
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OMAP_I2C_TIMEOUT);
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OMAP_I2C_TIMEOUT);
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dev->buf_len = 0;
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if (timeout == 0) {
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if (timeout == 0) {
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dev_err(dev->dev, "controller timed out\n");
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dev_err(dev->dev, "controller timed out\n");
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omap_i2c_init(dev);
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omap_i2c_init(dev);
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