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drm/i915/gem: Make i915_gem_object_flush_write_domain() static
flush_write_domain() is only used within the GEM domain management code, so move it to i915_gem_domain.c and drop the export. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210119144912.12653-5-chris@chris-wilson.co.uk
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@ -5,6 +5,7 @@
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*/
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*/
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#include "display/intel_frontbuffer.h"
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#include "display/intel_frontbuffer.h"
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#include "gt/intel_gt.h"
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#include "i915_drv.h"
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#include "i915_drv.h"
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#include "i915_gem_clflush.h"
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#include "i915_gem_clflush.h"
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@ -15,13 +16,58 @@
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#include "i915_gem_lmem.h"
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#include "i915_gem_lmem.h"
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#include "i915_gem_mman.h"
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#include "i915_gem_mman.h"
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static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
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{
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return !(obj->cache_level == I915_CACHE_NONE ||
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obj->cache_level == I915_CACHE_WT);
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}
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static void
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flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
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{
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struct i915_vma *vma;
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assert_object_held(obj);
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if (!(obj->write_domain & flush_domains))
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return;
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switch (obj->write_domain) {
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case I915_GEM_DOMAIN_GTT:
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spin_lock(&obj->vma.lock);
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for_each_ggtt_vma(vma, obj) {
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if (i915_vma_unset_ggtt_write(vma))
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intel_gt_flush_ggtt_writes(vma->vm->gt);
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}
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spin_unlock(&obj->vma.lock);
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i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
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break;
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case I915_GEM_DOMAIN_WC:
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wmb();
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break;
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case I915_GEM_DOMAIN_CPU:
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i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
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break;
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case I915_GEM_DOMAIN_RENDER:
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if (gpu_write_needs_clflush(obj))
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obj->cache_dirty = true;
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break;
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}
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obj->write_domain = 0;
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}
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static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
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static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
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{
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{
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/*
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/*
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* We manually flush the CPU domain so that we can override and
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* We manually flush the CPU domain so that we can override and
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* force the flush for the display, and perform it asyncrhonously.
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* force the flush for the display, and perform it asyncrhonously.
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*/
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*/
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i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
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flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
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if (obj->cache_dirty)
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if (obj->cache_dirty)
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i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
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i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
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obj->write_domain = 0;
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obj->write_domain = 0;
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@ -80,7 +126,7 @@ i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
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if (ret)
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if (ret)
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return ret;
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return ret;
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i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
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flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
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/* Serialise direct access to this object with the barriers for
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/* Serialise direct access to this object with the barriers for
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* coherent writes from the GPU, by effectively invalidating the
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* coherent writes from the GPU, by effectively invalidating the
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@ -141,7 +187,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
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if (ret)
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if (ret)
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return ret;
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return ret;
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i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
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flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
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/* Serialise direct access to this object with the barriers for
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/* Serialise direct access to this object with the barriers for
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* coherent writes from the GPU, by effectively invalidating the
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* coherent writes from the GPU, by effectively invalidating the
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@ -451,7 +497,7 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
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if (ret)
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if (ret)
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return ret;
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return ret;
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i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
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flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
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/* Flush the CPU cache if it's still invalid. */
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/* Flush the CPU cache if it's still invalid. */
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if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
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if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
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@ -619,7 +665,7 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj,
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goto out;
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goto out;
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}
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}
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i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
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flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
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/* If we're not in the cpu read domain, set ourself into the gtt
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/* If we're not in the cpu read domain, set ourself into the gtt
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* read domain and manually flush cachelines (if required). This
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* read domain and manually flush cachelines (if required). This
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@ -670,7 +716,7 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj,
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goto out;
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goto out;
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}
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}
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i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
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flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
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/* If we're not in the cpu write domain, set ourself into the
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/* If we're not in the cpu write domain, set ourself into the
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* gtt write domain and manually flush cachelines (as required).
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* gtt write domain and manually flush cachelines (as required).
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@ -25,7 +25,6 @@
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#include <linux/sched/mm.h>
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#include <linux/sched/mm.h>
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#include "display/intel_frontbuffer.h"
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#include "display/intel_frontbuffer.h"
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#include "gt/intel_gt.h"
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#include "i915_drv.h"
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#include "i915_drv.h"
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#include "i915_gem_clflush.h"
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#include "i915_gem_clflush.h"
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#include "i915_gem_context.h"
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#include "i915_gem_context.h"
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@ -313,52 +312,6 @@ static void i915_gem_free_object(struct drm_gem_object *gem_obj)
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queue_work(i915->wq, &i915->mm.free_work);
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queue_work(i915->wq, &i915->mm.free_work);
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}
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}
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static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
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{
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return !(obj->cache_level == I915_CACHE_NONE ||
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obj->cache_level == I915_CACHE_WT);
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}
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void
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i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
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unsigned int flush_domains)
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{
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struct i915_vma *vma;
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assert_object_held(obj);
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if (!(obj->write_domain & flush_domains))
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return;
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switch (obj->write_domain) {
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case I915_GEM_DOMAIN_GTT:
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spin_lock(&obj->vma.lock);
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for_each_ggtt_vma(vma, obj) {
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if (i915_vma_unset_ggtt_write(vma))
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intel_gt_flush_ggtt_writes(vma->vm->gt);
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}
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spin_unlock(&obj->vma.lock);
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i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
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break;
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case I915_GEM_DOMAIN_WC:
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wmb();
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break;
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case I915_GEM_DOMAIN_CPU:
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i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
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break;
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case I915_GEM_DOMAIN_RENDER:
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if (gpu_write_needs_clflush(obj))
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obj->cache_dirty = true;
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break;
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}
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obj->write_domain = 0;
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}
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void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
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void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
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enum fb_op_origin origin)
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enum fb_op_origin origin)
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{
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{
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@ -427,10 +427,6 @@ static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
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void __i915_gem_object_release_map(struct drm_i915_gem_object *obj);
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void __i915_gem_object_release_map(struct drm_i915_gem_object *obj);
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void
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i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
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unsigned int flush_domains);
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int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj,
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int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj,
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unsigned int *needs_clflush);
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unsigned int *needs_clflush);
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int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj,
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int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj,
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