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ASoC: cs53l30: Correct number of volume levels on SX controls
[ Upstream commit 7fbd6dd681
]
This driver specified the maximum value rather than the number of volume
levels on the SX controls, this is incorrect, so correct them.
Reported-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220602162119.3393857-4-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -348,22 +348,22 @@ static const struct snd_kcontrol_new cs53l30_snd_controls[] = {
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SOC_ENUM("ADC2 NG Delay", adc2_ng_delay_enum),
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SOC_SINGLE_SX_TLV("ADC1A PGA Volume",
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CS53L30_ADC1A_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
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CS53L30_ADC1A_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
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SOC_SINGLE_SX_TLV("ADC1B PGA Volume",
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CS53L30_ADC1B_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
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CS53L30_ADC1B_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
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SOC_SINGLE_SX_TLV("ADC2A PGA Volume",
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CS53L30_ADC2A_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
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CS53L30_ADC2A_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
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SOC_SINGLE_SX_TLV("ADC2B PGA Volume",
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CS53L30_ADC2B_AFE_CTL, 0, 0x34, 0x18, pga_tlv),
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CS53L30_ADC2B_AFE_CTL, 0, 0x34, 0x24, pga_tlv),
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SOC_SINGLE_SX_TLV("ADC1A Digital Volume",
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CS53L30_ADC1A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
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CS53L30_ADC1A_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
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SOC_SINGLE_SX_TLV("ADC1B Digital Volume",
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CS53L30_ADC1B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
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CS53L30_ADC1B_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
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SOC_SINGLE_SX_TLV("ADC2A Digital Volume",
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CS53L30_ADC2A_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
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CS53L30_ADC2A_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
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SOC_SINGLE_SX_TLV("ADC2B Digital Volume",
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CS53L30_ADC2B_DIG_VOL, 0, 0xA0, 0x0C, dig_tlv),
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CS53L30_ADC2B_DIG_VOL, 0, 0xA0, 0x6C, dig_tlv),
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};
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static const struct snd_soc_dapm_widget cs53l30_dapm_widgets[] = {
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