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drm/mediatek: add gmc_bits for ovl private data
This patch add gmc_bits for ovl private data GMC register was set RDMA ultra and pre-ultra threshold. 10bit GMC register define is different with other SOC, gmc_thrshd_l not used. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
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@ -31,7 +31,9 @@
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#define DISP_REG_OVL_ADDR_MT8173 0x0f40
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#define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
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#define OVL_RDMA_MEM_GMC 0x40402020
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#define GMC_THRESHOLD_BITS 16
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#define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
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#define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)
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#define OVL_CON_BYTE_SWAP BIT(24)
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#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
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@ -49,6 +51,7 @@
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struct mtk_disp_ovl_data {
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unsigned int addr;
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unsigned int gmc_bits;
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bool fmt_rgb565_is_0;
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};
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@ -132,9 +135,23 @@ static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
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static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
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{
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unsigned int reg;
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unsigned int gmc_thrshd_l;
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unsigned int gmc_thrshd_h;
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unsigned int gmc_value;
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struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
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writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
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writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
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gmc_thrshd_l = GMC_THRESHOLD_LOW >>
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(GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
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gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
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(GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
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if (ovl->data->gmc_bits == 10)
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gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
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else
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gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
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gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
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writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
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reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
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reg = reg | BIT(idx);
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@ -316,11 +333,13 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
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static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
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.addr = DISP_REG_OVL_ADDR_MT2701,
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.gmc_bits = 8,
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.fmt_rgb565_is_0 = false,
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};
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static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
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.addr = DISP_REG_OVL_ADDR_MT8173,
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.gmc_bits = 8,
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.fmt_rgb565_is_0 = true,
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};
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