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riscv: Fix Zbb alternative IDs
Commit4bf8860760
("riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions") switched ISA extension alternatives to use the RISCV_ISA_EXT_* macros instead of CPUFEATURE_*. This was mismerged when applied on top of the Zbb series, so the Zbb alternatives referenced the wrong errata ID values. Fixes:9daca9a5b9
("Merge patch series "riscv: improve boot time isa extensions handling"") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Guo Ren <guoren@kernel.org> Tested-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230212021534.59121-3-samuel@sholland.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -23,11 +23,6 @@
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#define ERRATA_THEAD_NUMBER 3
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#endif
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#define CPUFEATURE_SVPBMT 0
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#define CPUFEATURE_ZICBOM 1
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#define CPUFEATURE_ZBB 2
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#define CPUFEATURE_NUMBER 3
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#ifdef __ASSEMBLY__
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#define ALT_INSN_FAULT(x) \
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@ -9,7 +9,7 @@
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/* int strcmp(const char *cs, const char *ct) */
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SYM_FUNC_START(strcmp)
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ALTERNATIVE("nop", "j strcmp_zbb", 0, CPUFEATURE_ZBB, CONFIG_RISCV_ISA_ZBB)
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ALTERNATIVE("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
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/*
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* Returns
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@ -9,7 +9,7 @@
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/* int strlen(const char *s) */
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SYM_FUNC_START(strlen)
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ALTERNATIVE("nop", "j strlen_zbb", 0, CPUFEATURE_ZBB, CONFIG_RISCV_ISA_ZBB)
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ALTERNATIVE("nop", "j strlen_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
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/*
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* Returns
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@ -9,7 +9,7 @@
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/* int strncmp(const char *cs, const char *ct, size_t count) */
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SYM_FUNC_START(strncmp)
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ALTERNATIVE("nop", "j strncmp_zbb", 0, CPUFEATURE_ZBB, CONFIG_RISCV_ISA_ZBB)
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ALTERNATIVE("nop", "j strncmp_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
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/*
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* Returns
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