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ASoC: cs42l42: Correct some register default values
Some registers had wrong default values in cs42l42_reg_defaults[].
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Fixes: 2c394ca796
("ASoC: Add support for CS42L42 codec")
Link: https://lore.kernel.org/r/20211015133619.4698-4-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -93,7 +93,7 @@ static const struct reg_default cs42l42_reg_defaults[] = {
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{ CS42L42_ASP_RX_INT_MASK, 0x1F },
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{ CS42L42_ASP_TX_INT_MASK, 0x0F },
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{ CS42L42_CODEC_INT_MASK, 0x03 },
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{ CS42L42_SRCPL_INT_MASK, 0xFF },
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{ CS42L42_SRCPL_INT_MASK, 0x7F },
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{ CS42L42_VPMON_INT_MASK, 0x01 },
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{ CS42L42_PLL_LOCK_INT_MASK, 0x01 },
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{ CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
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@ -130,7 +130,7 @@ static const struct reg_default cs42l42_reg_defaults[] = {
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{ CS42L42_MIXER_CHA_VOL, 0x3F },
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{ CS42L42_MIXER_ADC_VOL, 0x3F },
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{ CS42L42_MIXER_CHB_VOL, 0x3F },
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{ CS42L42_EQ_COEF_IN0, 0x22 },
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{ CS42L42_EQ_COEF_IN0, 0x00 },
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{ CS42L42_EQ_COEF_IN1, 0x00 },
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{ CS42L42_EQ_COEF_IN2, 0x00 },
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{ CS42L42_EQ_COEF_IN3, 0x00 },
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