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ARM: dts: kirkwood: resynch 98dx4122 dtsi

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The 98DX4122 dtsi file lacks the defintion of the PCIe controller which
is present on this SoC.

The SATA phys must also be explicitely disabled since they are not
present on this SoC. If they remain enabled, a hardlock occures when
their clock gates are enabled.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Link: https://lkml.kernel.org/r/1400230143-15620-2-git-send-email-valentin.longchamp@keymile.com
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Valentin Longchamp 2014-05-16 10:49:01 +02:00 committed by Jason Cooper
parent 57dc7971d3
commit d584a10d1e
1 changed files with 43 additions and 0 deletions
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43
arch/arm/boot/dts/kirkwood-98dx4122.dtsi
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@ -1,4 +1,39 @@
/ {
mbus {
pciec: pcie-controller {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gate_clk 2>;
status = "disabled";
};
};
};
ocp@f1000000 {
pinctrl: pin-controller@10000 {
compatible = "marvell,98dx4122-pinctrl";
@ -6,3 +41,11 @@
};
};
};
&sata_phy0 {
status = "disabled";
};
&sata_phy1 {
status = "disabled";
};