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- Add the final conversions to the new Intel VFM CPU model matching macros
which include the vendor and finally drop the old ones which hardcode family 6 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmbe/GYACgkQEsHwGGHe VUqCcw//Y0HgpGpCzi7/WraEI0kzqduV4SCm2louK8MnkgSIVVrccSg6rTWapvs9 Fxqyg6ZfTNxMuSEexSX9NMc7Nq7nm3m1JPztsZKcwur3fnfwPoxWjfR89dmnXbo6 iUYbolgiPMUo8S18NSXyEaopMwPJYSV/lvMRPclrUsAFhy40+kQcXYVMvP1BAw2z Pi1TuRqMViVf5lzC71Xy/VntoAgWOtIEPnCLXeOLGIPkRZW+T/jUyTe6xFBOqjrg BAWfVH8U2Smf2eNzPqO0RDQttSYl6GWcz9bJIPihmlMpFuACSH9j0UadjAMPCVKp Th0uLxIaEWL7QV7qfSmWm0W79FZAhfJbA+EEKDQrUr+jgTEDE2r2hL7JVo2y8bHV 3nXdaUTnyC0oFr0FPl8yRVk4RN23Uj+fB1m6CCkFnZZQ5xIGT5FERGqut6vEwJlV fAR8LioKMfRD7q/iQqw/iqMAi8SI0/YQ7R3HGYf6gnjkO86j4snWEdnpWHTraAlR y24CSUrJ1hh8FRl/ISj56fB6efPm4Ef/znd9CRhWoIaLMgEV8ICDDVkH8RBePaGK 8D83mA/l1WJTAyyAUs6bu96x1TVWK+0xsazQmNJjPeh/mG54mmmrl9wK8YUaK0r4 NasmpovQ7M0QQx5IkFgx4oR84r179pHF246phSV1nrLpX8/EAzQ= =0KAq -----END PGP SIGNATURE----- Merge tag 'x86_cpu_for_v6.12_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 cpuid updates from Borislav Petkov: - Add the final conversions to the new Intel VFM CPU model matching macros which include the vendor and finally drop the old ones which hardcode family 6 * tag 'x86_cpu_for_v6.12_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu/vfm: Delete all the *_FAM6_ CPU #defines x86/cpu/vfm: Delete X86_MATCH_INTEL_FAM6_MODEL[_STEPPING]() macros extcon: axp288: Switch to new Intel CPU model defines x86/cpu/intel: Replace PAT erratum model/family magic numbers with symbolic IFM references
This commit is contained in:
Linus Torvalds
commit
d580d74ea2
@ -192,26 +192,6 @@
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#define X86_MATCH_VENDOR_FAM(vendor, family, data) \
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X86_MATCH_VENDOR_FAM_MODEL(vendor, family, X86_MODEL_ANY, data)
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/**
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* X86_MATCH_INTEL_FAM6_MODEL - Match vendor INTEL, family 6 and model
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* @model: The model name without the INTEL_FAM6_ prefix or ANY
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* The model name is expanded to INTEL_FAM6_@model internally
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* @data: Driver specific data or NULL. The internal storage
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* format is unsigned long. The supplied value, pointer
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* etc. is casted to unsigned long internally.
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*
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* The vendor is set to INTEL, the family to 6 and all other missing
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* arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are set to wildcards.
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*
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* See X86_MATCH_VENDOR_FAM_MODEL_FEATURE() for further information.
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*/
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#define X86_MATCH_INTEL_FAM6_MODEL(model, data) \
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X86_MATCH_VENDOR_FAM_MODEL(INTEL, 6, INTEL_FAM6_##model, data)
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#define X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(model, steppings, data) \
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X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
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steppings, X86_FEATURE_ANY, data)
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/**
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* X86_MATCH_VFM - Match encoded vendor/family/model
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* @vfm: Encoded 8-bits each for vendor, family, model
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@ -10,7 +10,7 @@
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* that group keep the CPUID for the variants sorted by model number.
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*
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* The defined symbol names have the following form:
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* INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
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* INTEL_{OPTFAMILY}_{MICROARCH}{OPTDIFF}
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* where:
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* OPTFAMILY Describes the family of CPUs that this belongs to. Default
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* is assumed to be "_CORE" (and should be omitted). Other values
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@ -42,215 +42,136 @@
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#define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model)
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/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
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#define INTEL_FAM6_ANY X86_MODEL_ANY
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/* Wildcard match for FAM6 so X86_MATCH_VFM(ANY) works */
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/* Wildcard match so X86_MATCH_VFM(ANY) works */
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#define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY)
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#define INTEL_FAM6_CORE_YONAH 0x0E
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#define INTEL_PENTIUM_PRO IFM(6, 0x01)
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#define INTEL_CORE_YONAH IFM(6, 0x0E)
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#define INTEL_FAM6_CORE2_MEROM 0x0F
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#define INTEL_CORE2_MEROM IFM(6, 0x0F)
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#define INTEL_FAM6_CORE2_MEROM_L 0x16
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#define INTEL_CORE2_MEROM_L IFM(6, 0x16)
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#define INTEL_FAM6_CORE2_PENRYN 0x17
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#define INTEL_CORE2_PENRYN IFM(6, 0x17)
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#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
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#define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D)
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#define INTEL_FAM6_NEHALEM 0x1E
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#define INTEL_NEHALEM IFM(6, 0x1E)
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#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
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#define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */
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#define INTEL_FAM6_NEHALEM_EP 0x1A
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#define INTEL_NEHALEM_EP IFM(6, 0x1A)
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#define INTEL_FAM6_NEHALEM_EX 0x2E
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#define INTEL_NEHALEM_EX IFM(6, 0x2E)
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#define INTEL_FAM6_WESTMERE 0x25
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#define INTEL_WESTMERE IFM(6, 0x25)
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#define INTEL_FAM6_WESTMERE_EP 0x2C
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#define INTEL_WESTMERE_EP IFM(6, 0x2C)
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#define INTEL_FAM6_WESTMERE_EX 0x2F
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#define INTEL_WESTMERE_EX IFM(6, 0x2F)
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#define INTEL_FAM6_SANDYBRIDGE 0x2A
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#define INTEL_SANDYBRIDGE IFM(6, 0x2A)
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#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
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#define INTEL_SANDYBRIDGE_X IFM(6, 0x2D)
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#define INTEL_FAM6_IVYBRIDGE 0x3A
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#define INTEL_IVYBRIDGE IFM(6, 0x3A)
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#define INTEL_FAM6_IVYBRIDGE_X 0x3E
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#define INTEL_IVYBRIDGE_X IFM(6, 0x3E)
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#define INTEL_FAM6_HASWELL 0x3C
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#define INTEL_HASWELL IFM(6, 0x3C)
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#define INTEL_FAM6_HASWELL_X 0x3F
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#define INTEL_HASWELL_X IFM(6, 0x3F)
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#define INTEL_FAM6_HASWELL_L 0x45
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#define INTEL_HASWELL_L IFM(6, 0x45)
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#define INTEL_FAM6_HASWELL_G 0x46
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#define INTEL_HASWELL_G IFM(6, 0x46)
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#define INTEL_FAM6_BROADWELL 0x3D
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#define INTEL_BROADWELL IFM(6, 0x3D)
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#define INTEL_FAM6_BROADWELL_G 0x47
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#define INTEL_BROADWELL_G IFM(6, 0x47)
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#define INTEL_FAM6_BROADWELL_X 0x4F
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#define INTEL_BROADWELL_X IFM(6, 0x4F)
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#define INTEL_FAM6_BROADWELL_D 0x56
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#define INTEL_BROADWELL_D IFM(6, 0x56)
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#define INTEL_FAM6_SKYLAKE_L 0x4E /* Sky Lake */
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#define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */
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#define INTEL_FAM6_SKYLAKE 0x5E /* Sky Lake */
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#define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */
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#define INTEL_FAM6_SKYLAKE_X 0x55 /* Sky Lake */
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#define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */
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/* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */
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/* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */
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#define INTEL_FAM6_KABYLAKE_L 0x8E /* Sky Lake */
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#define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */
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/* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */
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/* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */
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/* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */
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#define INTEL_FAM6_KABYLAKE 0x9E /* Sky Lake */
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#define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */
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/* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */
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#define INTEL_FAM6_COMETLAKE 0xA5 /* Sky Lake */
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#define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */
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#define INTEL_FAM6_COMETLAKE_L 0xA6 /* Sky Lake */
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#define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */
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#define INTEL_FAM6_CANNONLAKE_L 0x66 /* Palm Cove */
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#define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */
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#define INTEL_FAM6_ICELAKE_X 0x6A /* Sunny Cove */
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#define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */
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#define INTEL_FAM6_ICELAKE_D 0x6C /* Sunny Cove */
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#define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */
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#define INTEL_FAM6_ICELAKE 0x7D /* Sunny Cove */
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#define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */
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#define INTEL_FAM6_ICELAKE_L 0x7E /* Sunny Cove */
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#define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */
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#define INTEL_FAM6_ICELAKE_NNPI 0x9D /* Sunny Cove */
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#define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */
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#define INTEL_FAM6_ROCKETLAKE 0xA7 /* Cypress Cove */
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#define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */
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#define INTEL_FAM6_TIGERLAKE_L 0x8C /* Willow Cove */
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#define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */
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#define INTEL_FAM6_TIGERLAKE 0x8D /* Willow Cove */
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#define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */
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#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */
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#define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */
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#define INTEL_FAM6_EMERALDRAPIDS_X 0xCF
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#define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF)
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#define INTEL_FAM6_GRANITERAPIDS_X 0xAD
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#define INTEL_GRANITERAPIDS_X IFM(6, 0xAD)
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#define INTEL_FAM6_GRANITERAPIDS_D 0xAE
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#define INTEL_GRANITERAPIDS_D IFM(6, 0xAE)
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/* "Hybrid" Processors (P-Core/E-Core) */
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#define INTEL_FAM6_LAKEFIELD 0x8A /* Sunny Cove / Tremont */
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#define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */
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#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */
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#define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */
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#define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */
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#define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */
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#define INTEL_FAM6_RAPTORLAKE 0xB7 /* Raptor Cove / Enhanced Gracemont */
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#define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */
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#define INTEL_FAM6_RAPTORLAKE_P 0xBA
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#define INTEL_RAPTORLAKE_P IFM(6, 0xBA)
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#define INTEL_FAM6_RAPTORLAKE_S 0xBF
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#define INTEL_RAPTORLAKE_S IFM(6, 0xBF)
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#define INTEL_FAM6_METEORLAKE 0xAC
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#define INTEL_METEORLAKE IFM(6, 0xAC)
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#define INTEL_FAM6_METEORLAKE_L 0xAA
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#define INTEL_METEORLAKE_L IFM(6, 0xAA)
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#define INTEL_FAM6_ARROWLAKE_H 0xC5
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#define INTEL_ARROWLAKE_H IFM(6, 0xC5)
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#define INTEL_FAM6_ARROWLAKE 0xC6
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#define INTEL_ARROWLAKE IFM(6, 0xC6)
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#define INTEL_FAM6_ARROWLAKE_U 0xB5
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#define INTEL_ARROWLAKE_U IFM(6, 0xB5)
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#define INTEL_FAM6_LUNARLAKE_M 0xBD
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#define INTEL_LUNARLAKE_M IFM(6, 0xBD)
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/* "Small Core" Processors (Atom/E-Core) */
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#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
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#define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */
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#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
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#define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */
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#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
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#define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */
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#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
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#define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */
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#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
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#define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */
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#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
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#define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */
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#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */
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#define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */
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#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
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#define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */
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#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
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#define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */
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#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
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#define INTEL_ATOM_AIRMONT_MID IFM(6, 0x5A) /* Moorefield */
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#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
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#define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
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#define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */
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#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
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#define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */
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/* Note: the micro-architecture is "Goldmont Plus" */
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#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
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#define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */
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#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */
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#define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */
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#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
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#define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */
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#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */
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#define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */
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#define INTEL_FAM6_ATOM_GRACEMONT 0xBE /* Alderlake N */
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#define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */
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#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */
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#define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */
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#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */
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#define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */
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#define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */
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#define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest */
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/* Xeon Phi */
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#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
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#define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */
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#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
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#define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */
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/* Family 5 */
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@ -311,16 +311,18 @@ static void early_init_intel(struct cpuinfo_x86 *c)
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}
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/*
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* There is a known erratum on Pentium III and Core Solo
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* and Core Duo CPUs.
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* " Page with PAT set to WC while associated MTRR is UC
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* may consolidate to UC "
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* Because of this erratum, it is better to stick with
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* setting WC in MTRR rather than using PAT on these CPUs.
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* PAT is broken on early family 6 CPUs, the last of which
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* is "Yonah" where the erratum is named "AN7":
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*
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* Enable PAT WC only on P4, Core 2 or later CPUs.
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* Page with PAT (Page Attribute Table) Set to USWC
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* (Uncacheable Speculative Write Combine) While
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* Associated MTRR (Memory Type Range Register) Is UC
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* (Uncacheable) May Consolidate to UC
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*
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* Disable PAT and fall back to MTRR on these CPUs.
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*/
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if (c->x86 == 6 && c->x86_model < 15)
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if (c->x86_vfm >= INTEL_PENTIUM_PRO &&
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c->x86_vfm <= INTEL_CORE_YONAH)
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clear_cpu_cap(c, X86_FEATURE_PAT);
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/*
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|
||||
@ -108,7 +108,7 @@ struct axp288_extcon_info {
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id cherry_trail_cpu_ids[] = {
|
||||
X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
|
||||
X86_MATCH_VFM(INTEL_ATOM_AIRMONT, NULL),
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user