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x86/mm: Move LDT remap out of KASLR region on 5-level paging
On 5-level paging the LDT remap area is placed in the middle of the KASLR
randomization region and it can overlap with the direct mapping, the
vmalloc or the vmap area.
The LDT mapping is per mm, so it cannot be moved into the P4D page table
next to the CPU_ENTRY_AREA without complicating PGD table allocation for
5-level paging.
The 4 PGD slot gap just before the direct mapping is reserved for
hypervisors, so it cannot be used.
Move the direct mapping one slot deeper and use the resulting gap for the
LDT remap area. The resulting layout is the same for 4 and 5 level paging.
[ tglx: Massaged changelog ]
Fixes: f55f0501cb ("x86/pti: Put the LDT in its own PGD if PTI is on")
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andy Lutomirski <luto@kernel.org>
Cc: bp@alien8.de
Cc: hpa@zytor.com
Cc: dave.hansen@linux.intel.com
Cc: peterz@infradead.org
Cc: boris.ostrovsky@oracle.com
Cc: jgross@suse.com
Cc: bhe@redhat.com
Cc: willy@infradead.org
Cc: linux-mm@kvack.org
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20181026122856.66224-2-kirill.shutemov@linux.intel.com
This commit is contained in:
Kirill A. Shutemov
Thomas Gleixner
parent
e8a308e5f4
commit
d52888aa27
@ -34,23 +34,24 @@ __________________|____________|__________________|_________|___________________
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____________________________________________________________|___________________________________________________________
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ffff800000000000 | -128 TB | ffff87ffffffffff | 8 TB | ... guard hole, also reserved for hypervisor
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ffff880000000000 | -120 TB | ffffc7ffffffffff | 64 TB | direct mapping of all physical memory (page_offset_base)
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ffffc80000000000 | -56 TB | ffffc8ffffffffff | 1 TB | ... unused hole
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ffff880000000000 | -120 TB | ffff887fffffffff | 0.5 TB | LDT remap for PTI
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ffff888000000000 | -119.5 TB | ffffc87fffffffff | 64 TB | direct mapping of all physical memory (page_offset_base)
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ffffc88000000000 | -55.5 TB | ffffc8ffffffffff | 0.5 TB | ... unused hole
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ffffc90000000000 | -55 TB | ffffe8ffffffffff | 32 TB | vmalloc/ioremap space (vmalloc_base)
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ffffe90000000000 | -23 TB | ffffe9ffffffffff | 1 TB | ... unused hole
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ffffea0000000000 | -22 TB | ffffeaffffffffff | 1 TB | virtual memory map (vmemmap_base)
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ffffeb0000000000 | -21 TB | ffffebffffffffff | 1 TB | ... unused hole
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ffffec0000000000 | -20 TB | fffffbffffffffff | 16 TB | KASAN shadow memory
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__________________|____________|__________________|_________|____________________________________________________________
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| Identical layout to the 56-bit one from here on:
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____________________________________________________________|____________________________________________________________
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| | | |
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fffffc0000000000 | -4 TB | fffffdffffffffff | 2 TB | ... unused hole
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| | | | vaddr_end for KASLR
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fffffe0000000000 | -2 TB | fffffe7fffffffff | 0.5 TB | cpu_entry_area mapping
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fffffe8000000000 | -1.5 TB | fffffeffffffffff | 0.5 TB | LDT remap for PTI
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fffffe8000000000 | -1.5 TB | fffffeffffffffff | 0.5 TB | ... unused hole
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ffffff0000000000 | -1 TB | ffffff7fffffffff | 0.5 TB | %esp fixup stacks
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__________________|____________|__________________|_________|____________________________________________________________
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| Identical layout to the 47-bit one from here on:
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____________________________________________________________|____________________________________________________________
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| | | |
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ffffff8000000000 | -512 GB | ffffffeeffffffff | 444 GB | ... unused hole
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ffffffef00000000 | -68 GB | fffffffeffffffff | 64 GB | EFI region mapping space
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ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | ... unused hole
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@ -83,7 +84,7 @@ Notes:
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__________________|____________|__________________|_________|___________________________________________________________
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0000800000000000 | +64 PB | ffff7fffffffffff | ~16K PB | ... huge, still almost 64 bits wide hole of non-canonical
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| | | | virtual memory addresses up to the -128 TB
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| | | | virtual memory addresses up to the -64 PB
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| | | | starting offset of kernel mappings.
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__________________|____________|__________________|_________|___________________________________________________________
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@ -91,23 +92,24 @@ __________________|____________|__________________|_________|___________________
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____________________________________________________________|___________________________________________________________
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ff00000000000000 | -64 PB | ff0fffffffffffff | 4 PB | ... guard hole, also reserved for hypervisor
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ff10000000000000 | -60 PB | ff8fffffffffffff | 32 PB | direct mapping of all physical memory (page_offset_base)
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ff90000000000000 | -28 PB | ff9fffffffffffff | 4 PB | LDT remap for PTI
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ff10000000000000 | -60 PB | ff10ffffffffffff | 0.25 PB | LDT remap for PTI
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ff11000000000000 | -59.75 PB | ff90ffffffffffff | 32 PB | direct mapping of all physical memory (page_offset_base)
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ff91000000000000 | -27.75 PB | ff9fffffffffffff | 3.75 PB | ... unused hole
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ffa0000000000000 | -24 PB | ffd1ffffffffffff | 12.5 PB | vmalloc/ioremap space (vmalloc_base)
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ffd2000000000000 | -11.5 PB | ffd3ffffffffffff | 0.5 PB | ... unused hole
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ffd4000000000000 | -11 PB | ffd5ffffffffffff | 0.5 PB | virtual memory map (vmemmap_base)
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ffd6000000000000 | -10.5 PB | ffdeffffffffffff | 2.25 PB | ... unused hole
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ffdf000000000000 | -8.25 PB | fffffdffffffffff | ~8 PB | KASAN shadow memory
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fffffc0000000000 | -4 TB | fffffdffffffffff | 2 TB | ... unused hole
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| | | | vaddr_end for KASLR
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fffffe0000000000 | -2 TB | fffffe7fffffffff | 0.5 TB | cpu_entry_area mapping
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fffffe8000000000 | -1.5 TB | fffffeffffffffff | 0.5 TB | ... unused hole
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ffffff0000000000 | -1 TB | ffffff7fffffffff | 0.5 TB | %esp fixup stacks
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__________________|____________|__________________|_________|____________________________________________________________
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| Identical layout to the 47-bit one from here on:
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____________________________________________________________|____________________________________________________________
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| | | |
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fffffc0000000000 | -4 TB | fffffdffffffffff | 2 TB | ... unused hole
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| | | | vaddr_end for KASLR
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fffffe0000000000 | -2 TB | fffffe7fffffffff | 0.5 TB | cpu_entry_area mapping
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fffffe8000000000 | -1.5 TB | fffffeffffffffff | 0.5 TB | ... unused hole
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ffffff0000000000 | -1 TB | ffffff7fffffffff | 0.5 TB | %esp fixup stacks
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ffffff8000000000 | -512 GB | ffffffeeffffffff | 444 GB | ... unused hole
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ffffffef00000000 | -68 GB | fffffffeffffffff | 64 GB | EFI region mapping space
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ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | ... unused hole
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@ -33,12 +33,14 @@
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/*
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* Set __PAGE_OFFSET to the most negative possible address +
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* PGDIR_SIZE*16 (pgd slot 272). The gap is to allow a space for a
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* hypervisor to fit. Choosing 16 slots here is arbitrary, but it's
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* what Xen requires.
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* PGDIR_SIZE*17 (pgd slot 273).
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*
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* The gap is to allow a space for LDT remap for PTI (1 pgd slot) and space for
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* a hypervisor (16 slots). Choosing 16 slots for a hypervisor is arbitrary,
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* but it's what Xen requires.
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*/
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#define __PAGE_OFFSET_BASE_L5 _AC(0xff10000000000000, UL)
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#define __PAGE_OFFSET_BASE_L4 _AC(0xffff880000000000, UL)
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#define __PAGE_OFFSET_BASE_L5 _AC(0xff11000000000000, UL)
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#define __PAGE_OFFSET_BASE_L4 _AC(0xffff888000000000, UL)
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#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
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#define __PAGE_OFFSET page_offset_base
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@ -111,9 +111,7 @@ extern unsigned int ptrs_per_p4d;
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*/
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#define MAXMEM (1UL << MAX_PHYSMEM_BITS)
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#define LDT_PGD_ENTRY_L4 -3UL
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#define LDT_PGD_ENTRY_L5 -112UL
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#define LDT_PGD_ENTRY (pgtable_l5_enabled() ? LDT_PGD_ENTRY_L5 : LDT_PGD_ENTRY_L4)
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#define LDT_PGD_ENTRY -240UL
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#define LDT_BASE_ADDR (LDT_PGD_ENTRY << PGDIR_SHIFT)
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#define LDT_END_ADDR (LDT_BASE_ADDR + PGDIR_SIZE)
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@ -1905,7 +1905,7 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
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init_top_pgt[0] = __pgd(0);
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/* Pre-constructed entries are in pfn, so convert to mfn */
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/* L4[272] -> level3_ident_pgt */
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/* L4[273] -> level3_ident_pgt */
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/* L4[511] -> level3_kernel_pgt */
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convert_pfn_mfn(init_top_pgt);
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@ -1925,8 +1925,8 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
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addr[0] = (unsigned long)pgd;
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addr[1] = (unsigned long)l3;
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addr[2] = (unsigned long)l2;
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/* Graft it onto L4[272][0]. Note that we creating an aliasing problem:
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* Both L4[272][0] and L4[511][510] have entries that point to the same
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/* Graft it onto L4[273][0]. Note that we creating an aliasing problem:
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* Both L4[273][0] and L4[511][510] have entries that point to the same
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* L2 (PMD) tables. Meaning that if you modify it in __va space
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* it will be also modified in the __ka space! (But if you just
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* modify the PMD table to point to other PTE's or none, then you
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