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RISC-V Devicetrees for v6.4
Microchip: A "fix" for the system controller's regs on PolarFire SoC, adding a missing reg property. The patch had been sitting there for months and I only re-found it recently, so you can guess how much of a "fix" it actually is. It'll become needed when the system controller's QSPI gets added in the future, but at present there's no urgency as the driver can handle both the current and "fixed" versions. StarFive: Basic support for the JH7110 & the associated first-party dev board, the VisionFive v2 (in two forms). There's a bunch of dt-bindings required for this too, all of which have had input from the DT folk. There's enough in this tag to boot to a console w/ an initramfs but little more. The SoC supports some of the "new" bit manipulation instructions, which is a good test for the recently added Zbb support in the kernel. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZC8o6wAKCRB4tDGHoIJi 0pdpAP0Y0qkT5tZSV635h2XOrWBpW3D3Vpx6+LGmw2mRjhHVPgD+Mfe0LkP6Dbq3 JS6fMISbgMAG/8dqcys/e0gmHksYJAk= =FsQ1 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmQ5U/EACgkQYKtH/8kJ Uif0hhAAxHk3QfPh5BF/1TzzUdeOgXuCiT9sQWHB9VtX1N03nwRoMETbFPRxjI1v P/KckzA5nxVA8q8Me+hb5nRQFwiDOVsH5cBMMnPQ46NGImEaptZ7Jwf1/RT1yk6n eBg9vRipRhD56CYTE20iasjhwjVohljvce58Rg61oXQ2lK1dKxnIjPeDfypPz9/p 149/wWUy8e6pGIciDw25hKGuxZiXHlO4OwdL0yWggXl/iuBi8l7gAQAcCv7vWNS3 oM8t6n/o1Vr0L+MBJtBBKPmuPKu7u54+RWsaKrO3zyiRRKGjI/VMZOi5ZKcooynL ThAGlqCIrnXu25XJ2V7l95FDTdPeTljhh1FRyOIJjvzlCX9QBdr5suQU3q9zr+Mf ZdE5baezkwsTF+1Hi/Yc65gCAtUfQmGG88/TE1krFw4aaE1xVr7nAfDCpdLcCzDS D/1b9/4h/2B2dJIdBO3VdzKG4bTcaK3Eb6TX6z2zIZ6stNHcoDxr6dcQXdiGAoYu /I8zAX3zTo5Q8E0Y67h7ao4dxDqxVUIop/92OJeD3X3IkcJreXEuxBEEsRvs53P6 /tqAsG5zPpW5GwfeopUHfFUYJRn+sLrqQ9zD+k4InwiCSlR/tJ7tBMXqyRsQUEyR P336MHjq10PRVmgKjsPpTx87K9f39Qgh6doHWAKBfMo/gSQ8z9U= =l6EI -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.4 Microchip: A "fix" for the system controller's regs on PolarFire SoC, adding a missing reg property. The patch had been sitting there for months and I only re-found it recently, so you can guess how much of a "fix" it actually is. It'll become needed when the system controller's QSPI gets added in the future, but at present there's no urgency as the driver can handle both the current and "fixed" versions. StarFive: Basic support for the JH7110 & the associated first-party dev board, the VisionFive v2 (in two forms). There's a bunch of dt-bindings required for this too, all of which have had input from the DT folk. There's enough in this tag to boot to a console w/ an initramfs but little more. The SoC supports some of the "new" bit manipulation instructions, which is a good test for the recently added Zbb support in the kernel. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree riscv: dts: starfive: Add StarFive JH7110 pin function definitions riscv: dts: starfive: Add initial StarFive JH7110 device tree dt-bindings: riscv: Add SiFive S7 compatible dt-bindings: interrupt-controller: Add StarFive JH7110 plic dt-bindings: timer: Add StarFive JH7110 clint dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator dt-bindings: clock: Add StarFive JH7110 system clock and reset generator riscv: dts: microchip: fix the mpfs' mailbox regs riscv: dts: microchip: add mpfs specific macb reset support Link: https://lore.kernel.org/r/20230406-shank-impromptu-3d483bbc249f@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d40a2f5062
@ -0,0 +1,107 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Always-On Clock and Reset Generator
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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properties:
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compatible:
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const: starfive,jh7110-aoncrg
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC0 RMII reference or GMAC0 RGMII RX
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- description: STG AXI/AHB
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- description: APB Bus
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- description: GMAC0 GTX
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC0 RMII reference or GMAC0 RGMII RX
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- description: STG AXI/AHB or GMAC0 RGMII RX
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- description: APB Bus or STG AXI/AHB
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- description: GMAC0 GTX or APB Bus
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- description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC0 RMII reference
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- description: GMAC0 RGMII RX
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- description: STG AXI/AHB
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- description: APB Bus
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- description: GMAC0 GTX
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- description: RTC Oscillator (32.768 kHz)
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clock-names:
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oneOf:
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- minItems: 5
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items:
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- const: osc
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- enum:
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- gmac0_rmii_refin
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- gmac0_rgmii_rxin
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- const: stg_axiahb
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- const: apb_bus
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- const: gmac0_gtxclk
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- const: rtc_osc
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- minItems: 6
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items:
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- const: osc
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- const: gmac0_rmii_refin
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- const: gmac0_rgmii_rxin
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- const: stg_axiahb
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- const: apb_bus
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- const: gmac0_gtxclk
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- const: rtc_osc
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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clock-controller@17000000 {
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compatible = "starfive,jh7110-aoncrg";
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reg = <0x17000000 0x10000>;
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clocks = <&osc>, <&gmac0_rmii_refin>,
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<&gmac0_rgmii_rxin>,
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<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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<&syscrg JH7110_SYSCLK_APB_BUS>,
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<&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
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<&rtc_osc>;
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clock-names = "osc", "gmac0_rmii_refin",
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"gmac0_rgmii_rxin", "stg_axiahb",
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"apb_bus", "gmac0_gtxclk",
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"rtc_osc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -0,0 +1,104 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 System Clock and Reset Generator
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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properties:
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compatible:
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const: starfive,jh7110-syscrg
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC1 RMII reference or GMAC1 RGMII RX
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- description: External I2S TX bit clock
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- description: External I2S TX left/right channel clock
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- description: External I2S RX bit clock
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC1 RMII reference
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- description: GMAC1 RGMII RX
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- description: External I2S TX bit clock
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- description: External I2S TX left/right channel clock
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- description: External I2S RX bit clock
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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clock-names:
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oneOf:
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- items:
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- const: osc
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- enum:
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- gmac1_rmii_refin
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- gmac1_rgmii_rxin
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- const: i2stx_bclk_ext
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- const: i2stx_lrck_ext
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- const: i2srx_bclk_ext
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- items:
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- const: osc
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- const: gmac1_rmii_refin
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- const: gmac1_rgmii_rxin
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- const: i2stx_bclk_ext
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- const: i2stx_lrck_ext
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- const: i2srx_bclk_ext
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@13020000 {
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compatible = "starfive,jh7110-syscrg";
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reg = <0x13020000 0x10000>;
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clocks = <&osc>, <&gmac1_rmii_refin>,
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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<&tdm_ext>, <&mclk_ext>;
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clock-names = "osc", "gmac1_rmii_refin",
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"gmac1_rgmii_rxin",
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"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
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"tdm_ext", "mclk_ext";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -59,6 +59,7 @@ properties:
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- enum:
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- sifive,fu540-c000-plic
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- starfive,jh7100-plic
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- starfive,jh7110-plic
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- canaan,k210-plic
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- const: sifive,plic-1.0.0
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- items:
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@ -35,6 +35,7 @@ properties:
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- sifive,e7
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- sifive,e71
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- sifive,rocket0
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- sifive,s7
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- sifive,u5
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- sifive,u54
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- sifive,u7
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@ -31,6 +31,7 @@ properties:
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- enum:
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- sifive,fu540-c000-clint
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- starfive,jh7100-clint
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- starfive,jh7110-clint
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- canaan,k210-clint
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- const: sifive,clint0
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- items:
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@ -234,6 +234,7 @@
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reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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clocks = <&refclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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ccc_se: clock-controller@38010000 {
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@ -415,7 +416,7 @@
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};
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mac0: ethernet@20110000 {
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compatible = "cdns,macb";
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compatible = "microchip,mpfs-macb", "cdns,macb";
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reg = <0x0 0x20110000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -424,11 +425,12 @@
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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resets = <&clkcfg CLK_MAC0>;
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status = "disabled";
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};
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mac1: ethernet@20112000 {
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compatible = "cdns,macb";
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compatible = "microchip,mpfs-macb", "cdns,macb";
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reg = <0x0 0x20112000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -437,6 +439,7 @@
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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resets = <&clkcfg CLK_MAC1>;
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status = "disabled";
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};
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@ -498,7 +501,8 @@
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mbox: mailbox@37020000 {
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compatible = "microchip,mpfs-mailbox";
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reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
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reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
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<0x0 0x37020800 0x0 0x100>;
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interrupt-parent = <&plic>;
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interrupts = <96>;
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#mbox-cells = <1>;
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@ -1,2 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
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308
arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
Normal file
308
arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
Normal file
@ -0,0 +1,308 @@
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#ifndef __JH7110_PINFUNC_H__
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#define __JH7110_PINFUNC_H__
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/*
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* mux bits:
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* | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
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* | din | dout | doen | function | gpio nr |
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*
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||||
* dout: output signal
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||||
* doen: output enable signal
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* din: optional input signal, 0xff = none
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* function: function selector
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* gpio nr: gpio number, 0 - 63
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*/
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#define GPIOMUX(n, dout, doen, din) ( \
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(((din) & 0xff) << 24) | \
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(((dout) & 0xff) << 16) | \
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(((doen) & 0x3f) << 10) | \
|
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((n) & 0x3f))
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#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff))
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/* sys_iomux dout */
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#define GPOUT_LOW 0
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#define GPOUT_HIGH 1
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#define GPOUT_SYS_WAVE511_UART_TX 2
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#define GPOUT_SYS_CAN0_STBY 3
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#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4
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#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5
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||||
#define GPOUT_SYS_CAN0_TXD 6
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||||
#define GPOUT_SYS_USB_DRIVE_VBUS 7
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||||
#define GPOUT_SYS_QSPI_CS1 8
|
||||
#define GPOUT_SYS_SPDIF 9
|
||||
#define GPOUT_SYS_HDMI_CEC_SDA 10
|
||||
#define GPOUT_SYS_HDMI_DDC_SCL 11
|
||||
#define GPOUT_SYS_HDMI_DDC_SDA 12
|
||||
#define GPOUT_SYS_WATCHDOG 13
|
||||
#define GPOUT_SYS_I2C0_CLK 14
|
||||
#define GPOUT_SYS_I2C0_DATA 15
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||||
#define GPOUT_SYS_SDIO0_BACK_END_POWER 16
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||||
#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17
|
||||
#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18
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||||
#define GPOUT_SYS_SDIO0_RST 19
|
||||
#define GPOUT_SYS_UART0_TX 20
|
||||
#define GPOUT_SYS_HIFI4_JTAG_TDO 21
|
||||
#define GPOUT_SYS_JTAG_TDO 22
|
||||
#define GPOUT_SYS_PDM_MCLK 23
|
||||
#define GPOUT_SYS_PWM_CHANNEL0 24
|
||||
#define GPOUT_SYS_PWM_CHANNEL1 25
|
||||
#define GPOUT_SYS_PWM_CHANNEL2 26
|
||||
#define GPOUT_SYS_PWM_CHANNEL3 27
|
||||
#define GPOUT_SYS_PWMDAC_LEFT 28
|
||||
#define GPOUT_SYS_PWMDAC_RIGHT 29
|
||||
#define GPOUT_SYS_SPI0_CLK 30
|
||||
#define GPOUT_SYS_SPI0_FSS 31
|
||||
#define GPOUT_SYS_SPI0_TXD 32
|
||||
#define GPOUT_SYS_GMAC_PHYCLK 33
|
||||
#define GPOUT_SYS_I2SRX_BCLK 34
|
||||
#define GPOUT_SYS_I2SRX_LRCK 35
|
||||
#define GPOUT_SYS_I2STX0_BCLK 36
|
||||
#define GPOUT_SYS_I2STX0_LRCK 37
|
||||
#define GPOUT_SYS_MCLK 38
|
||||
#define GPOUT_SYS_TDM_CLK 39
|
||||
#define GPOUT_SYS_TDM_SYNC 40
|
||||
#define GPOUT_SYS_TDM_TXD 41
|
||||
#define GPOUT_SYS_TRACE_DATA0 42
|
||||
#define GPOUT_SYS_TRACE_DATA1 43
|
||||
#define GPOUT_SYS_TRACE_DATA2 44
|
||||
#define GPOUT_SYS_TRACE_DATA3 45
|
||||
#define GPOUT_SYS_TRACE_REF 46
|
||||
#define GPOUT_SYS_CAN1_STBY 47
|
||||
#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48
|
||||
#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49
|
||||
#define GPOUT_SYS_CAN1_TXD 50
|
||||
#define GPOUT_SYS_I2C1_CLK 51
|
||||
#define GPOUT_SYS_I2C1_DATA 52
|
||||
#define GPOUT_SYS_SDIO1_BACK_END_POWER 53
|
||||
#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54
|
||||
#define GPOUT_SYS_SDIO1_CLK 55
|
||||
#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56
|
||||
#define GPOUT_SYS_SDIO1_CMD 57
|
||||
#define GPOUT_SYS_SDIO1_DATA0 58
|
||||
#define GPOUT_SYS_SDIO1_DATA1 59
|
||||
#define GPOUT_SYS_SDIO1_DATA2 60
|
||||
#define GPOUT_SYS_SDIO1_DATA3 61
|
||||
#define GPOUT_SYS_SDIO1_DATA4 63
|
||||
#define GPOUT_SYS_SDIO1_DATA5 63
|
||||
#define GPOUT_SYS_SDIO1_DATA6 64
|
||||
#define GPOUT_SYS_SDIO1_DATA7 65
|
||||
#define GPOUT_SYS_SDIO1_RST 66
|
||||
#define GPOUT_SYS_UART1_RTS 67
|
||||
#define GPOUT_SYS_UART1_TX 68
|
||||
#define GPOUT_SYS_I2STX1_SDO0 69
|
||||
#define GPOUT_SYS_I2STX1_SDO1 70
|
||||
#define GPOUT_SYS_I2STX1_SDO2 71
|
||||
#define GPOUT_SYS_I2STX1_SDO3 72
|
||||
#define GPOUT_SYS_SPI1_CLK 73
|
||||
#define GPOUT_SYS_SPI1_FSS 74
|
||||
#define GPOUT_SYS_SPI1_TXD 75
|
||||
#define GPOUT_SYS_I2C2_CLK 76
|
||||
#define GPOUT_SYS_I2C2_DATA 77
|
||||
#define GPOUT_SYS_UART2_RTS 78
|
||||
#define GPOUT_SYS_UART2_TX 79
|
||||
#define GPOUT_SYS_SPI2_CLK 80
|
||||
#define GPOUT_SYS_SPI2_FSS 81
|
||||
#define GPOUT_SYS_SPI2_TXD 82
|
||||
#define GPOUT_SYS_I2C3_CLK 83
|
||||
#define GPOUT_SYS_I2C3_DATA 84
|
||||
#define GPOUT_SYS_UART3_TX 85
|
||||
#define GPOUT_SYS_SPI3_CLK 86
|
||||
#define GPOUT_SYS_SPI3_FSS 87
|
||||
#define GPOUT_SYS_SPI3_TXD 88
|
||||
#define GPOUT_SYS_I2C4_CLK 89
|
||||
#define GPOUT_SYS_I2C4_DATA 90
|
||||
#define GPOUT_SYS_UART4_RTS 91
|
||||
#define GPOUT_SYS_UART4_TX 92
|
||||
#define GPOUT_SYS_SPI4_CLK 93
|
||||
#define GPOUT_SYS_SPI4_FSS 94
|
||||
#define GPOUT_SYS_SPI4_TXD 95
|
||||
#define GPOUT_SYS_I2C5_CLK 96
|
||||
#define GPOUT_SYS_I2C5_DATA 97
|
||||
#define GPOUT_SYS_UART5_RTS 98
|
||||
#define GPOUT_SYS_UART5_TX 99
|
||||
#define GPOUT_SYS_SPI5_CLK 100
|
||||
#define GPOUT_SYS_SPI5_FSS 101
|
||||
#define GPOUT_SYS_SPI5_TXD 102
|
||||
#define GPOUT_SYS_I2C6_CLK 103
|
||||
#define GPOUT_SYS_I2C6_DATA 104
|
||||
#define GPOUT_SYS_SPI6_CLK 105
|
||||
#define GPOUT_SYS_SPI6_FSS 106
|
||||
#define GPOUT_SYS_SPI6_TXD 107
|
||||
|
||||
/* aon_iomux dout */
|
||||
#define GPOUT_AON_CLK_32K_OUT 2
|
||||
#define GPOUT_AON_PTC0_PWM4 3
|
||||
#define GPOUT_AON_PTC0_PWM5 4
|
||||
#define GPOUT_AON_PTC0_PWM6 5
|
||||
#define GPOUT_AON_PTC0_PWM7 6
|
||||
#define GPOUT_AON_CLK_GCLK0 7
|
||||
#define GPOUT_AON_CLK_GCLK1 8
|
||||
#define GPOUT_AON_CLK_GCLK2 9
|
||||
|
||||
/* sys_iomux doen */
|
||||
#define GPOEN_ENABLE 0
|
||||
#define GPOEN_DISABLE 1
|
||||
#define GPOEN_SYS_HDMI_CEC_SDA 2
|
||||
#define GPOEN_SYS_HDMI_DDC_SCL 3
|
||||
#define GPOEN_SYS_HDMI_DDC_SDA 4
|
||||
#define GPOEN_SYS_I2C0_CLK 5
|
||||
#define GPOEN_SYS_I2C0_DATA 6
|
||||
#define GPOEN_SYS_HIFI4_JTAG_TDO 7
|
||||
#define GPOEN_SYS_JTAG_TDO 8
|
||||
#define GPOEN_SYS_PWM0_CHANNEL0 9
|
||||
#define GPOEN_SYS_PWM0_CHANNEL1 10
|
||||
#define GPOEN_SYS_PWM0_CHANNEL2 11
|
||||
#define GPOEN_SYS_PWM0_CHANNEL3 12
|
||||
#define GPOEN_SYS_SPI0_NSSPCTL 13
|
||||
#define GPOEN_SYS_SPI0_NSSP 14
|
||||
#define GPOEN_SYS_TDM_SYNC 15
|
||||
#define GPOEN_SYS_TDM_TXD 16
|
||||
#define GPOEN_SYS_I2C1_CLK 17
|
||||
#define GPOEN_SYS_I2C1_DATA 18
|
||||
#define GPOEN_SYS_SDIO1_CMD 19
|
||||
#define GPOEN_SYS_SDIO1_DATA0 20
|
||||
#define GPOEN_SYS_SDIO1_DATA1 21
|
||||
#define GPOEN_SYS_SDIO1_DATA2 22
|
||||
#define GPOEN_SYS_SDIO1_DATA3 23
|
||||
#define GPOEN_SYS_SDIO1_DATA4 24
|
||||
#define GPOEN_SYS_SDIO1_DATA5 25
|
||||
#define GPOEN_SYS_SDIO1_DATA6 26
|
||||
#define GPOEN_SYS_SDIO1_DATA7 27
|
||||
#define GPOEN_SYS_SPI1_NSSPCTL 28
|
||||
#define GPOEN_SYS_SPI1_NSSP 29
|
||||
#define GPOEN_SYS_I2C2_CLK 30
|
||||
#define GPOEN_SYS_I2C2_DATA 31
|
||||
#define GPOEN_SYS_SPI2_NSSPCTL 32
|
||||
#define GPOEN_SYS_SPI2_NSSP 33
|
||||
#define GPOEN_SYS_I2C3_CLK 34
|
||||
#define GPOEN_SYS_I2C3_DATA 35
|
||||
#define GPOEN_SYS_SPI3_NSSPCTL 36
|
||||
#define GPOEN_SYS_SPI3_NSSP 37
|
||||
#define GPOEN_SYS_I2C4_CLK 38
|
||||
#define GPOEN_SYS_I2C4_DATA 39
|
||||
#define GPOEN_SYS_SPI4_NSSPCTL 40
|
||||
#define GPOEN_SYS_SPI4_NSSP 41
|
||||
#define GPOEN_SYS_I2C5_CLK 42
|
||||
#define GPOEN_SYS_I2C5_DATA 43
|
||||
#define GPOEN_SYS_SPI5_NSSPCTL 44
|
||||
#define GPOEN_SYS_SPI5_NSSP 45
|
||||
#define GPOEN_SYS_I2C6_CLK 46
|
||||
#define GPOEN_SYS_I2C6_DATA 47
|
||||
#define GPOEN_SYS_SPI6_NSSPCTL 48
|
||||
#define GPOEN_SYS_SPI6_NSSP 49
|
||||
|
||||
/* aon_iomux doen */
|
||||
#define GPOEN_AON_PTC0_OE_N_4 2
|
||||
#define GPOEN_AON_PTC0_OE_N_5 3
|
||||
#define GPOEN_AON_PTC0_OE_N_6 4
|
||||
#define GPOEN_AON_PTC0_OE_N_7 5
|
||||
|
||||
/* sys_iomux gin */
|
||||
#define GPI_NONE 255
|
||||
|
||||
#define GPI_SYS_WAVE511_UART_RX 0
|
||||
#define GPI_SYS_CAN0_RXD 1
|
||||
#define GPI_SYS_USB_OVERCURRENT 2
|
||||
#define GPI_SYS_SPDIF 3
|
||||
#define GPI_SYS_JTAG_RST 4
|
||||
#define GPI_SYS_HDMI_CEC_SDA 5
|
||||
#define GPI_SYS_HDMI_DDC_SCL 6
|
||||
#define GPI_SYS_HDMI_DDC_SDA 7
|
||||
#define GPI_SYS_HDMI_HPD 8
|
||||
#define GPI_SYS_I2C0_CLK 9
|
||||
#define GPI_SYS_I2C0_DATA 10
|
||||
#define GPI_SYS_SDIO0_CD 11
|
||||
#define GPI_SYS_SDIO0_INT 12
|
||||
#define GPI_SYS_SDIO0_WP 13
|
||||
#define GPI_SYS_UART0_RX 14
|
||||
#define GPI_SYS_HIFI4_JTAG_TCK 15
|
||||
#define GPI_SYS_HIFI4_JTAG_TDI 16
|
||||
#define GPI_SYS_HIFI4_JTAG_TMS 17
|
||||
#define GPI_SYS_HIFI4_JTAG_RST 18
|
||||
#define GPI_SYS_JTAG_TDI 19
|
||||
#define GPI_SYS_JTAG_TMS 20
|
||||
#define GPI_SYS_PDM_DMIC0 21
|
||||
#define GPI_SYS_PDM_DMIC1 22
|
||||
#define GPI_SYS_I2SRX_SDIN0 23
|
||||
#define GPI_SYS_I2SRX_SDIN1 24
|
||||
#define GPI_SYS_I2SRX_SDIN2 25
|
||||
#define GPI_SYS_SPI0_CLK 26
|
||||
#define GPI_SYS_SPI0_FSS 27
|
||||
#define GPI_SYS_SPI0_RXD 28
|
||||
#define GPI_SYS_JTAG_TCK 29
|
||||
#define GPI_SYS_MCLK_EXT 30
|
||||
#define GPI_SYS_I2SRX_BCLK 31
|
||||
#define GPI_SYS_I2SRX_LRCK 32
|
||||
#define GPI_SYS_I2STX0_BCLK 33
|
||||
#define GPI_SYS_I2STX0_LRCK 34
|
||||
#define GPI_SYS_TDM_CLK 35
|
||||
#define GPI_SYS_TDM_RXD 36
|
||||
#define GPI_SYS_TDM_SYNC 37
|
||||
#define GPI_SYS_CAN1_RXD 38
|
||||
#define GPI_SYS_I2C1_CLK 39
|
||||
#define GPI_SYS_I2C1_DATA 40
|
||||
#define GPI_SYS_SDIO1_CD 41
|
||||
#define GPI_SYS_SDIO1_INT 42
|
||||
#define GPI_SYS_SDIO1_WP 43
|
||||
#define GPI_SYS_SDIO1_CMD 44
|
||||
#define GPI_SYS_SDIO1_DATA0 45
|
||||
#define GPI_SYS_SDIO1_DATA1 46
|
||||
#define GPI_SYS_SDIO1_DATA2 47
|
||||
#define GPI_SYS_SDIO1_DATA3 48
|
||||
#define GPI_SYS_SDIO1_DATA4 49
|
||||
#define GPI_SYS_SDIO1_DATA5 50
|
||||
#define GPI_SYS_SDIO1_DATA6 51
|
||||
#define GPI_SYS_SDIO1_DATA7 52
|
||||
#define GPI_SYS_SDIO1_STRB 53
|
||||
#define GPI_SYS_UART1_CTS 54
|
||||
#define GPI_SYS_UART1_RX 55
|
||||
#define GPI_SYS_SPI1_CLK 56
|
||||
#define GPI_SYS_SPI1_FSS 57
|
||||
#define GPI_SYS_SPI1_RXD 58
|
||||
#define GPI_SYS_I2C2_CLK 59
|
||||
#define GPI_SYS_I2C2_DATA 60
|
||||
#define GPI_SYS_UART2_CTS 61
|
||||
#define GPI_SYS_UART2_RX 62
|
||||
#define GPI_SYS_SPI2_CLK 63
|
||||
#define GPI_SYS_SPI2_FSS 64
|
||||
#define GPI_SYS_SPI2_RXD 65
|
||||
#define GPI_SYS_I2C3_CLK 66
|
||||
#define GPI_SYS_I2C3_DATA 67
|
||||
#define GPI_SYS_UART3_RX 68
|
||||
#define GPI_SYS_SPI3_CLK 69
|
||||
#define GPI_SYS_SPI3_FSS 70
|
||||
#define GPI_SYS_SPI3_RXD 71
|
||||
#define GPI_SYS_I2C4_CLK 72
|
||||
#define GPI_SYS_I2C4_DATA 73
|
||||
#define GPI_SYS_UART4_CTS 74
|
||||
#define GPI_SYS_UART4_RX 75
|
||||
#define GPI_SYS_SPI4_CLK 76
|
||||
#define GPI_SYS_SPI4_FSS 77
|
||||
#define GPI_SYS_SPI4_RXD 78
|
||||
#define GPI_SYS_I2C5_CLK 79
|
||||
#define GPI_SYS_I2C5_DATA 80
|
||||
#define GPI_SYS_UART5_CTS 81
|
||||
#define GPI_SYS_UART5_RX 82
|
||||
#define GPI_SYS_SPI5_CLK 83
|
||||
#define GPI_SYS_SPI5_FSS 84
|
||||
#define GPI_SYS_SPI5_RXD 85
|
||||
#define GPI_SYS_I2C6_CLK 86
|
||||
#define GPI_SYS_I2C6_DATA 87
|
||||
#define GPI_SYS_SPI6_CLK 88
|
||||
#define GPI_SYS_SPI6_FSS 89
|
||||
#define GPI_SYS_SPI6_RXD 90
|
||||
|
||||
/* aon_iomux gin */
|
||||
#define GPI_AON_PMU_GPIO_WAKEUP_0 0
|
||||
#define GPI_AON_PMU_GPIO_WAKEUP_1 1
|
||||
#define GPI_AON_PMU_GPIO_WAKEUP_2 2
|
||||
#define GPI_AON_PMU_GPIO_WAKEUP_3 3
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2022 StarFive Technology Co., Ltd.
|
||||
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "jh7110-starfive-visionfive-2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "StarFive VisionFive 2 v1.2A";
|
||||
compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
|
||||
};
|
||||
@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2022 StarFive Technology Co., Ltd.
|
||||
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "jh7110-starfive-visionfive-2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "StarFive VisionFive 2 v1.3B";
|
||||
compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
|
||||
};
|
||||
215
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
Normal file
215
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
Normal file
@ -0,0 +1,215 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2022 StarFive Technology Co., Ltd.
|
||||
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "jh7110.dtsi"
|
||||
#include "jh7110-pinfunc.h"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c2 = &i2c2;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
timebase-frequency = <4000000>;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0x1 0x0>;
|
||||
};
|
||||
|
||||
gpio-restart {
|
||||
compatible = "gpio-restart";
|
||||
gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
|
||||
priority = <224>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0_rgmii_rxin {
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
&gmac0_rmii_refin {
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
&gmac1_rgmii_rxin {
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
&gmac1_rmii_refin {
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
&i2srx_bclk_ext {
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
&i2srx_lrck_ext {
|
||||
clock-frequency = <192000>;
|
||||
};
|
||||
|
||||
&i2stx_bclk_ext {
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
&i2stx_lrck_ext {
|
||||
clock-frequency = <192000>;
|
||||
};
|
||||
|
||||
&mclk_ext {
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
&osc {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&rtc_osc {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&tdm_ext {
|
||||
clock-frequency = <49152000>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <510>;
|
||||
i2c-scl-falling-time-ns = <510>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <510>;
|
||||
i2c-scl-falling-time-ns = <510>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <510>;
|
||||
i2c-scl-falling-time-ns = <510>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <510>;
|
||||
i2c-scl-falling-time-ns = <510>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sysgpio {
|
||||
i2c0_pins: i2c0-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(57, GPOUT_LOW,
|
||||
GPOEN_SYS_I2C0_CLK,
|
||||
GPI_SYS_I2C0_CLK)>,
|
||||
<GPIOMUX(58, GPOUT_LOW,
|
||||
GPOEN_SYS_I2C0_DATA,
|
||||
GPI_SYS_I2C0_DATA)>;
|
||||
bias-disable; /* external pull-up */
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(3, GPOUT_LOW,
|
||||
GPOEN_SYS_I2C2_CLK,
|
||||
GPI_SYS_I2C2_CLK)>,
|
||||
<GPIOMUX(2, GPOUT_LOW,
|
||||
GPOEN_SYS_I2C2_DATA,
|
||||
GPI_SYS_I2C2_DATA)>;
|
||||
bias-disable; /* external pull-up */
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c5_pins: i2c5-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(19, GPOUT_LOW,
|
||||
GPOEN_SYS_I2C5_CLK,
|
||||
GPI_SYS_I2C5_CLK)>,
|
||||
<GPIOMUX(20, GPOUT_LOW,
|
||||
GPOEN_SYS_I2C5_DATA,
|
||||
GPI_SYS_I2C5_DATA)>;
|
||||
bias-disable; /* external pull-up */
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c6_pins: i2c6-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(16, GPOUT_LOW,
|
||||
GPOEN_SYS_I2C6_CLK,
|
||||
GPI_SYS_I2C6_CLK)>,
|
||||
<GPIOMUX(17, GPOUT_LOW,
|
||||
GPOEN_SYS_I2C6_DATA,
|
||||
GPI_SYS_I2C6_DATA)>;
|
||||
bias-disable; /* external pull-up */
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-0 {
|
||||
tx-pins {
|
||||
pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
|
||||
GPOEN_ENABLE,
|
||||
GPI_NONE)>;
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
|
||||
rx-pins {
|
||||
pinmux = <GPIOMUX(6, GPOUT_LOW,
|
||||
GPOEN_DISABLE,
|
||||
GPI_SYS_UART0_RX)>;
|
||||
bias-disable; /* external pull-up */
|
||||
drive-strength = <2>;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
500
arch/riscv/boot/dts/starfive/jh7110.dtsi
Normal file
500
arch/riscv/boot/dts/starfive/jh7110.dtsi
Normal file
@ -0,0 +1,500 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2022 StarFive Technology Co., Ltd.
|
||||
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/clock/starfive,jh7110-crg.h>
|
||||
#include <dt-bindings/reset/starfive,jh7110-crg.h>
|
||||
|
||||
/ {
|
||||
compatible = "starfive,jh7110";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
S7_0: cpu@0 {
|
||||
compatible = "sifive,s7", "riscv";
|
||||
reg = <0>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <16384>;
|
||||
next-level-cache = <&ccache>;
|
||||
riscv,isa = "rv64imac_zba_zbb";
|
||||
status = "disabled";
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
U74_1: cpu@1 {
|
||||
compatible = "sifive,u74-mc", "riscv";
|
||||
reg = <1>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <40>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <40>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <&ccache>;
|
||||
riscv,isa = "rv64imafdc_zba_zbb";
|
||||
tlb-split;
|
||||
|
||||
cpu1_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
U74_2: cpu@2 {
|
||||
compatible = "sifive,u74-mc", "riscv";
|
||||
reg = <2>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <40>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <40>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <&ccache>;
|
||||
riscv,isa = "rv64imafdc_zba_zbb";
|
||||
tlb-split;
|
||||
|
||||
cpu2_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
U74_3: cpu@3 {
|
||||
compatible = "sifive,u74-mc", "riscv";
|
||||
reg = <3>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <40>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <40>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <&ccache>;
|
||||
riscv,isa = "rv64imafdc_zba_zbb";
|
||||
tlb-split;
|
||||
|
||||
cpu3_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
U74_4: cpu@4 {
|
||||
compatible = "sifive,u74-mc", "riscv";
|
||||
reg = <4>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <40>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <40>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <&ccache>;
|
||||
riscv,isa = "rv64imafdc_zba_zbb";
|
||||
tlb-split;
|
||||
|
||||
cpu4_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&S7_0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&U74_1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&U74_2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&U74_3>;
|
||||
};
|
||||
|
||||
core4 {
|
||||
cpu = <&U74_4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "gmac0_rgmii_rxin";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
gmac0_rmii_refin: gmac0-rmii-refin-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "gmac0_rmii_refin";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "gmac1_rgmii_rxin";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
gmac1_rmii_refin: gmac1-rmii-refin-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "gmac1_rmii_refin";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
i2srx_bclk_ext: i2srx-bclk-ext-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "i2srx_bclk_ext";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
i2srx_lrck_ext: i2srx-lrck-ext-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "i2srx_lrck_ext";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
i2stx_bclk_ext: i2stx-bclk-ext-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "i2stx_bclk_ext";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
i2stx_lrck_ext: i2stx-lrck-ext-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "i2stx_lrck_ext";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
mclk_ext: mclk-ext-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "mclk_ext";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
osc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "osc";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rtc_osc: rtc-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "rtc_osc";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
tdm_ext: tdm-ext-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "tdm_ext";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&plic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
clint: timer@2000000 {
|
||||
compatible = "starfive,jh7110-clint", "sifive,clint0";
|
||||
reg = <0x0 0x2000000 0x0 0x10000>;
|
||||
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
|
||||
<&cpu1_intc 3>, <&cpu1_intc 7>,
|
||||
<&cpu2_intc 3>, <&cpu2_intc 7>,
|
||||
<&cpu3_intc 3>, <&cpu3_intc 7>,
|
||||
<&cpu4_intc 3>, <&cpu4_intc 7>;
|
||||
};
|
||||
|
||||
ccache: cache-controller@2010000 {
|
||||
compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
|
||||
reg = <0x0 0x2010000 0x0 0x4000>;
|
||||
interrupts = <1>, <3>, <4>, <2>;
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-sets = <2048>;
|
||||
cache-size = <2097152>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
plic: interrupt-controller@c000000 {
|
||||
compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
|
||||
reg = <0x0 0xc000000 0x0 0x4000000>;
|
||||
interrupts-extended = <&cpu0_intc 11>,
|
||||
<&cpu1_intc 11>, <&cpu1_intc 9>,
|
||||
<&cpu2_intc 11>, <&cpu2_intc 9>,
|
||||
<&cpu3_intc 11>, <&cpu3_intc 9>,
|
||||
<&cpu4_intc 11>, <&cpu4_intc 9>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
riscv,ndev = <136>;
|
||||
};
|
||||
|
||||
uart0: serial@10000000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x10000000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
|
||||
<&syscrg JH7110_SYSCLK_UART0_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
resets = <&syscrg JH7110_SYSRST_UART0_APB>;
|
||||
interrupts = <32>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10010000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x10010000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
|
||||
<&syscrg JH7110_SYSCLK_UART1_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
resets = <&syscrg JH7110_SYSRST_UART1_APB>;
|
||||
interrupts = <33>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@10020000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x10020000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
|
||||
<&syscrg JH7110_SYSCLK_UART2_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
resets = <&syscrg JH7110_SYSRST_UART2_APB>;
|
||||
interrupts = <34>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@10030000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x10030000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
|
||||
clock-names = "ref";
|
||||
resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
|
||||
interrupts = <35>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@10040000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x10040000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
|
||||
clock-names = "ref";
|
||||
resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
|
||||
interrupts = <36>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@10050000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x10050000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
|
||||
clock-names = "ref";
|
||||
resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
|
||||
interrupts = <37>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@12000000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x12000000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
|
||||
<&syscrg JH7110_SYSCLK_UART3_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
resets = <&syscrg JH7110_SYSRST_UART3_APB>;
|
||||
interrupts = <45>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@12010000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x12010000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
|
||||
<&syscrg JH7110_SYSCLK_UART4_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
resets = <&syscrg JH7110_SYSRST_UART4_APB>;
|
||||
interrupts = <46>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@12020000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x12020000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
|
||||
<&syscrg JH7110_SYSCLK_UART5_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
resets = <&syscrg JH7110_SYSRST_UART5_APB>;
|
||||
interrupts = <47>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@12030000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x12030000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
|
||||
clock-names = "ref";
|
||||
resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
|
||||
interrupts = <48>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@12040000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x12040000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
|
||||
clock-names = "ref";
|
||||
resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
|
||||
interrupts = <49>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@12050000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x12050000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
|
||||
clock-names = "ref";
|
||||
resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
|
||||
interrupts = <50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@12060000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x12060000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
|
||||
clock-names = "ref";
|
||||
resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
|
||||
interrupts = <51>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscrg: clock-controller@13020000 {
|
||||
compatible = "starfive,jh7110-syscrg";
|
||||
reg = <0x0 0x13020000 0x0 0x10000>;
|
||||
clocks = <&osc>, <&gmac1_rmii_refin>,
|
||||
<&gmac1_rgmii_rxin>,
|
||||
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
|
||||
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
|
||||
<&tdm_ext>, <&mclk_ext>;
|
||||
clock-names = "osc", "gmac1_rmii_refin",
|
||||
"gmac1_rgmii_rxin",
|
||||
"i2stx_bclk_ext", "i2stx_lrck_ext",
|
||||
"i2srx_bclk_ext", "i2srx_lrck_ext",
|
||||
"tdm_ext", "mclk_ext";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
sysgpio: pinctrl@13040000 {
|
||||
compatible = "starfive,jh7110-sys-pinctrl";
|
||||
reg = <0x0 0x13040000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
|
||||
resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
|
||||
interrupts = <86>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
aoncrg: clock-controller@17000000 {
|
||||
compatible = "starfive,jh7110-aoncrg";
|
||||
reg = <0x0 0x17000000 0x0 0x10000>;
|
||||
clocks = <&osc>, <&gmac0_rmii_refin>,
|
||||
<&gmac0_rgmii_rxin>,
|
||||
<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
|
||||
<&syscrg JH7110_SYSCLK_APB_BUS>,
|
||||
<&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
|
||||
<&rtc_osc>;
|
||||
clock-names = "osc", "gmac0_rmii_refin",
|
||||
"gmac0_rgmii_rxin", "stg_axiahb",
|
||||
"apb_bus", "gmac0_gtxclk",
|
||||
"rtc_osc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
aongpio: pinctrl@17020000 {
|
||||
compatible = "starfive,jh7110-aon-pinctrl";
|
||||
reg = <0x0 0x17020000 0x0 0x10000>;
|
||||
resets = <&aoncrg JH7110_AONRST_IOMUX>;
|
||||
interrupts = <85>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
221
include/dt-bindings/clock/starfive,jh7110-crg.h
Normal file
221
include/dt-bindings/clock/starfive,jh7110-crg.h
Normal file
@ -0,0 +1,221 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
|
||||
/*
|
||||
* Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
|
||||
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
|
||||
|
||||
/* SYSCRG clocks */
|
||||
#define JH7110_SYSCLK_CPU_ROOT 0
|
||||
#define JH7110_SYSCLK_CPU_CORE 1
|
||||
#define JH7110_SYSCLK_CPU_BUS 2
|
||||
#define JH7110_SYSCLK_GPU_ROOT 3
|
||||
#define JH7110_SYSCLK_PERH_ROOT 4
|
||||
#define JH7110_SYSCLK_BUS_ROOT 5
|
||||
#define JH7110_SYSCLK_NOCSTG_BUS 6
|
||||
#define JH7110_SYSCLK_AXI_CFG0 7
|
||||
#define JH7110_SYSCLK_STG_AXIAHB 8
|
||||
#define JH7110_SYSCLK_AHB0 9
|
||||
#define JH7110_SYSCLK_AHB1 10
|
||||
#define JH7110_SYSCLK_APB_BUS 11
|
||||
#define JH7110_SYSCLK_APB0 12
|
||||
#define JH7110_SYSCLK_PLL0_DIV2 13
|
||||
#define JH7110_SYSCLK_PLL1_DIV2 14
|
||||
#define JH7110_SYSCLK_PLL2_DIV2 15
|
||||
#define JH7110_SYSCLK_AUDIO_ROOT 16
|
||||
#define JH7110_SYSCLK_MCLK_INNER 17
|
||||
#define JH7110_SYSCLK_MCLK 18
|
||||
#define JH7110_SYSCLK_MCLK_OUT 19
|
||||
#define JH7110_SYSCLK_ISP_2X 20
|
||||
#define JH7110_SYSCLK_ISP_AXI 21
|
||||
#define JH7110_SYSCLK_GCLK0 22
|
||||
#define JH7110_SYSCLK_GCLK1 23
|
||||
#define JH7110_SYSCLK_GCLK2 24
|
||||
#define JH7110_SYSCLK_CORE 25
|
||||
#define JH7110_SYSCLK_CORE1 26
|
||||
#define JH7110_SYSCLK_CORE2 27
|
||||
#define JH7110_SYSCLK_CORE3 28
|
||||
#define JH7110_SYSCLK_CORE4 29
|
||||
#define JH7110_SYSCLK_DEBUG 30
|
||||
#define JH7110_SYSCLK_RTC_TOGGLE 31
|
||||
#define JH7110_SYSCLK_TRACE0 32
|
||||
#define JH7110_SYSCLK_TRACE1 33
|
||||
#define JH7110_SYSCLK_TRACE2 34
|
||||
#define JH7110_SYSCLK_TRACE3 35
|
||||
#define JH7110_SYSCLK_TRACE4 36
|
||||
#define JH7110_SYSCLK_TRACE_COM 37
|
||||
#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
|
||||
#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
|
||||
#define JH7110_SYSCLK_OSC_DIV2 40
|
||||
#define JH7110_SYSCLK_PLL1_DIV4 41
|
||||
#define JH7110_SYSCLK_PLL1_DIV8 42
|
||||
#define JH7110_SYSCLK_DDR_BUS 43
|
||||
#define JH7110_SYSCLK_DDR_AXI 44
|
||||
#define JH7110_SYSCLK_GPU_CORE 45
|
||||
#define JH7110_SYSCLK_GPU_CORE_CLK 46
|
||||
#define JH7110_SYSCLK_GPU_SYS_CLK 47
|
||||
#define JH7110_SYSCLK_GPU_APB 48
|
||||
#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
|
||||
#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
|
||||
#define JH7110_SYSCLK_ISP_TOP_CORE 51
|
||||
#define JH7110_SYSCLK_ISP_TOP_AXI 52
|
||||
#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
|
||||
#define JH7110_SYSCLK_HIFI4_CORE 54
|
||||
#define JH7110_SYSCLK_HIFI4_AXI 55
|
||||
#define JH7110_SYSCLK_AXI_CFG1_MAIN 56
|
||||
#define JH7110_SYSCLK_AXI_CFG1_AHB 57
|
||||
#define JH7110_SYSCLK_VOUT_SRC 58
|
||||
#define JH7110_SYSCLK_VOUT_AXI 59
|
||||
#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
|
||||
#define JH7110_SYSCLK_VOUT_TOP_AHB 61
|
||||
#define JH7110_SYSCLK_VOUT_TOP_AXI 62
|
||||
#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63
|
||||
#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64
|
||||
#define JH7110_SYSCLK_JPEGC_AXI 65
|
||||
#define JH7110_SYSCLK_CODAJ12_AXI 66
|
||||
#define JH7110_SYSCLK_CODAJ12_CORE 67
|
||||
#define JH7110_SYSCLK_CODAJ12_APB 68
|
||||
#define JH7110_SYSCLK_VDEC_AXI 69
|
||||
#define JH7110_SYSCLK_WAVE511_AXI 70
|
||||
#define JH7110_SYSCLK_WAVE511_BPU 71
|
||||
#define JH7110_SYSCLK_WAVE511_VCE 72
|
||||
#define JH7110_SYSCLK_WAVE511_APB 73
|
||||
#define JH7110_SYSCLK_VDEC_JPG 74
|
||||
#define JH7110_SYSCLK_VDEC_MAIN 75
|
||||
#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
|
||||
#define JH7110_SYSCLK_VENC_AXI 77
|
||||
#define JH7110_SYSCLK_WAVE420L_AXI 78
|
||||
#define JH7110_SYSCLK_WAVE420L_BPU 79
|
||||
#define JH7110_SYSCLK_WAVE420L_VCE 80
|
||||
#define JH7110_SYSCLK_WAVE420L_APB 81
|
||||
#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
|
||||
#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83
|
||||
#define JH7110_SYSCLK_AXI_CFG0_MAIN 84
|
||||
#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85
|
||||
#define JH7110_SYSCLK_AXIMEM2_AXI 86
|
||||
#define JH7110_SYSCLK_QSPI_AHB 87
|
||||
#define JH7110_SYSCLK_QSPI_APB 88
|
||||
#define JH7110_SYSCLK_QSPI_REF_SRC 89
|
||||
#define JH7110_SYSCLK_QSPI_REF 90
|
||||
#define JH7110_SYSCLK_SDIO0_AHB 91
|
||||
#define JH7110_SYSCLK_SDIO1_AHB 92
|
||||
#define JH7110_SYSCLK_SDIO0_SDCARD 93
|
||||
#define JH7110_SYSCLK_SDIO1_SDCARD 94
|
||||
#define JH7110_SYSCLK_USB_125M 95
|
||||
#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
|
||||
#define JH7110_SYSCLK_GMAC1_AHB 97
|
||||
#define JH7110_SYSCLK_GMAC1_AXI 98
|
||||
#define JH7110_SYSCLK_GMAC_SRC 99
|
||||
#define JH7110_SYSCLK_GMAC1_GTXCLK 100
|
||||
#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
|
||||
#define JH7110_SYSCLK_GMAC1_PTP 102
|
||||
#define JH7110_SYSCLK_GMAC1_RX 103
|
||||
#define JH7110_SYSCLK_GMAC1_RX_INV 104
|
||||
#define JH7110_SYSCLK_GMAC1_TX 105
|
||||
#define JH7110_SYSCLK_GMAC1_TX_INV 106
|
||||
#define JH7110_SYSCLK_GMAC1_GTXC 107
|
||||
#define JH7110_SYSCLK_GMAC0_GTXCLK 108
|
||||
#define JH7110_SYSCLK_GMAC0_PTP 109
|
||||
#define JH7110_SYSCLK_GMAC_PHY 110
|
||||
#define JH7110_SYSCLK_GMAC0_GTXC 111
|
||||
#define JH7110_SYSCLK_IOMUX_APB 112
|
||||
#define JH7110_SYSCLK_MAILBOX_APB 113
|
||||
#define JH7110_SYSCLK_INT_CTRL_APB 114
|
||||
#define JH7110_SYSCLK_CAN0_APB 115
|
||||
#define JH7110_SYSCLK_CAN0_TIMER 116
|
||||
#define JH7110_SYSCLK_CAN0_CAN 117
|
||||
#define JH7110_SYSCLK_CAN1_APB 118
|
||||
#define JH7110_SYSCLK_CAN1_TIMER 119
|
||||
#define JH7110_SYSCLK_CAN1_CAN 120
|
||||
#define JH7110_SYSCLK_PWM_APB 121
|
||||
#define JH7110_SYSCLK_WDT_APB 122
|
||||
#define JH7110_SYSCLK_WDT_CORE 123
|
||||
#define JH7110_SYSCLK_TIMER_APB 124
|
||||
#define JH7110_SYSCLK_TIMER0 125
|
||||
#define JH7110_SYSCLK_TIMER1 126
|
||||
#define JH7110_SYSCLK_TIMER2 127
|
||||
#define JH7110_SYSCLK_TIMER3 128
|
||||
#define JH7110_SYSCLK_TEMP_APB 129
|
||||
#define JH7110_SYSCLK_TEMP_CORE 130
|
||||
#define JH7110_SYSCLK_SPI0_APB 131
|
||||
#define JH7110_SYSCLK_SPI1_APB 132
|
||||
#define JH7110_SYSCLK_SPI2_APB 133
|
||||
#define JH7110_SYSCLK_SPI3_APB 134
|
||||
#define JH7110_SYSCLK_SPI4_APB 135
|
||||
#define JH7110_SYSCLK_SPI5_APB 136
|
||||
#define JH7110_SYSCLK_SPI6_APB 137
|
||||
#define JH7110_SYSCLK_I2C0_APB 138
|
||||
#define JH7110_SYSCLK_I2C1_APB 139
|
||||
#define JH7110_SYSCLK_I2C2_APB 140
|
||||
#define JH7110_SYSCLK_I2C3_APB 141
|
||||
#define JH7110_SYSCLK_I2C4_APB 142
|
||||
#define JH7110_SYSCLK_I2C5_APB 143
|
||||
#define JH7110_SYSCLK_I2C6_APB 144
|
||||
#define JH7110_SYSCLK_UART0_APB 145
|
||||
#define JH7110_SYSCLK_UART0_CORE 146
|
||||
#define JH7110_SYSCLK_UART1_APB 147
|
||||
#define JH7110_SYSCLK_UART1_CORE 148
|
||||
#define JH7110_SYSCLK_UART2_APB 149
|
||||
#define JH7110_SYSCLK_UART2_CORE 150
|
||||
#define JH7110_SYSCLK_UART3_APB 151
|
||||
#define JH7110_SYSCLK_UART3_CORE 152
|
||||
#define JH7110_SYSCLK_UART4_APB 153
|
||||
#define JH7110_SYSCLK_UART4_CORE 154
|
||||
#define JH7110_SYSCLK_UART5_APB 155
|
||||
#define JH7110_SYSCLK_UART5_CORE 156
|
||||
#define JH7110_SYSCLK_PWMDAC_APB 157
|
||||
#define JH7110_SYSCLK_PWMDAC_CORE 158
|
||||
#define JH7110_SYSCLK_SPDIF_APB 159
|
||||
#define JH7110_SYSCLK_SPDIF_CORE 160
|
||||
#define JH7110_SYSCLK_I2STX0_APB 161
|
||||
#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
|
||||
#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163
|
||||
#define JH7110_SYSCLK_I2STX0_LRCK_MST 164
|
||||
#define JH7110_SYSCLK_I2STX0_BCLK 165
|
||||
#define JH7110_SYSCLK_I2STX0_BCLK_INV 166
|
||||
#define JH7110_SYSCLK_I2STX0_LRCK 167
|
||||
#define JH7110_SYSCLK_I2STX1_APB 168
|
||||
#define JH7110_SYSCLK_I2STX1_BCLK_MST 169
|
||||
#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170
|
||||
#define JH7110_SYSCLK_I2STX1_LRCK_MST 171
|
||||
#define JH7110_SYSCLK_I2STX1_BCLK 172
|
||||
#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
|
||||
#define JH7110_SYSCLK_I2STX1_LRCK 174
|
||||
#define JH7110_SYSCLK_I2SRX_APB 175
|
||||
#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
|
||||
#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
|
||||
#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
|
||||
#define JH7110_SYSCLK_I2SRX_BCLK 179
|
||||
#define JH7110_SYSCLK_I2SRX_BCLK_INV 180
|
||||
#define JH7110_SYSCLK_I2SRX_LRCK 181
|
||||
#define JH7110_SYSCLK_PDM_DMIC 182
|
||||
#define JH7110_SYSCLK_PDM_APB 183
|
||||
#define JH7110_SYSCLK_TDM_AHB 184
|
||||
#define JH7110_SYSCLK_TDM_APB 185
|
||||
#define JH7110_SYSCLK_TDM_INTERNAL 186
|
||||
#define JH7110_SYSCLK_TDM_TDM 187
|
||||
#define JH7110_SYSCLK_TDM_TDM_INV 188
|
||||
#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
|
||||
|
||||
#define JH7110_SYSCLK_END 190
|
||||
|
||||
/* AONCRG clocks */
|
||||
#define JH7110_AONCLK_OSC_DIV4 0
|
||||
#define JH7110_AONCLK_APB_FUNC 1
|
||||
#define JH7110_AONCLK_GMAC0_AHB 2
|
||||
#define JH7110_AONCLK_GMAC0_AXI 3
|
||||
#define JH7110_AONCLK_GMAC0_RMII_RTX 4
|
||||
#define JH7110_AONCLK_GMAC0_TX 5
|
||||
#define JH7110_AONCLK_GMAC0_TX_INV 6
|
||||
#define JH7110_AONCLK_GMAC0_RX 7
|
||||
#define JH7110_AONCLK_GMAC0_RX_INV 8
|
||||
#define JH7110_AONCLK_OTPC_APB 9
|
||||
#define JH7110_AONCLK_RTC_APB 10
|
||||
#define JH7110_AONCLK_RTC_INTERNAL 11
|
||||
#define JH7110_AONCLK_RTC_32K 12
|
||||
#define JH7110_AONCLK_RTC_CAL 13
|
||||
|
||||
#define JH7110_AONCLK_END 14
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
|
||||
154
include/dt-bindings/reset/starfive,jh7110-crg.h
Normal file
154
include/dt-bindings/reset/starfive,jh7110-crg.h
Normal file
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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*/
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#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
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#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
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/* SYSCRG resets */
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#define JH7110_SYSRST_JTAG_APB 0
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#define JH7110_SYSRST_SYSCON_APB 1
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#define JH7110_SYSRST_IOMUX_APB 2
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#define JH7110_SYSRST_BUS 3
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#define JH7110_SYSRST_DEBUG 4
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#define JH7110_SYSRST_CORE0 5
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#define JH7110_SYSRST_CORE1 6
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#define JH7110_SYSRST_CORE2 7
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#define JH7110_SYSRST_CORE3 8
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#define JH7110_SYSRST_CORE4 9
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#define JH7110_SYSRST_CORE0_ST 10
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#define JH7110_SYSRST_CORE1_ST 11
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#define JH7110_SYSRST_CORE2_ST 12
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#define JH7110_SYSRST_CORE3_ST 13
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#define JH7110_SYSRST_CORE4_ST 14
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#define JH7110_SYSRST_TRACE0 15
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#define JH7110_SYSRST_TRACE1 16
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#define JH7110_SYSRST_TRACE2 17
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#define JH7110_SYSRST_TRACE3 18
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#define JH7110_SYSRST_TRACE4 19
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#define JH7110_SYSRST_TRACE_COM 20
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#define JH7110_SYSRST_GPU_APB 21
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#define JH7110_SYSRST_GPU_DOMA 22
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#define JH7110_SYSRST_NOC_BUS_APB 23
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#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
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#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
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#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
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#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
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#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
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#define JH7110_SYSRST_NOC_BUS_DDRC 29
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#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
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#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
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#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
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#define JH7110_SYSRST_AXI_CFG1_AHB 33
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#define JH7110_SYSRST_AXI_CFG1_MAIN 34
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#define JH7110_SYSRST_AXI_CFG0_MAIN 35
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#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36
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#define JH7110_SYSRST_AXI_CFG0_HIFI4 37
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#define JH7110_SYSRST_DDR_AXI 38
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#define JH7110_SYSRST_DDR_OSC 39
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#define JH7110_SYSRST_DDR_APB 40
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#define JH7110_SYSRST_ISP_TOP 41
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#define JH7110_SYSRST_ISP_TOP_AXI 42
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#define JH7110_SYSRST_VOUT_TOP_SRC 43
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#define JH7110_SYSRST_CODAJ12_AXI 44
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#define JH7110_SYSRST_CODAJ12_CORE 45
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#define JH7110_SYSRST_CODAJ12_APB 46
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#define JH7110_SYSRST_WAVE511_AXI 47
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#define JH7110_SYSRST_WAVE511_BPU 48
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#define JH7110_SYSRST_WAVE511_VCE 49
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#define JH7110_SYSRST_WAVE511_APB 50
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#define JH7110_SYSRST_VDEC_JPG 51
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#define JH7110_SYSRST_VDEC_MAIN 52
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#define JH7110_SYSRST_AXIMEM0_AXI 53
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#define JH7110_SYSRST_WAVE420L_AXI 54
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#define JH7110_SYSRST_WAVE420L_BPU 55
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#define JH7110_SYSRST_WAVE420L_VCE 56
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#define JH7110_SYSRST_WAVE420L_APB 57
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#define JH7110_SYSRST_AXIMEM1_AXI 58
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#define JH7110_SYSRST_AXIMEM2_AXI 59
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#define JH7110_SYSRST_INTMEM 60
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#define JH7110_SYSRST_QSPI_AHB 61
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#define JH7110_SYSRST_QSPI_APB 62
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#define JH7110_SYSRST_QSPI_REF 63
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#define JH7110_SYSRST_SDIO0_AHB 64
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#define JH7110_SYSRST_SDIO1_AHB 65
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#define JH7110_SYSRST_GMAC1_AXI 66
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#define JH7110_SYSRST_GMAC1_AHB 67
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#define JH7110_SYSRST_MAILBOX_APB 68
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#define JH7110_SYSRST_SPI0_APB 69
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#define JH7110_SYSRST_SPI1_APB 70
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#define JH7110_SYSRST_SPI2_APB 71
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#define JH7110_SYSRST_SPI3_APB 72
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#define JH7110_SYSRST_SPI4_APB 73
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#define JH7110_SYSRST_SPI5_APB 74
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#define JH7110_SYSRST_SPI6_APB 75
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#define JH7110_SYSRST_I2C0_APB 76
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#define JH7110_SYSRST_I2C1_APB 77
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#define JH7110_SYSRST_I2C2_APB 78
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#define JH7110_SYSRST_I2C3_APB 79
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#define JH7110_SYSRST_I2C4_APB 80
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#define JH7110_SYSRST_I2C5_APB 81
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#define JH7110_SYSRST_I2C6_APB 82
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#define JH7110_SYSRST_UART0_APB 83
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#define JH7110_SYSRST_UART0_CORE 84
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#define JH7110_SYSRST_UART1_APB 85
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#define JH7110_SYSRST_UART1_CORE 86
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#define JH7110_SYSRST_UART2_APB 87
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#define JH7110_SYSRST_UART2_CORE 88
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#define JH7110_SYSRST_UART3_APB 89
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#define JH7110_SYSRST_UART3_CORE 90
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#define JH7110_SYSRST_UART4_APB 91
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#define JH7110_SYSRST_UART4_CORE 92
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#define JH7110_SYSRST_UART5_APB 93
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#define JH7110_SYSRST_UART5_CORE 94
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#define JH7110_SYSRST_SPDIF_APB 95
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#define JH7110_SYSRST_PWMDAC_APB 96
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#define JH7110_SYSRST_PDM_DMIC 97
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#define JH7110_SYSRST_PDM_APB 98
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#define JH7110_SYSRST_I2SRX_APB 99
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#define JH7110_SYSRST_I2SRX_BCLK 100
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#define JH7110_SYSRST_I2STX0_APB 101
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#define JH7110_SYSRST_I2STX0_BCLK 102
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#define JH7110_SYSRST_I2STX1_APB 103
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#define JH7110_SYSRST_I2STX1_BCLK 104
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#define JH7110_SYSRST_TDM_AHB 105
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#define JH7110_SYSRST_TDM_CORE 106
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#define JH7110_SYSRST_TDM_APB 107
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#define JH7110_SYSRST_PWM_APB 108
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#define JH7110_SYSRST_WDT_APB 109
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#define JH7110_SYSRST_WDT_CORE 110
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#define JH7110_SYSRST_CAN0_APB 111
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#define JH7110_SYSRST_CAN0_CORE 112
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#define JH7110_SYSRST_CAN0_TIMER 113
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#define JH7110_SYSRST_CAN1_APB 114
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#define JH7110_SYSRST_CAN1_CORE 115
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#define JH7110_SYSRST_CAN1_TIMER 116
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#define JH7110_SYSRST_TIMER_APB 117
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#define JH7110_SYSRST_TIMER0 118
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#define JH7110_SYSRST_TIMER1 119
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#define JH7110_SYSRST_TIMER2 120
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#define JH7110_SYSRST_TIMER3 121
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#define JH7110_SYSRST_INT_CTRL_APB 122
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#define JH7110_SYSRST_TEMP_APB 123
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#define JH7110_SYSRST_TEMP_CORE 124
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#define JH7110_SYSRST_JTAG_CERTIFICATION 125
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#define JH7110_SYSRST_END 126
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/* AONCRG resets */
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#define JH7110_AONRST_GMAC0_AXI 0
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#define JH7110_AONRST_GMAC0_AHB 1
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#define JH7110_AONRST_IOMUX 2
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#define JH7110_AONRST_PMU_APB 3
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#define JH7110_AONRST_PMU_WKUP 4
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#define JH7110_AONRST_RTC_APB 5
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#define JH7110_AONRST_RTC_CAL 6
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#define JH7110_AONRST_RTC_32K 7
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#define JH7110_AONRST_END 8
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#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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