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drm/vc4: Move the DSI clock divider workaround closer to the clock call.

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We want the adjusted_mode->clock to be the actual clock we're
expecting to program, so that consumers see the right values for clock
and vrefresh.

Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20170815234722.20700-1-eric@anholt.net
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Eric Anholt 2017-08-15 16:47:18 -07:00
parent 4b947b1c5a
commit d409eeafa9
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/drm/vc4/vc4_dsi.c
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@ -859,11 +859,7 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
pll_clock = parent_rate / divider; pll_clock = parent_rate / divider;
pixel_clock_hz = pll_clock / dsi->divider; pixel_clock_hz = pll_clock / dsi->divider;
/* Round up the clk_set_rate() request slightly, since adjusted_mode->clock = pixel_clock_hz / 1000;
* PLLD_DSI1 is an integer divider and its rate selection will
* never round up.
*/
adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
/* Given the new pixel clock, adjust HFP to keep vrefresh the same. */ /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
@ -901,7 +897,11 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
vc4_dsi_dump_regs(dsi); vc4_dsi_dump_regs(dsi);
} }
phy_clock = pixel_clock_hz * dsi->divider; /* Round up the clk_set_rate() request slightly, since
* PLLD_DSI1 is an integer divider and its rate selection will
* never round up.
*/
phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
if (ret) { if (ret) {
dev_err(&dsi->pdev->dev, dev_err(&dsi->pdev->dev,