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Minimal omap SoC changes for v4.4 merge window. As we've spent quite a

Browse Source 
bit of time sorting out regressions for v4.3 and are very late with
 these, I've kept the changes down to minimum:
 
 - A series of timer changes from Felipe Balbi to get us closer to
   moving the remaining timer code into drivers
 
 - A series of hwmod clean-up changes queued by Paul Walmsley
 
 - SoC detection clean-up to use soc_is instead of cpu_is as CPU is
   within the SoC and is confusing naming. The rest we can now change
   along with the other clean-up
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Merge tag 'omap-for-v4.4/soc-clean-up' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup

Minimal omap SoC changes for v4.4 merge window. As we've spent quite a
bit of time sorting out regressions for v4.3 and are very late with
these, I've kept the changes down to minimum:

- A series of timer changes from Felipe Balbi to get us closer to
  moving the remaining timer code into drivers

- A series of hwmod clean-up changes queued by Paul Walmsley

- SoC detection clean-up to use soc_is instead of cpu_is as CPU is
  within the SoC and is confusing naming. The rest we can now change
  along with the other clean-up

* tag 'omap-for-v4.4/soc-clean-up' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
  ARM: OMAP3: hwmod data: Remove legacy mailbox data and addrs
  ARM: DRA7: hwmod data: Remove spinlock hwmod addrs
  ARM: OMAP4: hwmod data: Remove spinlock hwmod addrs
  ARM: DRA7/AM335x/AM437x: hwmod: Remove gpmc address space from hwmod data
  arm: omap2: board-generic: use omap4_local_timer_init for AM437x
  ARM: DRA7/AM335x/AM437x: hwmod: Remove elm address space from hwmod data
  ARM: OMAP: Remove duplicated operand in OR operation
  clocksource: ti-32k: make it depend on GENERIC_CLOCKSOURCE
  ARM: OMAP: Change all cpu_is_* occurences to soc_is_* for id.c
  ARM: OMAP2+: Rename cpu_is macros to soc_is
  arm: omap2: timer: limit hwmod usage to non-DT boots
  arm: omap2+: select 32k clocksource driver
  clocksource: add TI 32.768 Hz counter driver
  arm: omap2: timer: rename omap_sync32k_timer_init()
  arm: omap2: timer: always call clocksource_of_init() when DT
  arm: omap2: timer: move realtime_counter_init() around
  arm: omap2: timer: provide generic sync32k_timer_init function
  arm: omap2: timer: remove __omap_gptimer_init()
  arm: omap2: timer: add a gptimer argument to sync32k_timer_init()
  arm: omap2: timer: get rid of obfuscating macros
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2015-10-26 14:35:41 +09:00
commit d3dc3df633
16 changed files with 339 additions and 295 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-omap2/Kconfig
View File

@ -96,6 +96,7 @@ config ARCH_OMAP2PLUS
select SOC_BUS
select TI_PRIV_EDMA
select OMAP_IRQCHIP
select CLKSRC_TI_32K
help
Systems based on OMAP2, OMAP3, OMAP4 or OMAP5

12
arch/arm/mach-omap2/board-generic.c
View File

@ -46,7 +46,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_machine = omap_generic_init,
.init_time = omap2_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = omap242x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
@ -63,7 +63,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_machine = omap_generic_init,
.init_time = omap2_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = omap243x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
@ -82,7 +82,7 @@ DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = n900_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@ -100,7 +100,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = omap3_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@ -116,7 +116,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
.init_early = omap3630_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = omap36xx_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@ -272,7 +272,7 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
.init_late = am43xx_init_late,
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
.init_time = omap3_gptimer_timer_init,
.init_time = omap4_local_timer_init,
.dt_compat = am43_boards_compat,
.restart = omap44xx_restart,
MACHINE_END

2
arch/arm/mach-omap2/board-ldp.c
View File

@ -424,6 +424,6 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
.init_irq = omap3_init_irq,
.init_machine = omap_ldp_init,
.init_late = omap3430_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.restart = omap3xxx_restart,
MACHINE_END

2
arch/arm/mach-omap2/board-rx51.c
View File

@ -136,6 +136,6 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
.init_irq = omap3_init_irq,
.init_machine = rx51_init,
.init_late = omap3430_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.restart = omap3xxx_restart,
MACHINE_END

3
arch/arm/mach-omap2/common.h
View File

@ -88,8 +88,7 @@ static inline int omap_mux_late_init(void)
extern void omap2_init_common_infrastructure(void);
extern void omap2_sync32k_timer_init(void);
extern void omap3_sync32k_timer_init(void);
extern void omap_init_time(void);
extern void omap3_secure_sync32k_timer_init(void);
extern void omap3_gptimer_timer_init(void);
extern void omap4_local_timer_init(void);

30
arch/arm/mach-omap2/id.c
View File

@ -57,15 +57,15 @@ int omap_type(void)
if (val < OMAP2_DEVICETYPE_MASK)
return val;
if (cpu_is_omap24xx()) {
if (soc_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
} else if (cpu_is_ti81xx()) {
} else if (soc_is_ti81xx()) {
val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
} else if (soc_is_am33xx() || soc_is_am43xx()) {
val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
} else if (cpu_is_omap34xx()) {
} else if (soc_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
} else if (soc_is_omap44xx()) {
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
@ -122,7 +122,7 @@ static u16 tap_prod_id;
void omap_get_die_id(struct omap_die_id *odi)
{
if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
@ -218,17 +218,17 @@ static void __init omap3_cpuinfo(void)
* on available features. Upon detection, update the CPU id
* and CPU class bits.
*/
if (cpu_is_omap3630()) {
if (soc_is_omap3630()) {
cpu_name = "OMAP3630";
} else if (soc_is_am35xx()) {
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
} else if (cpu_is_ti816x()) {
} else if (soc_is_ti816x()) {
cpu_name = "TI816X";
} else if (soc_is_am335x()) {
cpu_name = "AM335X";
} else if (soc_is_am437x()) {
cpu_name = "AM437x";
} else if (cpu_is_ti814x()) {
} else if (soc_is_ti814x()) {
cpu_name = "TI814X";
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
@ -275,11 +275,11 @@ void __init omap3xxx_check_features(void)
OMAP3_CHECK_FEATURE(status, SGX);
OMAP3_CHECK_FEATURE(status, NEON);
OMAP3_CHECK_FEATURE(status, ISP);
if (cpu_is_omap3630())
if (soc_is_omap3630())
omap_features |= OMAP3_HAS_192MHZ_CLK;
if (cpu_is_omap3430() || cpu_is_omap3630())
if (soc_is_omap3430() || soc_is_omap3630())
omap_features |= OMAP3_HAS_IO_WAKEUP;
if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
omap_rev() == OMAP3430_REV_ES3_1_2)
omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
@ -701,7 +701,7 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
tap_base = tap;
/* XXX What is this intended to do? */
if (cpu_is_omap34xx())
if (soc_is_omap34xx())
tap_prod_id = 0x0210;
else
tap_prod_id = 0x0208;
@ -719,11 +719,11 @@ static const char * const omap_types[] = {
static const char * __init omap_get_family(void)
{
if (cpu_is_omap24xx())
if (soc_is_omap24xx())
return kasprintf(GFP_KERNEL, "OMAP2");
else if (cpu_is_omap34xx())
else if (soc_is_omap34xx())
return kasprintf(GFP_KERNEL, "OMAP3");
else if (cpu_is_omap44xx())
else if (soc_is_omap44xx())
return kasprintf(GFP_KERNEL, "OMAP4");
else if (soc_is_omap54xx())
return kasprintf(GFP_KERNEL, "OMAP5");

20
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View File

@ -152,20 +152,10 @@ struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
{
.pa_start = 0x48080000,
.pa_end = 0x48080000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_elm_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_elm_addr_space,
.user = OCP_USER_MPU,
};
@ -285,20 +275,10 @@ struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
};
/* l3s cfg -> gpmc */
static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
{
.pa_start = 0x50000000,
.pa_end = 0x50000000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_gpmc_hwmod,
.clk = "l3s_gclk",
.addr = am33xx_gpmc_addr_space,
.user = OCP_USER_MPU,
};

29
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -26,7 +26,6 @@
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/iommu-omap.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/dmtimer.h>
#include "soc.h"
@ -1506,26 +1505,9 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
.sysc = &omap3xxx_mailbox_sysc,
};
static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
{ .name = "dsp", .tx_id = 0, .rx_id = 1 },
};
static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
.num_users = 2,
.num_fifos = 2,
.info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info),
.info = omap3xxx_mailbox_info,
};
static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
{ .irq = 26 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_mailbox_hwmod = {
.name = "mailbox",
.class = &omap3xxx_mailbox_hwmod_class,
.mpu_irqs = omap3xxx_mailbox_irqs,
.main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
@ -1536,7 +1518,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
},
},
.dev_attr = &omap3xxx_mailbox_attrs,
};
/*
@ -3276,20 +3257,10 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
{
.pa_start = 0x48094000,
.pa_end = 0x480941ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mailbox_hwmod,
.addr = omap3xxx_mailbox_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

10
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -4471,21 +4471,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
{
.pa_start = 0x4a0f6000,
.pa_end = 0x4a0f6fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> spinlock */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_spinlock_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_spinlock_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

3
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View File

@ -1844,8 +1844,7 @@ static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_RESET_STATUS),
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),

30
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -2566,21 +2566,11 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
{
.pa_start = 0x48078000,
.pa_end = 0x48078fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per1 -> elm */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_elm_hwmod,
.clk = "l3_iclk_div",
.addr = dra7xx_elm_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@ -2648,21 +2638,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
{
.pa_start = 0x50000000,
.pa_end = 0x500003ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l3_main_1 -> gpmc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_gpmc_hwmod,
.clk = "l3_iclk_div",
.addr = dra7xx_gpmc_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@ -3029,21 +3009,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
{
.pa_start = 0x4a0f6000,
.pa_end = 0x4a0f6fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> spinlock */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_spinlock_hwmod,
.clk = "l3_iclk_div",
.addr = dra7xx_spinlock_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

195
arch/arm/mach-omap2/soc.h
View File

@ -129,9 +129,9 @@ int omap_type(void);
/*
* omap_rev bits:
* CPU id bits (0730, 1510, 1710, 2422...) [31:16]
* CPU revision (See _REV_ defined in cpu.h) [15:08]
* CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
* SoC id bits (0730, 1510, 1710, 2422...) [31:16]
* SoC revision (See _REV_ defined in cpu.h) [15:08]
* SoC class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
*/
unsigned int omap_rev(void);
@ -141,20 +141,20 @@ static inline int soc_is_omap(void)
}
/*
* Get the CPU revision for OMAP devices
* Get the SoC revision for OMAP devices
*/
#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
/*
* Macros to group OMAP into cpu classes.
* These can be used in most places.
* cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
* cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
* cpu_is_omap243x(): True for OMAP2430
* cpu_is_omap343x(): True for OMAP3430
* cpu_is_omap443x(): True for OMAP4430
* cpu_is_omap446x(): True for OMAP4460
* cpu_is_omap447x(): True for OMAP4470
* soc_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
* soc_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
* soc_is_omap243x(): True for OMAP2430
* soc_is_omap343x(): True for OMAP3430
* soc_is_omap443x(): True for OMAP4430
* soc_is_omap446x(): True for OMAP4460
* soc_is_omap447x(): True for OMAP4470
* soc_is_omap543x(): True for OMAP5430, OMAP5432
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
@ -225,23 +225,23 @@ IS_TI_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
IS_AM_SUBCLASS(437x, 0x437)
#define cpu_is_omap24xx() 0
#define cpu_is_omap242x() 0
#define cpu_is_omap243x() 0
#define cpu_is_omap34xx() 0
#define cpu_is_omap343x() 0
#define cpu_is_ti81xx() 0
#define cpu_is_ti816x() 0
#define cpu_is_ti814x() 0
#define soc_is_omap24xx() 0
#define soc_is_omap242x() 0
#define soc_is_omap243x() 0
#define soc_is_omap34xx() 0
#define soc_is_omap343x() 0
#define soc_is_ti81xx() 0
#define soc_is_ti816x() 0
#define soc_is_ti814x() 0
#define soc_is_am35xx() 0
#define soc_is_am33xx() 0
#define soc_is_am335x() 0
#define soc_is_am43xx() 0
#define soc_is_am437x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
#define cpu_is_omap446x() 0
#define cpu_is_omap447x() 0
#define soc_is_omap44xx() 0
#define soc_is_omap443x() 0
#define soc_is_omap446x() 0
#define soc_is_omap447x() 0
#define soc_is_omap54xx() 0
#define soc_is_omap543x() 0
#define soc_is_dra7xx() 0
@ -250,54 +250,54 @@ IS_AM_SUBCLASS(437x, 0x437)
#if defined(MULTI_OMAP2)
# if defined(CONFIG_ARCH_OMAP2)
# undef cpu_is_omap24xx
# define cpu_is_omap24xx() is_omap24xx()
# undef soc_is_omap24xx
# define soc_is_omap24xx() is_omap24xx()
# endif
# if defined (CONFIG_SOC_OMAP2420)
# undef cpu_is_omap242x
# define cpu_is_omap242x() is_omap242x()
# undef soc_is_omap242x
# define soc_is_omap242x() is_omap242x()
# endif
# if defined (CONFIG_SOC_OMAP2430)
# undef cpu_is_omap243x
# define cpu_is_omap243x() is_omap243x()
# undef soc_is_omap243x
# define soc_is_omap243x() is_omap243x()
# endif
# if defined(CONFIG_ARCH_OMAP3)
# undef cpu_is_omap34xx
# undef cpu_is_omap343x
# define cpu_is_omap34xx() is_omap34xx()
# define cpu_is_omap343x() is_omap343x()
# undef soc_is_omap34xx
# undef soc_is_omap343x
# define soc_is_omap34xx() is_omap34xx()
# define soc_is_omap343x() is_omap343x()
# endif
#else
# if defined(CONFIG_ARCH_OMAP2)
# undef cpu_is_omap24xx
# define cpu_is_omap24xx() 1
# undef soc_is_omap24xx
# define soc_is_omap24xx() 1
# endif
# if defined(CONFIG_SOC_OMAP2420)
# undef cpu_is_omap242x
# define cpu_is_omap242x() 1
# undef soc_is_omap242x
# define soc_is_omap242x() 1
# endif
# if defined(CONFIG_SOC_OMAP2430)
# undef cpu_is_omap243x
# define cpu_is_omap243x() 1
# undef soc_is_omap243x
# define soc_is_omap243x() 1
# endif
# if defined(CONFIG_ARCH_OMAP3)
# undef cpu_is_omap34xx
# define cpu_is_omap34xx() 1
# undef soc_is_omap34xx
# define soc_is_omap34xx() 1
# endif
# if defined(CONFIG_SOC_OMAP3430)
# undef cpu_is_omap343x
# define cpu_is_omap343x() 1
# undef soc_is_omap343x
# define soc_is_omap343x() 1
# endif
#endif
/*
* Macros to detect individual cpu types.
* These are only rarely needed.
* cpu_is_omap2420(): True for OMAP2420
* cpu_is_omap2422(): True for OMAP2422
* cpu_is_omap2423(): True for OMAP2423
* cpu_is_omap2430(): True for OMAP2430
* cpu_is_omap3430(): True for OMAP3430
* soc_is_omap2420(): True for OMAP2420
* soc_is_omap2422(): True for OMAP2422
* soc_is_omap2423(): True for OMAP2423
* soc_is_omap2430(): True for OMAP2430
* soc_is_omap3430(): True for OMAP3430
*/
#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
@ -313,51 +313,51 @@ IS_OMAP_TYPE(2423, 0x2423)
IS_OMAP_TYPE(2430, 0x2430)
IS_OMAP_TYPE(3430, 0x3430)
#define cpu_is_omap2420() 0
#define cpu_is_omap2422() 0
#define cpu_is_omap2423() 0
#define cpu_is_omap2430() 0
#define cpu_is_omap3430() 0
#define cpu_is_omap3630() 0
#define soc_is_omap2420() 0
#define soc_is_omap2422() 0
#define soc_is_omap2423() 0
#define soc_is_omap2430() 0
#define soc_is_omap3430() 0
#define soc_is_omap3630() 0
#define soc_is_omap5430() 0
/* These are needed for the common code */
#ifdef CONFIG_ARCH_OMAP2PLUS
#define cpu_is_omap7xx() 0
#define cpu_is_omap15xx() 0
#define cpu_is_omap16xx() 0
#define cpu_is_omap1510() 0
#define cpu_is_omap1610() 0
#define cpu_is_omap1611() 0
#define cpu_is_omap1621() 0
#define cpu_is_omap1710() 0
#define soc_is_omap7xx() 0
#define soc_is_omap15xx() 0
#define soc_is_omap16xx() 0
#define soc_is_omap1510() 0
#define soc_is_omap1610() 0
#define soc_is_omap1611() 0
#define soc_is_omap1621() 0
#define soc_is_omap1710() 0
#define cpu_class_is_omap1() 0
#define cpu_class_is_omap2() 1
#endif
#if defined(CONFIG_ARCH_OMAP2)
# undef cpu_is_omap2420
# undef cpu_is_omap2422
# undef cpu_is_omap2423
# undef cpu_is_omap2430
# define cpu_is_omap2420() is_omap2420()
# define cpu_is_omap2422() is_omap2422()
# define cpu_is_omap2423() is_omap2423()
# define cpu_is_omap2430() is_omap2430()
# undef soc_is_omap2420
# undef soc_is_omap2422
# undef soc_is_omap2423
# undef soc_is_omap2430
# define soc_is_omap2420() is_omap2420()
# define soc_is_omap2422() is_omap2422()
# define soc_is_omap2423() is_omap2423()
# define soc_is_omap2430() is_omap2430()
#endif
#if defined(CONFIG_ARCH_OMAP3)
# undef cpu_is_omap3430
# undef cpu_is_ti81xx
# undef cpu_is_ti816x
# undef cpu_is_ti814x
# undef soc_is_omap3430
# undef soc_is_ti81xx
# undef soc_is_ti816x
# undef soc_is_ti814x
# undef soc_is_am35xx
# define cpu_is_omap3430() is_omap3430()
# undef cpu_is_omap3630
# define cpu_is_omap3630() is_omap363x()
# define cpu_is_ti81xx() is_ti81xx()
# define cpu_is_ti816x() is_ti816x()
# define cpu_is_ti814x() is_ti814x()
# define soc_is_omap3430() is_omap3430()
# undef soc_is_omap3630
# define soc_is_omap3630() is_omap363x()
# define soc_is_ti81xx() is_ti81xx()
# define soc_is_ti816x() is_ti816x()
# define soc_is_ti814x() is_ti814x()
# define soc_is_am35xx() is_am35xx()
#endif
@ -376,14 +376,14 @@ IS_OMAP_TYPE(3430, 0x3430)
#endif
# if defined(CONFIG_ARCH_OMAP4)
# undef cpu_is_omap44xx
# undef cpu_is_omap443x
# undef cpu_is_omap446x
# undef cpu_is_omap447x
# define cpu_is_omap44xx() is_omap44xx()
# define cpu_is_omap443x() is_omap443x()
# define cpu_is_omap446x() is_omap446x()
# define cpu_is_omap447x() is_omap447x()
# undef soc_is_omap44xx
# undef soc_is_omap443x
# undef soc_is_omap446x
# undef soc_is_omap447x
# define soc_is_omap44xx() is_omap44xx()
# define soc_is_omap443x() is_omap443x()
# define soc_is_omap446x() is_omap446x()
# define soc_is_omap447x() is_omap447x()
# endif
# if defined(CONFIG_SOC_OMAP5)
@ -556,5 +556,22 @@ level(__##fn);
#define omap_late_initcall(fn) omap_initcall(late_initcall, fn)
#define omap_late_initcall_sync(fn) omap_initcall(late_initcall_sync, fn)
#endif /* __ASSEMBLY__ */
/* Legacy defines, these can be removed when users are removed */
#define cpu_is_omap2420() soc_is_omap2420()
#define cpu_is_omap2422() soc_is_omap2422()
#define cpu_is_omap242x() soc_is_omap242x()
#define cpu_is_omap2430() soc_is_omap2430()
#define cpu_is_omap243x() soc_is_omap243x()
#define cpu_is_omap24xx() soc_is_omap24xx()
#define cpu_is_omap3430() soc_is_omap3430()
#define cpu_is_omap343x() soc_is_omap343x()
#define cpu_is_omap34xx() soc_is_omap34xx()
#define cpu_is_omap3630() soc_is_omap3630()
#define cpu_is_omap443x() soc_is_omap443x()
#define cpu_is_omap446x() soc_is_omap446x()
#define cpu_is_omap44xx() soc_is_omap44xx()
#define cpu_is_ti814x() soc_is_ti814x()
#define cpu_is_ti816x() soc_is_ti816x()
#define cpu_is_ti81xx() soc_is_ti81xx()
#endif /* __ASSEMBLY__ */

162
arch/arm/mach-omap2/timer.c
View File

@ -183,7 +183,8 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id *
of_get_property(np, "ti,timer-secure", NULL)))
continue;
of_add_property(np, &device_disabled);
if (!of_device_is_compatible(np, "ti,omap-counter32k"))
of_add_property(np, &device_disabled);
return np;
}
@ -394,7 +395,6 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
int ret;
struct device_node *np = NULL;
struct omap_hwmod *oh;
void __iomem *vbase;
const char *oh_name = "counter_32k";
/*
@ -420,18 +420,6 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
omap_hwmod_setup_one(oh_name);
if (np) {
vbase = of_iomap(np, 0);
of_node_put(np);
} else {
vbase = omap_hwmod_get_mpu_rt_va(oh);
}
if (!vbase) {
pr_warn("%s: failed to get counter_32k resource\n", __func__);
return -ENXIO;
}
ret = omap_hwmod_enable(oh);
if (ret) {
pr_warn("%s: failed to enable counter_32k module (%d)\n",
@ -439,13 +427,18 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
return ret;
}
ret = omap_init_clocksource_32k(vbase);
if (ret) {
pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
__func__, ret);
omap_hwmod_idle(oh);
}
if (!of_have_populated_dt()) {
void __iomem *vbase;
vbase = omap_hwmod_get_mpu_rt_va(oh);
ret = omap_init_clocksource_32k(vbase);
if (ret) {
pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
__func__, ret);
omap_hwmod_idle(oh);
}
}
return ret;
}
@ -476,7 +469,64 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
clocksource_gpt.name, clksrc.rate);
}
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
const char *clksrc_prop, bool gptimer)
{
omap_clk_init();
omap_dmtimer_init();
omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
/* Enable the use of clocksource="gp_timer" kernel parameter */
if (use_gptimer_clksrc || gptimer)
omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
clksrc_prop);
else
omap2_sync32k_clocksource_init();
}
void __init omap_init_time(void)
{
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL, false);
if (of_have_populated_dt())
clocksource_of_init();
}
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
void __init omap3_secure_sync32k_timer_init(void)
{
__omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
2, "timer_sys_ck", NULL, false);
}
#endif /* CONFIG_ARCH_OMAP3 */
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
void __init omap3_gptimer_timer_init(void)
{
__omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
1, "timer_sys_ck", "ti,timer-alwon", true);
}
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
static void __init omap4_sync32k_timer_init(void)
{
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
2, "sys_clkin_ck", NULL, false);
}
void __init omap4_local_timer_init(void)
{
omap4_sync32k_timer_init();
clocksource_of_init();
}
#endif
#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
/*
* The realtime counter also called master counter, is a free-running
* counter, which is related to real time. It produces the count used
@ -488,6 +538,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
*/
static void __init realtime_counter_init(void)
{
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
void __iomem *base;
static struct clk *sys_clk;
unsigned long rate;
@ -586,78 +637,9 @@ sysclk1_based:
set_cntfreq();
iounmap(base);
}
#else
static inline void __init realtime_counter_init(void)
{}
#endif
#define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
clksrc_nr, clksrc_src, clksrc_prop) \
void __init omap##name##_gptimer_timer_init(void) \
{ \
omap_clk_init(); \
omap_dmtimer_init(); \
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
clksrc_prop); \
}
#define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
clksrc_nr, clksrc_src, clksrc_prop) \
void __init omap##name##_sync32k_timer_init(void) \
{ \
omap_clk_init(); \
omap_dmtimer_init(); \
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
/* Enable the use of clocksource="gp_timer" kernel parameter */ \
if (use_gptimer_clksrc) \
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
clksrc_prop); \
else \
omap2_sync32k_clocksource_init(); \
}
#ifdef CONFIG_ARCH_OMAP2
OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL);
#endif /* CONFIG_ARCH_OMAP2 */
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL);
OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
2, "timer_sys_ck", NULL);
#endif /* CONFIG_ARCH_OMAP3 */
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
defined(CONFIG_SOC_AM43XX)
OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
1, "timer_sys_ck", "ti,timer-alwon");
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
2, "sys_clkin_ck", NULL);
#endif
#ifdef CONFIG_ARCH_OMAP4
#ifdef CONFIG_HAVE_ARM_TWD
void __init omap4_local_timer_init(void)
{
omap4_sync32k_timer_init();
clocksource_of_init();
}
#else
void __init omap4_local_timer_init(void)
{
omap4_sync32k_timer_init();
}
#endif /* CONFIG_HAVE_ARM_TWD */
#endif /* CONFIG_ARCH_OMAP4 */
#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
void __init omap5_realtime_timer_init(void)
{
omap4_sync32k_timer_init();

8
drivers/clocksource/Kconfig
View File

@ -115,6 +115,14 @@ config CLKSRC_PISTACHIO
bool
select CLKSRC_OF
config CLKSRC_TI_32K
bool "Texas Instruments 32.768 Hz Clocksource" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK
select CLKSRC_OF if OF
help
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)

1
drivers/clocksource/Makefile
View File

@ -45,6 +45,7 @@ obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o

126
drivers/clocksource/timer-ti-32k.c Normal file
View File

@ -0,0 +1,126 @@
/**
* timer-ti-32k.c - OMAP2 32k Timer Support
*
* Copyright (C) 2009 Nokia Corporation
*
* Update to use new clocksource/clockevent layers
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
* Copyright (C) 2007 MontaVista Software, Inc.
*
* Original driver:
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
* Juha Yrjölä <juha.yrjola@nokia.com>
* OMAP Dual-mode timer framework support by Timo Teras
*
* Some parts based off of TI's 24xx code:
*
* Copyright (C) 2004-2009 Texas Instruments, Inc.
*
* Roughly modelled after the OMAP1 MPU timer code.
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 of
* the License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/init.h>
#include <linux/time.h>
#include <linux/sched_clock.h>
#include <linux/clocksource.h>
#include <linux/of.h>
#include <linux/of_address.h>
/*
* 32KHz clocksource ... always available, on pretty most chips except
* OMAP 730 and 1510. Other timers could be used as clocksources, with
* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
* but systems won't necessarily want to spend resources that way.
*/
#define OMAP2_32KSYNCNT_REV_OFF 0x0
#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
struct ti_32k {
void __iomem *base;
void __iomem *counter;
struct clocksource cs;
};
static inline struct ti_32k *to_ti_32k(struct clocksource *cs)
{
return container_of(cs, struct ti_32k, cs);
}
static cycle_t ti_32k_read_cycles(struct clocksource *cs)
{
struct ti_32k *ti = to_ti_32k(cs);
return (cycle_t)readl_relaxed(ti->counter);
}
static struct ti_32k ti_32k_timer = {
.cs = {
.name = "32k_counter",
.rating = 250,
.read = ti_32k_read_cycles,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS |
CLOCK_SOURCE_SUSPEND_NONSTOP,
},
};
static u64 notrace omap_32k_read_sched_clock(void)
{
return ti_32k_read_cycles(&ti_32k_timer.cs);
}
static void __init ti_32k_timer_init(struct device_node *np)
{
int ret;
ti_32k_timer.base = of_iomap(np, 0);
if (!ti_32k_timer.base) {
pr_err("Can't ioremap 32k timer base\n");
return;
}
ti_32k_timer.counter = ti_32k_timer.base;
/*
* 32k sync Counter IP register offsets vary between the highlander
* version and the legacy ones.
*
* The 'SCHEME' bits(30-31) of the revision register is used to identify
* the version.
*/
if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) &
OMAP2_32KSYNCNT_REV_SCHEME)
ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_HIGH;
else
ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
ret = clocksource_register_hz(&ti_32k_timer.cs, 32768);
if (ret) {
pr_err("32k_counter: can't register clocksource\n");
return;
}
sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
}
CLOCKSOURCE_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k",
ti_32k_timer_init);