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Pin control fixes for the v5.9 kernel:

Browse Source 
- Fix a mux problem for I2C in the MVEBU driver.
 
 - Fix a really hairy inversion problem in the Intel Cherryview
   driver.
 
 - Fix the register for the sdc2_clk in the Qualcomm SM8250
   driver.
 
 - Check the virtual GPIO boot failur in the Mediatek driver.
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Merge tag 'pinctrl-v5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "Some pin control fixes here. All of them are driver fixes, the Intel
  Cherryview being the most interesting one.

   - Fix a mux problem for I2C in the MVEBU driver.

   - Fix a really hairy inversion problem in the Intel Cherryview
     driver.

   - Fix the register for the sdc2_clk in the Qualcomm SM8250 driver.

   - Check the virtual GPIO boot failur in the Mediatek driver"

* tag 'pinctrl-v5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: mediatek: check mtk_is_virt_gpio input parameter
  pinctrl: qcom: sm8250: correct sdc2_clk
  pinctrl: cherryview: Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs
  pinctrl: mvebu: Fix i2c sda definition for 98DX3236
This commit is contained in:
Linus Torvalds 2020-10-02 14:51:34 -07:00
commit d3d45f8220
4 changed files with 19 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -58,6 +58,7 @@
#define CHV_PADCTRL1_CFGLOCK BIT(31)
#define CHV_PADCTRL1_INVRXTX_SHIFT 4
#define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4)
#define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7)
#define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6)
#define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5)
#define CHV_PADCTRL1_ODEN BIT(3)
@ -792,11 +793,22 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
unsigned int offset)
{
u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
u32 value;
/*
* One some devices the GPIO should output the inverted value from what
* device-drivers / ACPI code expects (inverted external buffer?). The
* BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
* preserve this flag if the pin is already setup as GPIO.
*/
value = chv_readl(pctrl, offset, CHV_PADCTRL0);
if (value & CHV_PADCTRL0_GPIOEN)
invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
value = chv_readl(pctrl, offset, CHV_PADCTRL1);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~CHV_PADCTRL1_INVRXTX_MASK;
value &= ~invrxtx_mask;
chv_writel(pctrl, offset, CHV_PADCTRL1, value);
}

4
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
View File

@ -259,6 +259,10 @@ bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
/* if the GPIO is not supported for eint mode */
if (desc->eint.eint_m == NO_EINT_SUPPORT)
return virt_gpio;
if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
virt_gpio = true;

2
drivers/pinctrl/mvebu/pinctrl-armada-xp.c
View File

@ -414,7 +414,7 @@ static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)),
MPP_MODE(15,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "i2c0", "sda", V_98DX3236_PLUS)),
MPP_VAR_FUNCTION(0x1, "i2c0", "sda", V_98DX3236_PLUS)),
MPP_MODE(16,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)),

2
drivers/pinctrl/qcom/pinctrl-sm8250.c
View File

@ -1308,7 +1308,7 @@ static const struct msm_pingroup sm8250_groups[] = {
[178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _),
[179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _),
[180] = UFS_RESET(ufs_reset, 0xb8000),
[181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6),
[181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6),
[182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3),
[183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0),
};