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drm/amdgpu: toggle DF-Cstate when accessing UMC ras error related registers
On arcturus, DF-Cstate needs to be toggled off/on before and after accessing UMC error counter and error address registers, otherwise, clearing such registers may fail. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -186,6 +186,10 @@ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
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if (rsmu_umc_index_state)
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umc_v6_1_disable_umc_index_mode(adev);
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if ((adev->asic_type == CHIP_ARCTURUS) &&
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amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
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DRM_WARN("Fail to disable DF-Cstate.\n");
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LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
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umc_reg_offset = get_umc_6_reg_offset(adev,
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umc_inst,
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@ -199,6 +203,10 @@ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
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&(err_data->ue_count));
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}
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if ((adev->asic_type == CHIP_ARCTURUS) &&
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amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
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DRM_WARN("Fail to enable DF-Cstate\n");
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if (rsmu_umc_index_state)
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umc_v6_1_enable_umc_index_mode(adev);
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}
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@ -288,6 +296,10 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
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if (rsmu_umc_index_state)
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umc_v6_1_disable_umc_index_mode(adev);
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if ((adev->asic_type == CHIP_ARCTURUS) &&
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amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
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DRM_WARN("Fail to disable DF-Cstate.\n");
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LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
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umc_reg_offset = get_umc_6_reg_offset(adev,
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umc_inst,
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@ -300,6 +312,10 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
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umc_inst);
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}
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if ((adev->asic_type == CHIP_ARCTURUS) &&
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amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
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DRM_WARN("Fail to enable DF-Cstate\n");
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if (rsmu_umc_index_state)
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umc_v6_1_enable_umc_index_mode(adev);
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}
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