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ACPI: EC: Fold acpi_ec_clear_gpe() into its caller
Fold acpi_ec_clear_gpe() which is only used in one place into its caller and clean up comments related to that function while at it. No intentional functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -372,23 +372,6 @@ static inline void acpi_ec_disable_gpe(struct acpi_ec *ec, bool close)
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}
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}
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static inline void acpi_ec_clear_gpe(struct acpi_ec *ec)
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{
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/*
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* GPE STS is a W1C register, which means:
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* 1. Software can clear it without worrying about clearing other
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* GPEs' STS bits when the hardware sets them in parallel.
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* 2. As long as software can ensure only clearing it when it is
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* set, hardware won't set it in parallel.
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* So software can clear GPE in any contexts.
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* Warning: do not move the check into advance_transaction() as the
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* EC commands will be sent without GPE raised.
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*/
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if (!acpi_ec_is_gpe_raised(ec))
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return;
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acpi_clear_gpe(NULL, ec->gpe);
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}
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/* --------------------------------------------------------------------------
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* Transaction Management
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* -------------------------------------------------------------------------- */
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@ -639,13 +622,21 @@ static void advance_transaction(struct acpi_ec *ec, bool interrupt)
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bool wakeup = false;
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ec_dbg_stm("%s (%d)", interrupt ? "IRQ" : "TASK", smp_processor_id());
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/*
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* By always clearing STS before handling all indications, we can
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* ensure a hardware STS 0->1 change after this clearing can always
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* trigger a GPE interrupt.
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* Clear GPE_STS upfront to allow subsequent hardware GPE_STS 0->1
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* changes to always trigger a GPE interrupt.
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*
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* GPE STS is a W1C register, which means:
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*
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* 1. Software can clear it without worrying about clearing the other
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* GPEs' STS bits when the hardware sets them in parallel.
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*
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* 2. As long as software can ensure only clearing it when it is set,
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* hardware won't set it in parallel.
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*/
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if (ec->gpe >= 0)
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acpi_ec_clear_gpe(ec);
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if (ec->gpe >= 0 && acpi_ec_is_gpe_raised(ec))
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acpi_clear_gpe(NULL, ec->gpe);
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status = acpi_ec_read_status(ec);
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t = ec->curr;
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