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Merge branch kvm-arm64/aarch32-idreg-trap into kvmarm-master/next
* kvm-arm64/aarch32-idreg-trap: : . : Add trapping/sanitising infrastructure for AArch32 systen registers, : allowing more control over what we actually expose (such as the PMU). : : Patches courtesy of Oliver and Alexandru. : . KVM: arm64: Fix new instances of 32bit ESRs KVM: arm64: Hide AArch32 PMU registers when not available KVM: arm64: Start trapping ID registers for 32 bit guests KVM: arm64: Plumb cp10 ID traps through the AArch64 sysreg handler KVM: arm64: Wire up CP15 feature registers to their AArch64 equivalents KVM: arm64: Don't write to Rt unless sys_reg emulation succeeds KVM: arm64: Return a bool from emulate_cp() Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
commit
d25f30fe41
@ -80,11 +80,12 @@
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* FMO: Override CPSR.F and enable signaling with VF
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* SWIO: Turn set/way invalidates into set/way clean+invalidate
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* PTW: Take a stage2 fault if a stage1 walk steps in device memory
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* TID3: Trap EL1 reads of group 3 ID registers
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*/
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#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
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HCR_BSU_IS | HCR_FB | HCR_TACR | \
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HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
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HCR_FMO | HCR_IMO | HCR_PTW )
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HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 )
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#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
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#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
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#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
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@ -87,13 +87,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
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if (vcpu_el1_is_32bit(vcpu))
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vcpu->arch.hcr_el2 &= ~HCR_RW;
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else
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/*
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* TID3: trap feature register accesses that we virtualise.
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* For now this is conditional, since no AArch32 feature regs
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* are currently virtualised.
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*/
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vcpu->arch.hcr_el2 |= HCR_TID3;
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if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||
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vcpu_el1_is_32bit(vcpu))
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@ -688,6 +688,7 @@ int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
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int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
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int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
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int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
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int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
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void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
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@ -194,6 +194,7 @@ static exit_handle_fn arm_exit_handlers[] = {
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[ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64,
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[ESR_ELx_EC_CP14_MR] = kvm_handle_cp14_32,
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[ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store,
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[ESR_ELx_EC_CP10_ID] = kvm_handle_cp10_id,
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[ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64,
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[ESR_ELx_EC_HVC32] = handle_hvc,
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[ESR_ELx_EC_SMC32] = handle_smc,
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@ -2023,20 +2023,22 @@ static const struct sys_reg_desc cp14_64_regs[] = {
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{ Op1( 0), CRm( 2), .access = trap_raz_wi },
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};
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#define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \
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AA32(_map), \
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Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
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.visibility = pmu_visibility
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/* Macro to expand the PMEVCNTRn register */
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#define PMU_PMEVCNTR(n) \
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/* PMEVCNTRn */ \
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{ Op1(0), CRn(0b1110), \
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CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
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access_pmu_evcntr }
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{ CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
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(0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
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.access = access_pmu_evcntr }
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/* Macro to expand the PMEVTYPERn register */
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#define PMU_PMEVTYPER(n) \
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/* PMEVTYPERn */ \
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{ Op1(0), CRn(0b1110), \
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CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
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access_pmu_evtyper }
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{ CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
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(0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
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.access = access_pmu_evtyper }
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/*
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* Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
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* depending on the way they are accessed (as a 32bit or a 64bit
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@ -2076,25 +2078,25 @@ static const struct sys_reg_desc cp15_regs[] = {
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{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
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/* PMU */
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{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
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{ Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
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{ Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
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{ Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
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{ Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
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{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
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{ AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
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{ AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
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{ Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
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{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
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{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
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{ Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
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{ Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
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{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
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{ Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
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{ AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid },
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{ AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
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{ CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
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{ CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
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{ CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
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{ CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
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/* PMMIR */
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{ Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
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/* PRRR/MAIR0 */
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{ AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
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@ -2179,7 +2181,7 @@ static const struct sys_reg_desc cp15_regs[] = {
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PMU_PMEVTYPER(29),
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PMU_PMEVTYPER(30),
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/* PMCCFILTR */
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{ Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
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{ Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
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{ Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
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@ -2188,7 +2190,7 @@ static const struct sys_reg_desc cp15_regs[] = {
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static const struct sys_reg_desc cp15_64_regs[] = {
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{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
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{ Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
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{ CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
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{ Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
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{ Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
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{ Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
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@ -2255,27 +2257,27 @@ static void perform_access(struct kvm_vcpu *vcpu,
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* @table: array of trap descriptors
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* @num: size of the trap descriptor array
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*
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* Return 0 if the access has been handled, and -1 if not.
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* Return true if the access has been handled, false if not.
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*/
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static int emulate_cp(struct kvm_vcpu *vcpu,
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struct sys_reg_params *params,
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const struct sys_reg_desc *table,
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size_t num)
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static bool emulate_cp(struct kvm_vcpu *vcpu,
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struct sys_reg_params *params,
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const struct sys_reg_desc *table,
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size_t num)
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{
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const struct sys_reg_desc *r;
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if (!table)
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return -1; /* Not handled */
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return false; /* Not handled */
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r = find_reg(params, table, num);
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if (r) {
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perform_access(vcpu, params, r);
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return 0;
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return true;
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}
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/* Not handled */
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return -1;
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return false;
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}
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static void unhandled_cp_access(struct kvm_vcpu *vcpu,
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@ -2313,7 +2315,7 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
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size_t nr_global)
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{
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struct sys_reg_params params;
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u32 esr = kvm_vcpu_get_esr(vcpu);
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u64 esr = kvm_vcpu_get_esr(vcpu);
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int Rt = kvm_vcpu_sys_get_rt(vcpu);
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int Rt2 = (esr >> 10) & 0x1f;
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@ -2339,7 +2341,7 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
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* potential register operation in the case of a read and return
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* with success.
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*/
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if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
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if (emulate_cp(vcpu, ¶ms, global, nr_global)) {
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/* Split up the value between registers for the read side */
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if (!params.is_write) {
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vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
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@ -2353,34 +2355,144 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
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return 1;
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}
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static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
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/*
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* The CP10 ID registers are architecturally mapped to AArch64 feature
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* registers. Abuse that fact so we can rely on the AArch64 handler for accesses
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* from AArch32.
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*/
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static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
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{
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u8 reg_id = (esr >> 10) & 0xf;
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bool valid;
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params->is_write = ((esr & 1) == 0);
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params->Op0 = 3;
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params->Op1 = 0;
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params->CRn = 0;
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params->CRm = 3;
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/* CP10 ID registers are read-only */
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valid = !params->is_write;
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switch (reg_id) {
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/* MVFR0 */
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case 0b0111:
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params->Op2 = 0;
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break;
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/* MVFR1 */
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case 0b0110:
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params->Op2 = 1;
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break;
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/* MVFR2 */
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case 0b0101:
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params->Op2 = 2;
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break;
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default:
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valid = false;
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}
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if (valid)
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return true;
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kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
|
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params->is_write ? "write" : "read", reg_id);
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return false;
|
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}
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|
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/**
|
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* kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
|
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* VFP Register' from AArch32.
|
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* @vcpu: The vCPU pointer
|
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*
|
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* MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
|
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* Work out the correct AArch64 system register encoding and reroute to the
|
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* AArch64 system register emulation.
|
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*/
|
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int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
|
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{
|
||||
int Rt = kvm_vcpu_sys_get_rt(vcpu);
|
||||
u64 esr = kvm_vcpu_get_esr(vcpu);
|
||||
struct sys_reg_params params;
|
||||
|
||||
/* UNDEF on any unhandled register access */
|
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if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) {
|
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kvm_inject_undefined(vcpu);
|
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return 1;
|
||||
}
|
||||
|
||||
if (emulate_sys_reg(vcpu, ¶ms))
|
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vcpu_set_reg(vcpu, Rt, params.regval);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
|
||||
* CRn=0, which corresponds to the AArch32 feature
|
||||
* registers.
|
||||
* @vcpu: the vCPU pointer
|
||||
* @params: the system register access parameters.
|
||||
*
|
||||
* Our cp15 system register tables do not enumerate the AArch32 feature
|
||||
* registers. Conveniently, our AArch64 table does, and the AArch32 system
|
||||
* register encoding can be trivially remapped into the AArch64 for the feature
|
||||
* registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
|
||||
*
|
||||
* According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
|
||||
* System registers with (coproc=0b1111, CRn==c0)", read accesses from this
|
||||
* range are either UNKNOWN or RES0. Rerouting remains architectural as we
|
||||
* treat undefined registers in this range as RAZ.
|
||||
*/
|
||||
static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
|
||||
struct sys_reg_params *params)
|
||||
{
|
||||
int Rt = kvm_vcpu_sys_get_rt(vcpu);
|
||||
|
||||
/* Treat impossible writes to RO registers as UNDEFINED */
|
||||
if (params->is_write) {
|
||||
unhandled_cp_access(vcpu, params);
|
||||
return 1;
|
||||
}
|
||||
|
||||
params->Op0 = 3;
|
||||
|
||||
/*
|
||||
* All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
|
||||
* Avoid conflicting with future expansion of AArch64 feature registers
|
||||
* and simply treat them as RAZ here.
|
||||
*/
|
||||
if (params->CRm > 3)
|
||||
params->regval = 0;
|
||||
else if (!emulate_sys_reg(vcpu, params))
|
||||
return 1;
|
||||
|
||||
vcpu_set_reg(vcpu, Rt, params->regval);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
|
||||
* @vcpu: The VCPU pointer
|
||||
* @run: The kvm_run struct
|
||||
*/
|
||||
static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
|
||||
struct sys_reg_params *params,
|
||||
const struct sys_reg_desc *global,
|
||||
size_t nr_global)
|
||||
{
|
||||
struct sys_reg_params params;
|
||||
u32 esr = kvm_vcpu_get_esr(vcpu);
|
||||
int Rt = kvm_vcpu_sys_get_rt(vcpu);
|
||||
|
||||
params.CRm = (esr >> 1) & 0xf;
|
||||
params.regval = vcpu_get_reg(vcpu, Rt);
|
||||
params.is_write = ((esr & 1) == 0);
|
||||
params.CRn = (esr >> 10) & 0xf;
|
||||
params.Op0 = 0;
|
||||
params.Op1 = (esr >> 14) & 0x7;
|
||||
params.Op2 = (esr >> 17) & 0x7;
|
||||
params->regval = vcpu_get_reg(vcpu, Rt);
|
||||
|
||||
if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
|
||||
if (!params.is_write)
|
||||
vcpu_set_reg(vcpu, Rt, params.regval);
|
||||
if (emulate_cp(vcpu, params, global, nr_global)) {
|
||||
if (!params->is_write)
|
||||
vcpu_set_reg(vcpu, Rt, params->regval);
|
||||
return 1;
|
||||
}
|
||||
|
||||
unhandled_cp_access(vcpu, ¶ms);
|
||||
unhandled_cp_access(vcpu, params);
|
||||
return 1;
|
||||
}
|
||||
|
||||
@ -2391,7 +2503,20 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
|
||||
|
||||
int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
|
||||
struct sys_reg_params params;
|
||||
|
||||
params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
|
||||
|
||||
/*
|
||||
* Certain AArch32 ID registers are handled by rerouting to the AArch64
|
||||
* system register table. Registers in the ID range where CRm=0 are
|
||||
* excluded from this scheme as they do not trivially map into AArch64
|
||||
* system register encodings.
|
||||
*/
|
||||
if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
|
||||
return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
|
||||
|
||||
return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
|
||||
}
|
||||
|
||||
int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
|
||||
@ -2401,7 +2526,11 @@ int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
|
||||
|
||||
int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
|
||||
struct sys_reg_params params;
|
||||
|
||||
params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
|
||||
|
||||
return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs));
|
||||
}
|
||||
|
||||
static bool is_imp_def_sys_reg(struct sys_reg_params *params)
|
||||
@ -2410,7 +2539,14 @@ static bool is_imp_def_sys_reg(struct sys_reg_params *params)
|
||||
return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
|
||||
}
|
||||
|
||||
static int emulate_sys_reg(struct kvm_vcpu *vcpu,
|
||||
/**
|
||||
* emulate_sys_reg - Emulate a guest access to an AArch64 system register
|
||||
* @vcpu: The VCPU pointer
|
||||
* @params: Decoded system register parameters
|
||||
*
|
||||
* Return: true if the system register access was successful, false otherwise.
|
||||
*/
|
||||
static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
|
||||
struct sys_reg_params *params)
|
||||
{
|
||||
const struct sys_reg_desc *r;
|
||||
@ -2419,7 +2555,10 @@ static int emulate_sys_reg(struct kvm_vcpu *vcpu,
|
||||
|
||||
if (likely(r)) {
|
||||
perform_access(vcpu, params, r);
|
||||
} else if (is_imp_def_sys_reg(params)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
if (is_imp_def_sys_reg(params)) {
|
||||
kvm_inject_undefined(vcpu);
|
||||
} else {
|
||||
print_sys_reg_msg(params,
|
||||
@ -2427,7 +2566,7 @@ static int emulate_sys_reg(struct kvm_vcpu *vcpu,
|
||||
*vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
|
||||
kvm_inject_undefined(vcpu);
|
||||
}
|
||||
return 1;
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -2455,18 +2594,18 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
|
||||
struct sys_reg_params params;
|
||||
unsigned long esr = kvm_vcpu_get_esr(vcpu);
|
||||
int Rt = kvm_vcpu_sys_get_rt(vcpu);
|
||||
int ret;
|
||||
|
||||
trace_kvm_handle_sys_reg(esr);
|
||||
|
||||
params = esr_sys64_to_params(esr);
|
||||
params.regval = vcpu_get_reg(vcpu, Rt);
|
||||
|
||||
ret = emulate_sys_reg(vcpu, ¶ms);
|
||||
if (!emulate_sys_reg(vcpu, ¶ms))
|
||||
return 1;
|
||||
|
||||
if (!params.is_write)
|
||||
vcpu_set_reg(vcpu, Rt, params.regval);
|
||||
return ret;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
|
@ -35,12 +35,19 @@ struct sys_reg_params {
|
||||
.Op2 = ((esr) >> 17) & 0x7, \
|
||||
.is_write = !((esr) & 1) })
|
||||
|
||||
#define esr_cp1x_32_to_params(esr) \
|
||||
((struct sys_reg_params){ .Op1 = ((esr) >> 14) & 0x7, \
|
||||
.CRn = ((esr) >> 10) & 0xf, \
|
||||
.CRm = ((esr) >> 1) & 0xf, \
|
||||
.Op2 = ((esr) >> 17) & 0x7, \
|
||||
.is_write = !((esr) & 1) })
|
||||
|
||||
struct sys_reg_desc {
|
||||
/* Sysreg string for debug */
|
||||
const char *name;
|
||||
|
||||
enum {
|
||||
AA32_ZEROHIGH,
|
||||
AA32_DIRECT,
|
||||
AA32_LO,
|
||||
AA32_HI,
|
||||
} aarch32_map;
|
||||
|
Loading…
Reference in New Issue
Block a user