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PCI: aardvark: Fix masking and unmasking legacy INTx interrupts

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irq_mask and irq_unmask callbacks need to be properly guarded by raw spin
locks as masking/unmasking procedure needs atomic read-modify-write
operation on hardware register.

Link: https://lore.kernel.org/r/20210820155020.3000-1-pali@kernel.org
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
This commit is contained in:
Pali Rohár 2021-08-20 17:50:20 +02:00 committed by Lorenzo Pieralisi
parent 64f160e19e
commit d212dcee27
1 changed files with 9 additions and 0 deletions
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9
drivers/pci/controller/pci-aardvark.c
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@ -232,6 +232,7 @@ struct advk_pcie {
u8 wins_count; u8 wins_count;
struct irq_domain *irq_domain; struct irq_domain *irq_domain;
struct irq_chip irq_chip; struct irq_chip irq_chip;
raw_spinlock_t irq_lock;
struct irq_domain *msi_domain; struct irq_domain *msi_domain;
struct irq_domain *msi_inner_domain; struct irq_domain *msi_inner_domain;
struct irq_chip msi_bottom_irq_chip; struct irq_chip msi_bottom_irq_chip;
@ -1104,22 +1105,28 @@ static void advk_pcie_irq_mask(struct irq_data *d)
{ {
struct advk_pcie *pcie = d->domain->host_data; struct advk_pcie *pcie = d->domain->host_data;
irq_hw_number_t hwirq = irqd_to_hwirq(d); irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
u32 mask; u32 mask;
raw_spin_lock_irqsave(&pcie->irq_lock, flags);
mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
mask |= PCIE_ISR1_INTX_ASSERT(hwirq); mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
} }
static void advk_pcie_irq_unmask(struct irq_data *d) static void advk_pcie_irq_unmask(struct irq_data *d)
{ {
struct advk_pcie *pcie = d->domain->host_data; struct advk_pcie *pcie = d->domain->host_data;
irq_hw_number_t hwirq = irqd_to_hwirq(d); irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
u32 mask; u32 mask;
raw_spin_lock_irqsave(&pcie->irq_lock, flags);
mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
} }
static int advk_pcie_irq_map(struct irq_domain *h, static int advk_pcie_irq_map(struct irq_domain *h,
@ -1203,6 +1210,8 @@ static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
struct irq_chip *irq_chip; struct irq_chip *irq_chip;
int ret = 0; int ret = 0;
raw_spin_lock_init(&pcie->irq_lock);
pcie_intc_node = of_get_next_child(node, NULL); pcie_intc_node = of_get_next_child(node, NULL);
if (!pcie_intc_node) { if (!pcie_intc_node) {
dev_err(dev, "No PCIe Intc node found\n"); dev_err(dev, "No PCIe Intc node found\n");