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drm/gma500: Make all chips use gma_wait_for_vblank
Also remove the duplicated oaktrail function. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
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@ -34,6 +34,7 @@
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#include "psb_drv.h"
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "gma_display.h"
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#include <drm/drm_dp_helper.h>
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#define _wait_for(COND, MS, W) ({ \
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@ -1317,7 +1318,7 @@ cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder)
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/* Enable output, wait for it to become active */
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REG_WRITE(intel_dp->output_reg, reg);
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REG_READ(intel_dp->output_reg);
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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DRM_DEBUG_KMS("Link config\n");
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/* Write the link configuration data */
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@ -65,7 +65,7 @@ void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)
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}
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/* FIXME JLIU7_PO */
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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return;
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/* Wait for for the pipe disable to take effect. */
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@ -93,7 +93,7 @@ void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe)
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}
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/* FIXME JLIU7_PO */
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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return;
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/* Wait for for the pipe enable to take effect. */
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@ -1034,7 +1034,7 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
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/* Wait for for the pipe enable to take effect. */
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REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]);
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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mrst_crtc_mode_set_exit:
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@ -242,7 +242,7 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
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REG_READ(map->conf);
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}
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/* Wait for for the pipe disable to take effect. */
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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temp = REG_READ(map->dpll);
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if ((temp & DPLL_VCO_ENABLE) != 0) {
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@ -484,10 +484,10 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
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REG_WRITE(map->conf, pipeconf);
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REG_READ(map->conf);
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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REG_WRITE(map->cntr, dspcntr);
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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oaktrail_crtc_mode_set_exit:
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gma_power_end(dev);
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@ -155,12 +155,6 @@ static void oaktrail_hdmi_audio_disable(struct drm_device *dev)
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HDMI_READ(HDMI_HCR);
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}
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static void wait_for_vblank(struct drm_device *dev)
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{
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/* Wait for 20ms, i.e. one cycle at 50hz. */
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mdelay(20);
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}
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static unsigned int htotal_calculate(struct drm_display_mode *mode)
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{
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u32 htotal, new_crtc_htotal;
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@ -372,10 +366,10 @@ int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc,
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REG_WRITE(PCH_PIPEBCONF, pipeconf);
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REG_READ(PCH_PIPEBCONF);
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wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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REG_WRITE(dspcntr_reg, dspcntr);
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wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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gma_power_end(dev);
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@ -459,7 +453,7 @@ void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode)
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REG_READ(PCH_PIPEBCONF);
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}
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wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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/* Enable plane */
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temp = REG_READ(DSPBCNTR);
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@ -82,12 +82,6 @@ static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
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clock->dot = clock->vco / clock->p;
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}
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void psb_intel_wait_for_vblank(struct drm_device *dev)
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{
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/* Wait for 20ms, i.e. one cycle at 50hz. */
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mdelay(20);
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}
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static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
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int x, int y, struct drm_framebuffer *old_fb)
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{
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@ -244,7 +238,7 @@ static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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}
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/* Wait for vblank for the disable to take effect. */
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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temp = REG_READ(map->dpll);
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if ((temp & DPLL_VCO_ENABLE) != 0) {
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@ -516,14 +510,14 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
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REG_WRITE(map->conf, pipeconf);
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REG_READ(map->conf);
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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REG_WRITE(map->cntr, dspcntr);
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/* Flush the plane changes */
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crtc_funcs->mode_set_base(crtc, x, y, old_fb);
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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return 0;
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}
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@ -669,12 +663,12 @@ static void psb_intel_crtc_restore(struct drm_crtc *crtc)
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REG_WRITE(map->base, crtc_state->saveDSPBASE);
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REG_WRITE(map->conf, crtc_state->savePIPECONF);
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
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REG_WRITE(map->base, crtc_state->saveDSPBASE);
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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paletteReg = map->palette;
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for (i = 0; i < 256; ++i)
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@ -246,7 +246,6 @@ extern struct drm_encoder *psb_intel_best_encoder(struct drm_connector
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extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
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struct drm_crtc *crtc);
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extern void psb_intel_wait_for_vblank(struct drm_device *dev);
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extern int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev,
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@ -1121,7 +1121,7 @@ static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
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if ((temp & SDVO_ENABLE) == 0)
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psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
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for (i = 0; i < 2; i++)
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psb_intel_wait_for_vblank(dev);
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gma_wait_for_vblank(dev);
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status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
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/* Warn if the device reported failure to sync.
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