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pinctrl: th1520: Update pinmux tables

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When Drew took over the pinctrl driver it seems like he didn't use the
git tree I pointed him at and thus missed some important fixes to the
tables describing valid pinmux settings.

The documentation has a nice overview table of these settings but
unfortunately it doesn't fully match the register descriptions, which
seem to be the correct version.

Fixes: bed5cd6f8a ("pinctrl: Add driver for the T-Head TH1520 SoC")
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Drew Fustini <dfustini@tenstorrent.com>
Tested-by: Drew Fustini <dfustini@tenstorrent.com>
Link: https://lore.kernel.org/20241011144826.381104-3-emil.renner.berthing@canonical.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Emil Renner Berthing 2024-10-11 16:48:24 +02:00 committed by Linus Walleij
parent ca35d5d245
commit d1e16e2199
1 changed files with 9 additions and 9 deletions
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18
drivers/pinctrl/pinctrl-th1520.c
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@ -221,9 +221,9 @@ static const struct pinctrl_pin_desc th1520_group2_pins[] = {
TH1520_PAD(15, UART4_RTSN, UART, ____, ____, GPIO, ____, ____, 0),
TH1520_PAD(16, UART3_TXD, DBG, UART, ____, GPIO, ____, ____, 0),
TH1520_PAD(17, UART3_RXD, DBG, UART, ____, GPIO, ____, ____, 0),
TH1520_PAD(18, GPIO0_18, GPIO, I2C, ____, ____, ____, ____, 0),
TH1520_PAD(19, GPIO0_19, GPIO, I2C, ____, ____, ____, ____, 0),
TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, ____, ____, 0),
TH1520_PAD(18, GPIO0_18, GPIO, I2C, ____, ____, DPU0, DPU1, 0),
TH1520_PAD(19, GPIO0_19, GPIO, I2C, ____, ____, DPU0, DPU1, 0),
TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, DPU0, DPU1, 0),
TH1520_PAD(21, GPIO0_21, GPIO, UART, IR, ____, DPU0, DPU1, 0),
TH1520_PAD(22, GPIO0_22, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0),
TH1520_PAD(23, GPIO0_23, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0),
@ -241,7 +241,7 @@ static const struct pinctrl_pin_desc th1520_group2_pins[] = {
TH1520_PAD(35, GPIO1_3, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
TH1520_PAD(36, GPIO1_4, GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
TH1520_PAD(37, GPIO1_5, GPIO, ____, ____, ____, DPU0, DPU1, 0),
TH1520_PAD(38, GPIO1_6, GPIO, ____, ____, ____, DPU0, DPU1, 0),
TH1520_PAD(38, GPIO1_6, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
TH1520_PAD(39, GPIO1_7, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
TH1520_PAD(40, GPIO1_8, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
TH1520_PAD(41, GPIO1_9, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
@ -256,11 +256,11 @@ static const struct pinctrl_pin_desc th1520_group2_pins[] = {
TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0),
TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0),
TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0),
TH1520_PAD(53, GPIO1_21, GPIO, ____, ISP, ____, ____, ____, 0),
TH1520_PAD(54, GPIO1_22, GPIO, ____, ISP, ____, ____, ____, 0),
TH1520_PAD(55, GPIO1_23, GPIO, ____, ISP, ____, ____, ____, 0),
TH1520_PAD(56, GPIO1_24, GPIO, ____, ISP, ____, ____, ____, 0),
TH1520_PAD(57, GPIO1_25, GPIO, ____, ISP, ____, ____, ____, 0),
TH1520_PAD(53, GPIO1_21, JTAG, ____, ISP, GPIO, ____, ____, 0),
TH1520_PAD(54, GPIO1_22, JTAG, ____, ISP, GPIO, ____, ____, 0),
TH1520_PAD(55, GPIO1_23, JTAG, ____, ISP, GPIO, ____, ____, 0),
TH1520_PAD(56, GPIO1_24, JTAG, ____, ISP, GPIO, ____, ____, 0),
TH1520_PAD(57, GPIO1_25, JTAG, ____, ISP, GPIO, ____, ____, 0),
TH1520_PAD(58, GPIO1_26, GPIO, ____, ISP, ____, ____, ____, 0),
TH1520_PAD(59, GPIO1_27, GPIO, ____, ISP, ____, ____, ____, 0),
TH1520_PAD(60, GPIO1_28, GPIO, ____, ISP, ____, ____, ____, 0),