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powerpc updates for 4.1

Browse Source 
- Numerous minor fixes, cleanups etc.
 - More EEH work from Gavin to remove its dependency on device_nodes.
 - Memory hotplug implemented entirely in the kernel from Nathan Fontenot.
 - Removal of redundant CONFIG_PPC_OF by Kevin Hao.
 - Rewrite of VPHN parsing logic & tests from Greg Kurz.
 - A fix from Nish Aravamudan to reduce memory usage by clamping
   nodes_possible_map.
 - Support for pstore on powernv from Hari Bathini.
 - Removal of old powerpc specific byte swap routines by David Gibson.
 - Fix from Vasant Hegde to prevent the flash driver telling you it was flashing
   your firmware when it wasn't.
 - Patch from Ben Herrenschmidt to add an OPAL heartbeat driver.
 - Fix for an oops causing get/put_cpu_var() imbalance in perf by Jan Stancek.
 - Some fixes for migration from Tyrel Datwyler.
 - A new syscall to switch the cpu endian by Michael Ellerman.
 - Large series from Wei Yang to implement SRIOV, reviewed and acked by Bjorn.
 - A fix for the OPAL sensor driver from Cédric Le Goater.
 - Fixes to get STRICT_MM_TYPECHECKS building again by Michael Ellerman.
 - Large series from Daniel Axtens to make our PCI hooks per PHB rather than per
   machine.
 - Small patch from Sam Bobroff to explicitly abort non-suspended transactions
   on syscalls, plus a test to exercise it.
 - Numerous reworks and fixes for the 24x7 PMU from Sukadev Bhattiprolu.
 - Small patch to enable the hard lockup detector from Anton Blanchard.
 - Fix from Dave Olson for missing L2 cache information on some CPUs.
 - Some fixes from Michael Ellerman to get Cell machines booting again.
 - Freescale updates from Scott: Highlights include BMan device tree nodes, an
   MSI erratum workaround, a couple minor performance improvements, config
   updates, and misc fixes/cleanup.
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Merge tag 'powerpc-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux

Pull powerpc updates from Michael Ellerman:

 - Numerous minor fixes, cleanups etc.

 - More EEH work from Gavin to remove its dependency on device_nodes.

 - Memory hotplug implemented entirely in the kernel from Nathan
   Fontenot.

 - Removal of redundant CONFIG_PPC_OF by Kevin Hao.

 - Rewrite of VPHN parsing logic & tests from Greg Kurz.

 - A fix from Nish Aravamudan to reduce memory usage by clamping
   nodes_possible_map.

 - Support for pstore on powernv from Hari Bathini.

 - Removal of old powerpc specific byte swap routines by David Gibson.

 - Fix from Vasant Hegde to prevent the flash driver telling you it was
   flashing your firmware when it wasn't.

 - Patch from Ben Herrenschmidt to add an OPAL heartbeat driver.

 - Fix for an oops causing get/put_cpu_var() imbalance in perf by Jan
   Stancek.

 - Some fixes for migration from Tyrel Datwyler.

 - A new syscall to switch the cpu endian by Michael Ellerman.

 - Large series from Wei Yang to implement SRIOV, reviewed and acked by
   Bjorn.

 - A fix for the OPAL sensor driver from Cédric Le Goater.

 - Fixes to get STRICT_MM_TYPECHECKS building again by Michael Ellerman.

 - Large series from Daniel Axtens to make our PCI hooks per PHB rather
   than per machine.

 - Small patch from Sam Bobroff to explicitly abort non-suspended
   transactions on syscalls, plus a test to exercise it.

 - Numerous reworks and fixes for the 24x7 PMU from Sukadev Bhattiprolu.

 - Small patch to enable the hard lockup detector from Anton Blanchard.

 - Fix from Dave Olson for missing L2 cache information on some CPUs.

 - Some fixes from Michael Ellerman to get Cell machines booting again.

 - Freescale updates from Scott: Highlights include BMan device tree
   nodes, an MSI erratum workaround, a couple minor performance
   improvements, config updates, and misc fixes/cleanup.

* tag 'powerpc-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux: (196 commits)
  powerpc/powermac: Fix build error seen with powermac smp builds
  powerpc/pseries: Fix compile of memory hotplug without CONFIG_MEMORY_HOTREMOVE
  powerpc: Remove PPC32 code from pseries specific find_and_init_phbs()
  powerpc/cell: Fix iommu breakage caused by controller_ops change
  powerpc/eeh: Fix crash in eeh_add_device_early() on Cell
  powerpc/perf: Cap 64bit userspace backtraces to PERF_MAX_STACK_DEPTH
  powerpc/perf/hv-24x7: Fail 24x7 initcall if create_events_from_catalog() fails
  powerpc/pseries: Correct memory hotplug locking
  powerpc: Fix missing L2 cache size in /sys/devices/system/cpu
  powerpc: Add ppc64 hard lockup detector support
  oprofile: Disable oprofile NMI timer on ppc64
  powerpc/perf/hv-24x7: Add missing put_cpu_var()
  powerpc/perf/hv-24x7: Break up single_24x7_request
  powerpc/perf/hv-24x7: Define update_event_count()
  powerpc/perf/hv-24x7: Whitespace cleanup
  powerpc/perf/hv-24x7: Define add_event_to_24x7_request()
  powerpc/perf/hv-24x7: Rename hv_24x7_event_update
  powerpc/perf/hv-24x7: Move debug prints to separate function
  powerpc/perf/hv-24x7: Drop event_24x7_request()
  powerpc/perf/hv-24x7: Use pr_devel() to log message
  ...

Conflicts:
	tools/testing/selftests/powerpc/Makefile
	tools/testing/selftests/powerpc/tm/Makefile
This commit is contained in:
Linus Torvalds 2015-04-16 13:53:32 -05:00
commit d19d5efd8c
299 changed files with 8765 additions and 9770 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/ABI/testing/sysfs-class-cxl
View File

@ -100,7 +100,7 @@ Description: read only
Hexadecimal value of the device ID found in this AFU
configuration record.
What: /sys/class/cxl/<afu>/cr<config num>/vendor
What: /sys/class/cxl/<afu>/cr<config num>/class
Date: February 2015
Contact: linuxppc-dev@lists.ozlabs.org
Description: read only

301
Documentation/powerpc/pci_iov_resource_on_powernv.txt Normal file
View File

@ -0,0 +1,301 @@
Wei Yang <weiyang@linux.vnet.ibm.com>
Benjamin Herrenschmidt <benh@au1.ibm.com>
Bjorn Helgaas <bhelgaas@google.com>
26 Aug 2014
This document describes the requirement from hardware for PCI MMIO resource
sizing and assignment on PowerKVM and how generic PCI code handles this
requirement. The first two sections describe the concepts of Partitionable
Endpoints and the implementation on P8 (IODA2). The next two sections talks
about considerations on enabling SRIOV on IODA2.
1. Introduction to Partitionable Endpoints
A Partitionable Endpoint (PE) is a way to group the various resources
associated with a device or a set of devices to provide isolation between
partitions (i.e., filtering of DMA, MSIs etc.) and to provide a mechanism
to freeze a device that is causing errors in order to limit the possibility
of propagation of bad data.
There is thus, in HW, a table of PE states that contains a pair of "frozen"
state bits (one for MMIO and one for DMA, they get set together but can be
cleared independently) for each PE.
When a PE is frozen, all stores in any direction are dropped and all loads
return all 1's value. MSIs are also blocked. There's a bit more state that
captures things like the details of the error that caused the freeze etc., but
that's not critical.
The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
are matched to their corresponding PEs.
The following section provides a rough description of what we have on P8
(IODA2). Keep in mind that this is all per PHB (PCI host bridge). Each PHB
is a completely separate HW entity that replicates the entire logic, so has
its own set of PEs, etc.
2. Implementation of Partitionable Endpoints on P8 (IODA2)
P8 supports up to 256 Partitionable Endpoints per PHB.
* Inbound
For DMA, MSIs and inbound PCIe error messages, we have a table (in
memory but accessed in HW by the chip) that provides a direct
correspondence between a PCIe RID (bus/dev/fn) with a PE number.
We call this the RTT.
- For DMA we then provide an entire address space for each PE that can
contain two "windows", depending on the value of PCI address bit 59.
Each window can be configured to be remapped via a "TCE table" (IOMMU
translation table), which has various configurable characteristics
not described here.
- For MSIs, we have two windows in the address space (one at the top of
the 32-bit space and one much higher) which, via a combination of the
address and MSI value, will result in one of the 2048 interrupts per
bridge being triggered. There's a PE# in the interrupt controller
descriptor table as well which is compared with the PE# obtained from
the RTT to "authorize" the device to emit that specific interrupt.
- Error messages just use the RTT.
* Outbound. That's where the tricky part is.
Like other PCI host bridges, the Power8 IODA2 PHB supports "windows"
from the CPU address space to the PCI address space. There is one M32
window and sixteen M64 windows. They have different characteristics.
First what they have in common: they forward a configurable portion of
the CPU address space to the PCIe bus and must be naturally aligned
power of two in size. The rest is different:
- The M32 window:
* Is limited to 4GB in size.
* Drops the top bits of the address (above the size) and replaces
them with a configurable value. This is typically used to generate
32-bit PCIe accesses. We configure that window at boot from FW and
don't touch it from Linux; it's usually set to forward a 2GB
portion of address space from the CPU to PCIe
0x8000_0000..0xffff_ffff. (Note: The top 64KB are actually
reserved for MSIs but this is not a problem at this point; we just
need to ensure Linux doesn't assign anything there, the M32 logic
ignores that however and will forward in that space if we try).
* It is divided into 256 segments of equal size. A table in the chip
maps each segment to a PE#. That allows portions of the MMIO space
to be assigned to PEs on a segment granularity. For a 2GB window,
the segment granularity is 2GB/256 = 8MB.
Now, this is the "main" window we use in Linux today (excluding
SR-IOV). We basically use the trick of forcing the bridge MMIO windows
onto a segment alignment/granularity so that the space behind a bridge
can be assigned to a PE.
Ideally we would like to be able to have individual functions in PEs
but that would mean using a completely different address allocation
scheme where individual function BARs can be "grouped" to fit in one or
more segments.
- The M64 windows:
* Must be at least 256MB in size.
* Do not translate addresses (the address on PCIe is the same as the
address on the PowerBus). There is a way to also set the top 14
bits which are not conveyed by PowerBus but we don't use this.
* Can be configured to be segmented. When not segmented, we can
specify the PE# for the entire window. When segmented, a window
has 256 segments; however, there is no table for mapping a segment
to a PE#. The segment number *is* the PE#.
* Support overlaps. If an address is covered by multiple windows,
there's a defined ordering for which window applies.
We have code (fairly new compared to the M32 stuff) that exploits that
for large BARs in 64-bit space:
We configure an M64 window to cover the entire region of address space
that has been assigned by FW for the PHB (about 64GB, ignore the space
for the M32, it comes out of a different "reserve"). We configure it
as segmented.
Then we do the same thing as with M32, using the bridge alignment
trick, to match to those giant segments.
Since we cannot remap, we have two additional constraints:
- We do the PE# allocation *after* the 64-bit space has been assigned
because the addresses we use directly determine the PE#. We then
update the M32 PE# for the devices that use both 32-bit and 64-bit
spaces or assign the remaining PE# to 32-bit only devices.
- We cannot "group" segments in HW, so if a device ends up using more
than one segment, we end up with more than one PE#. There is a HW
mechanism to make the freeze state cascade to "companion" PEs but
that only works for PCIe error messages (typically used so that if
you freeze a switch, it freezes all its children). So we do it in
SW. We lose a bit of effectiveness of EEH in that case, but that's
the best we found. So when any of the PEs freezes, we freeze the
other ones for that "domain". We thus introduce the concept of
"master PE" which is the one used for DMA, MSIs, etc., and "secondary
PEs" that are used for the remaining M64 segments.
We would like to investigate using additional M64 windows in "single
PE" mode to overlay over specific BARs to work around some of that, for
example for devices with very large BARs, e.g., GPUs. It would make
sense, but we haven't done it yet.
3. Considerations for SR-IOV on PowerKVM
* SR-IOV Background
The PCIe SR-IOV feature allows a single Physical Function (PF) to
support several Virtual Functions (VFs). Registers in the PF's SR-IOV
Capability control the number of VFs and whether they are enabled.
When VFs are enabled, they appear in Configuration Space like normal
PCI devices, but the BARs in VF config space headers are unusual. For
a non-VF device, software uses BARs in the config space header to
discover the BAR sizes and assign addresses for them. For VF devices,
software uses VF BAR registers in the *PF* SR-IOV Capability to
discover sizes and assign addresses. The BARs in the VF's config space
header are read-only zeros.
When a VF BAR in the PF SR-IOV Capability is programmed, it sets the
base address for all the corresponding VF(n) BARs. For example, if the
PF SR-IOV Capability is programmed to enable eight VFs, and it has a
1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.
This region is divided into eight contiguous 1MB regions, each of which
is a BAR0 for one of the VFs. Note that even though the VF BAR
describes an 8MB region, the alignment requirement is for a single VF,
i.e., 1MB in this example.
There are several strategies for isolating VFs in PEs:
- M32 window: There's one M32 window, and it is split into 256
equally-sized segments. The finest granularity possible is a 256MB
window with 1MB segments. VF BARs that are 1MB or larger could be
mapped to separate PEs in this window. Each segment can be
individually mapped to a PE via the lookup table, so this is quite
flexible, but it works best when all the VF BARs are the same size. If
they are different sizes, the entire window has to be small enough that
the segment size matches the smallest VF BAR, which means larger VF
BARs span several segments.
- Non-segmented M64 window: A non-segmented M64 window is mapped entirely
to a single PE, so it could only isolate one VF.
- Single segmented M64 windows: A segmented M64 window could be used just
like the M32 window, but the segments can't be individually mapped to
PEs (the segment number is the PE#), so there isn't as much
flexibility. A VF with multiple BARs would have to be in a "domain" of
multiple PEs, which is not as well isolated as a single PE.
- Multiple segmented M64 windows: As usual, each window is split into 256
equally-sized segments, and the segment number is the PE#. But if we
use several M64 windows, they can be set to different base addresses
and different segment sizes. If we have VFs that each have a 1MB BAR
and a 32MB BAR, we could use one M64 window to assign 1MB segments and
another M64 window to assign 32MB segments.
Finally, the plan to use M64 windows for SR-IOV, which will be described
more in the next two sections. For a given VF BAR, we need to
effectively reserve the entire 256 segments (256 * VF BAR size) and
position the VF BAR to start at the beginning of a free range of
segments/PEs inside that M64 window.
The goal is of course to be able to give a separate PE for each VF.
The IODA2 platform has 16 M64 windows, which are used to map MMIO
range to PE#. Each M64 window defines one MMIO range and this range is
divided into 256 segments, with each segment corresponding to one PE.
We decide to leverage this M64 window to map VFs to individual PEs, since
SR-IOV VF BARs are all the same size.
But doing so introduces another problem: total_VFs is usually smaller
than the number of M64 window segments, so if we map one VF BAR directly
to one M64 window, some part of the M64 window will map to another
device's MMIO range.
IODA supports 256 PEs, so segmented windows contain 256 segments, so if
total_VFs is less than 256, we have the situation in Figure 1.0, where
segments [total_VFs, 255] of the M64 window may map to some MMIO range on
other devices:
0 1 total_VFs - 1
+------+------+- -+------+------+
| | | ... | | |
+------+------+- -+------+------+
VF(n) BAR space
0 1 total_VFs - 1 255
+------+------+- -+------+------+- -+------+------+
| | | ... | | | ... | | |
+------+------+- -+------+------+- -+------+------+
M64 window
Figure 1.0 Direct map VF(n) BAR space
Our current solution is to allocate 256 segments even if the VF(n) BAR
space doesn't need that much, as shown in Figure 1.1:
0 1 total_VFs - 1 255
+------+------+- -+------+------+- -+------+------+
| | | ... | | | ... | | |
+------+------+- -+------+------+- -+------+------+
VF(n) BAR space + extra
0 1 total_VFs - 1 255
+------+------+- -+------+------+- -+------+------+
| | | ... | | | ... | | |
+------+------+- -+------+------+- -+------+------+
M64 window
Figure 1.1 Map VF(n) BAR space + extra
Allocating the extra space ensures that the entire M64 window will be
assigned to this one SR-IOV device and none of the space will be
available for other devices. Note that this only expands the space
reserved in software; there are still only total_VFs VFs, and they only
respond to segments [0, total_VFs - 1]. There's nothing in hardware that
responds to segments [total_VFs, 255].
4. Implications for the Generic PCI Code
The PCIe SR-IOV spec requires that the base of the VF(n) BAR space be
aligned to the size of an individual VF BAR.
In IODA2, the MMIO address determines the PE#. If the address is in an M32
window, we can set the PE# by updating the table that translates segments
to PE#s. Similarly, if the address is in an unsegmented M64 window, we can
set the PE# for the window. But if it's in a segmented M64 window, the
segment number is the PE#.
Therefore, the only way to control the PE# for a VF is to change the base
of the VF(n) BAR space in the VF BAR. If the PCI core allocates the exact
amount of space required for the VF(n) BAR space, the VF BAR value is fixed
and cannot be changed.
On the other hand, if the PCI core allocates additional space, the VF BAR
value can be changed as long as the entire VF(n) BAR space remains inside
the space allocated by the core.
Ideally the segment size will be the same as an individual VF BAR size.
Then each VF will be in its own PE. The VF BARs (and therefore the PE#s)
are contiguous. If VF0 is in PE(x), then VF(n) is in PE(x+n). If we
allocate 256 segments, there are (256 - numVFs) choices for the PE# of VF0.
If the segment size is smaller than the VF BAR size, it will take several
segments to cover a VF BAR, and a VF will be in several PEs. This is
possible, but the isolation isn't as good, and it reduces the number of PE#
choices because instead of consuming only numVFs segments, the VF(n) BAR
space will consume (numVFs * n) segments. That means there aren't as many
available segments for adjusting base of the VF(n) BAR space.

36
Documentation/powerpc/transactional_memory.txt
View File

@ -74,22 +74,23 @@ Causes of transaction aborts
Syscalls
========
Performing syscalls from within transaction is not recommended, and can lead
to unpredictable results.
Syscalls made from within an active transaction will not be performed and the
transaction will be doomed by the kernel with the failure code TM_CAUSE_SYSCALL
| TM_CAUSE_PERSISTENT.
Syscalls do not by design abort transactions, but beware: The kernel code will
not be running in transactional state. The effect of syscalls will always
remain visible, but depending on the call they may abort your transaction as a
side-effect, read soon-to-be-aborted transactional data that should not remain
invisible, etc. If you constantly retry a transaction that constantly aborts
itself by calling a syscall, you'll have a livelock & make no progress.
Syscalls made from within a suspended transaction are performed as normal and
the transaction is not explicitly doomed by the kernel. However, what the
kernel does to perform the syscall may result in the transaction being doomed
by the hardware. The syscall is performed in suspended mode so any side
effects will be persistent, independent of transaction success or failure. No
guarantees are provided by the kernel about which syscalls will affect
transaction success.
Simple syscalls (e.g. sigprocmask()) "could" be OK. Even things like write()
from, say, printf() should be OK as long as the kernel does not access any
memory that was accessed transactionally.
Consider any syscalls that happen to work as debug-only -- not recommended for
production use. Best to queue them up till after the transaction is over.
Care must be taken when relying on syscalls to abort during active transactions
if the calls are made via a library. Libraries may cache values (which may
give the appearance of success) or perform operations that cause transaction
failure before entering the kernel (which may produce different failure codes).
Examples are glibc's getpid() and lazy symbol resolution.
Signals
@ -174,10 +175,9 @@ These are defined in <asm/reg.h>, and distinguish different reasons why the
kernel aborted a transaction:
TM_CAUSE_RESCHED Thread was rescheduled.
TM_CAUSE_TLBI Software TLB invalide.
TM_CAUSE_TLBI Software TLB invalid.
TM_CAUSE_FAC_UNAV FP/VEC/VSX unavailable trap.
TM_CAUSE_SYSCALL Currently unused; future syscalls that must abort
transactions for consistency will use this.
TM_CAUSE_SYSCALL Syscall from active transaction.
TM_CAUSE_SIGNAL Signal delivered.
TM_CAUSE_MISC Currently unused.
TM_CAUSE_ALIGNMENT Alignment fault.
@ -185,7 +185,7 @@ kernel aborted a transaction:
These can be checked by the user program's abort handler as TEXASR[0:7]. If
bit 7 is set, it indicates that the error is consider persistent. For example
a TM_CAUSE_ALIGNMENT will be persistent while a TM_CAUSE_RESCHED will not.q
a TM_CAUSE_ALIGNMENT will be persistent while a TM_CAUSE_RESCHED will not.
GDB
===

2
arch/Kconfig
View File

@ -32,7 +32,7 @@ config HAVE_OPROFILE
config OPROFILE_NMI_TIMER
def_bool y
depends on PERF_EVENTS && HAVE_PERF_EVENTS_NMI
depends on PERF_EVENTS && HAVE_PERF_EVENTS_NMI && !PPC64
config KPROBES
bool "Kprobes"

4
arch/powerpc/Kconfig
View File

@ -152,6 +152,7 @@ config PPC
select DCACHE_WORD_ACCESS if PPC64 && CPU_LITTLE_ENDIAN
select NO_BOOTMEM
select HAVE_GENERIC_RCU_GUP
select HAVE_PERF_EVENTS_NMI if PPC64
config GENERIC_CSUM
def_bool CPU_LITTLE_ENDIAN
@ -189,9 +190,6 @@ config ARCH_MAY_HAVE_PC_FDC
bool
default PCI
config PPC_OF
def_bool y
config PPC_UDBG_16550
bool
default n

9
arch/powerpc/Kconfig.debug
View File

@ -117,7 +117,7 @@ config BDI_SWITCH
config BOOTX_TEXT
bool "Support for early boot text console (BootX or OpenFirmware only)"
depends on PPC_OF && PPC_BOOK3S
depends on PPC_BOOK3S
help
Say Y here to see progress messages from the boot firmware in text
mode. Requires either BootX or Open Firmware.
@ -193,13 +193,6 @@ config PPC_EARLY_DEBUG_PAS_REALMODE
Select this to enable early debugging for PA Semi.
Output will be on UART0.
config PPC_EARLY_DEBUG_BEAT
bool "Beat HV Console"
depends on PPC_CELLEB
select PPC_UDBG_BEAT
help
Select this to enable early debugging for Celleb with Beat.
config PPC_EARLY_DEBUG_44x
bool "Early serial debugging for IBM/AMCC 44x CPUs"
depends on 44x

4
arch/powerpc/Makefile
View File

@ -248,10 +248,10 @@ boot := arch/$(ARCH)/boot
ifeq ($(CONFIG_RELOCATABLE),y)
quiet_cmd_relocs_check = CALL $<
cmd_relocs_check = perl $< "$(OBJDUMP)" "$(obj)/vmlinux"
cmd_relocs_check = $(CONFIG_SHELL) $< "$(OBJDUMP)" "$(obj)/vmlinux"
PHONY += relocs_check
relocs_check: arch/powerpc/relocs_check.pl vmlinux
relocs_check: arch/powerpc/relocs_check.sh vmlinux
$(call cmd,relocs_check)
zImage: relocs_check

4
arch/powerpc/boot/Makefile
View File

@ -110,7 +110,6 @@ src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S
src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
src-wlib := $(sort $(src-wlib-y))
@ -215,7 +214,6 @@ image-$(CONFIG_PPC_POWERNV) += zImage.pseries
image-$(CONFIG_PPC_MAPLE) += zImage.maple
image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
image-$(CONFIG_PPC_PS3) += dtbImage.ps3
image-$(CONFIG_PPC_CELLEB) += zImage.pseries
image-$(CONFIG_PPC_CELL_QPACE) += zImage.pseries
image-$(CONFIG_PPC_CHRP) += zImage.chrp
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
@ -317,7 +315,7 @@ endif
# Allow extra targets to be added to the defconfig
image-y += $(subst ",,$(CONFIG_EXTRA_TARGETS))
initrd- := $(patsubst zImage%, zImage.initrd%, $(image-n) $(image-))
initrd- := $(patsubst zImage%, zImage.initrd%, $(image-))
initrd-y := $(patsubst zImage%, zImage.initrd%, \
$(patsubst dtbImage%, dtbImage.initrd%, \
$(patsubst simpleImage%, simpleImage.initrd%, \

26
arch/powerpc/boot/crt0.S
View File

@ -155,29 +155,29 @@ p_base: mflr r10 /* r10 now points to runtime addr of p_base */
ld r9,(p_rela-p_base)(r10)
add r9,r9,r10
li r7,0
li r13,0
li r8,0
9: ld r6,0(r11) /* get tag */
cmpdi r6,0
9: ld r12,0(r11) /* get tag */
cmpdi r12,0
beq 12f /* end of list */
cmpdi r6,RELA
cmpdi r12,RELA
bne 10f
ld r7,8(r11) /* get RELA pointer in r7 */
ld r13,8(r11) /* get RELA pointer in r13 */
b 11f
10: addis r6,r6,(-RELACOUNT)@ha
cmpdi r6,RELACOUNT@l
10: addis r12,r12,(-RELACOUNT)@ha
cmpdi r12,RELACOUNT@l
bne 11f
ld r8,8(r11) /* get RELACOUNT value in r8 */
11: addi r11,r11,16
b 9b
12:
cmpdi r7,0 /* check we have both RELA and RELACOUNT */
cmpdi r13,0 /* check we have both RELA and RELACOUNT */
cmpdi cr1,r8,0
beq 3f
beq cr1,3f
/* Calcuate the runtime offset. */
subf r7,r7,r9
subf r13,r13,r9
/* Run through the list of relocations and process the
* R_PPC64_RELATIVE ones. */
@ -185,10 +185,10 @@ p_base: mflr r10 /* r10 now points to runtime addr of p_base */
13: ld r0,8(r9) /* ELF64_R_TYPE(reloc->r_info) */
cmpdi r0,22 /* R_PPC64_RELATIVE */
bne 3f
ld r6,0(r9) /* reloc->r_offset */
ld r12,0(r9) /* reloc->r_offset */
ld r0,16(r9) /* reloc->r_addend */
add r0,r0,r7
stdx r0,r7,r6
add r0,r0,r13
stdx r0,r13,r12
addi r9,r9,24
bdnz 13b
@ -218,7 +218,7 @@ p_base: mflr r10 /* r10 now points to runtime addr of p_base */
beq 6f
ld r1,0(r8)
li r0,0
stdu r0,-16(r1) /* establish a stack frame */
stdu r0,-112(r1) /* establish a stack frame */
6:
#endif /* __powerpc64__ */
/* Call platform_init() */

223
arch/powerpc/boot/dts/b4860emu.dts
View File

@ -1,223 +0,0 @@
/*
* B4860 emulator Device Tree Source
*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* This software is provided by Freescale Semiconductor "as is" and any
* express or implied warranties, including, but not limited to, the implied
* warranties of merchantability and fitness for a particular purpose are
* disclaimed. In no event shall Freescale Semiconductor be liable for any
* direct, indirect, incidental, special, exemplary, or consequential damages
* (including, but not limited to, procurement of substitute goods or services;
* loss of use, data, or profits; or business interruption) however caused and
* on any theory of liability, whether in contract, strict liability, or tort
* (including negligence or otherwise) arising in any way out of the use of
* this software, even if advised of the possibility of such damage.
*/
/dts-v1/;
/include/ "fsl/e6500_power_isa.dtsi"
/ {
compatible = "fsl,B4860";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
ccsr = &soc;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
dma0 = &dma0;
dma1 = &dma1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
next-level-cache = <&L2>;
fsl,portid-mapping = <0x80000000>;
};
};
};
/ {
model = "fsl,B4860QDS";
compatible = "fsl,B4860EMU", "fsl,B4860QDS";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
2 0 0xf 0xff800000 0x00010000
3 0 0xf 0xffdf0000 0x00008000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
};
memory {
device_type = "memory";
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,ifc", "simple-bus";
interrupts = <25 2 0 0>;
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
soc-sram-error {
compatible = "fsl,soc-sram-error";
interrupts = <16 2 1 2>;
};
corenet-law@0 {
compatible = "fsl,corenet-law";
reg = <0x0 0x1000>;
fsl,num-laws = <32>;
};
ddr1: memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 8>;
};
ddr2: memory-controller@9000 {
compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
reg = <0x9000 0x1000>;
interrupts = <16 2 1 9>;
};
cpc: l3-cache-controller@10000 {
compatible = "fsl,b4-l3-cache-controller", "cache";
reg = <0x10000 0x1000
0x11000 0x1000>;
interrupts = <16 2 1 4>;
};
corenet-cf@18000 {
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 0>;
fsl,ccf-num-csdids = <32>;
fsl,ccf-num-snoopids = <32>;
};
iommu@20000 {
compatible = "fsl,pamu-v1.0", "fsl,pamu";
reg = <0x20000 0x4000>;
fsl,portid-mapping = <0x8000>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <
24 2 0 0
16 2 1 1>;
pamu0: pamu@0 {
reg = <0 0x1000>;
fsl,primary-cache-geometry = <8 1>;
fsl,secondary-cache-geometry = <32 2>;
};
};
/include/ "fsl/qoriq-mpic.dtsi"
guts: global-utilities@e0000 {
compatible = "fsl,b4-device-config";
reg = <0xe0000 0xe00>;
fsl,has-rstcr;
fsl,liodn-bits = <12>;
};
/include/ "fsl/qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
};
/include/ "fsl/qoriq-dma-0.dtsi"
dma@100300 {
fsl,iommu-parent = <&pamu0>;
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
};
/include/ "fsl/qoriq-dma-1.dtsi"
dma@101300 {
fsl,iommu-parent = <&pamu0>;
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
};
/include/ "fsl/qoriq-i2c-0.dtsi"
/include/ "fsl/qoriq-i2c-1.dtsi"
/include/ "fsl/qoriq-duart-0.dtsi"
/include/ "fsl/qoriq-duart-1.dtsi"
L2: l2-cache-controller@c20000 {
compatible = "fsl,b4-l2-cache-controller";
reg = <0xc20000 0x1000>;
next-level-cache = <&cpc>;
};
};

17
arch/powerpc/boot/dts/b4qds.dtsi
View File

@ -1,7 +1,7 @@
/*
* B4420DS Device Tree Source
*
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2012 - 2014 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -97,10 +97,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01052000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x2000000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

60
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* B4860 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2012 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -109,6 +109,64 @@
};
};
&bportals {
bman-portal@38000 {
compatible = "fsl,bman-portal";
reg = <0x38000 0x4000>, <0x100e000 0x1000>;
interrupts = <133 2 0 0>;
};
bman-portal@3c000 {
compatible = "fsl,bman-portal";
reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
interrupts = <135 2 0 0>;
};
bman-portal@40000 {
compatible = "fsl,bman-portal";
reg = <0x40000 0x4000>, <0x1010000 0x1000>;
interrupts = <137 2 0 0>;
};
bman-portal@44000 {
compatible = "fsl,bman-portal";
reg = <0x44000 0x4000>, <0x1011000 0x1000>;
interrupts = <139 2 0 0>;
};
bman-portal@48000 {
compatible = "fsl,bman-portal";
reg = <0x48000 0x4000>, <0x1012000 0x1000>;
interrupts = <141 2 0 0>;
};
bman-portal@4c000 {
compatible = "fsl,bman-portal";
reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
interrupts = <143 2 0 0>;
};
bman-portal@50000 {
compatible = "fsl,bman-portal";
reg = <0x50000 0x4000>, <0x1014000 0x1000>;
interrupts = <145 2 0 0>;
};
bman-portal@54000 {
compatible = "fsl,bman-portal";
reg = <0x54000 0x4000>, <0x1015000 0x1000>;
interrupts = <147 2 0 0>;
};
bman-portal@58000 {
compatible = "fsl,bman-portal";
reg = <0x58000 0x4000>, <0x1016000 0x1000>;
interrupts = <149 2 0 0>;
};
bman-portal@5c000 {
compatible = "fsl,bman-portal";
reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
interrupts = <151 2 0 0>;
};
bman-portal@60000 {
compatible = "fsl,bman-portal";
reg = <0x60000 0x4000>, <0x1018000 0x1000>;
interrupts = <153 2 0 0>;
};
};
&soc {
ddr2: memory-controller@9000 {
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";

89
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* B4420 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2012 - 2014 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* this software, even if advised of the possibility of such damage.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
@ -128,6 +133,83 @@
};
};
&bportals {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
bman-portal@0 {
compatible = "fsl,bman-portal";
reg = <0x0 0x4000>, <0x1000000 0x1000>;
interrupts = <105 2 0 0>;
};
bman-portal@4000 {
compatible = "fsl,bman-portal";
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
interrupts = <107 2 0 0>;
};
bman-portal@8000 {
compatible = "fsl,bman-portal";
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
interrupts = <109 2 0 0>;
};
bman-portal@c000 {
compatible = "fsl,bman-portal";
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
interrupts = <111 2 0 0>;
};
bman-portal@10000 {
compatible = "fsl,bman-portal";
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
interrupts = <113 2 0 0>;
};
bman-portal@14000 {
compatible = "fsl,bman-portal";
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
interrupts = <115 2 0 0>;
};
bman-portal@18000 {
compatible = "fsl,bman-portal";
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
interrupts = <117 2 0 0>;
};
bman-portal@1c000 {
compatible = "fsl,bman-portal";
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
interrupts = <119 2 0 0>;
};
bman-portal@20000 {
compatible = "fsl,bman-portal";
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
interrupts = <121 2 0 0>;
};
bman-portal@24000 {
compatible = "fsl,bman-portal";
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
interrupts = <123 2 0 0>;
};
bman-portal@28000 {
compatible = "fsl,bman-portal";
reg = <0x28000 0x4000>, <0x100a000 0x1000>;
interrupts = <125 2 0 0>;
};
bman-portal@2c000 {
compatible = "fsl,bman-portal";
reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
interrupts = <127 2 0 0>;
};
bman-portal@30000 {
compatible = "fsl,bman-portal";
reg = <0x30000 0x4000>, <0x100c000 0x1000>;
interrupts = <129 2 0 0>;
};
bman-portal@34000 {
compatible = "fsl,bman-portal";
reg = <0x34000 0x4000>, <0x100d000 0x1000>;
interrupts = <131 2 0 0>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -261,6 +343,11 @@
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-sec5.3-0.dtsi"
/include/ "qoriq-bman1.dtsi"
bman: bman@31a000 {
interrupts = <16 2 1 29>;
};
L2: l2-cache-controller@c20000 {
compatible = "fsl,b4-l2-cache-controller";
reg = <0xc20000 0x1000>;

37
arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* P1023/P1017 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10 0>;
};
&lbc {
#address-cells = <2>;
#size-cells = <1>;
@ -97,6 +102,28 @@
};
};
&bportals {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
bman-portal@0 {
compatible = "fsl,bman-portal";
reg = <0x0 0x4000>, <0x100000 0x1000>;
interrupts = <30 2 0 0>;
};
bman-portal@4000 {
compatible = "fsl,bman-portal";
reg = <0x4000 0x4000>, <0x101000 0x1000>;
interrupts = <32 2 0 0>;
};
bman-portal@8000 {
compatible = "fsl,bman-portal";
reg = <0x8000 0x4000>, <0x102000 0x1000>;
interrupts = <34 2 0 0>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -221,6 +248,14 @@
/include/ "pq3-mpic.dtsi"
/include/ "pq3-mpic-timer-B.dtsi"
bman: bman@8a000 {
compatible = "fsl,bman";
reg = <0x8a000 0x1000>;
interrupts = <16 2 0 0>;
fsl,bman-portals = <&bportals>;
memory-region = <&bman_fbpr>;
};
global-utilities@e0000 {
compatible = "fsl,p1023-guts";
reg = <0xe0000 0x1000>;

11
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* P2041/P2040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10 0>;
};
&lbc {
compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
interrupts = <25 2 0 0>;
@ -216,6 +221,8 @@
};
};
/include/ "qoriq-bman1-portals.dtsi"
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -407,4 +414,6 @@
crypto: crypto@300000 {
fsl,iommu-parent = <&pamu1>;
};
/include/ "qoriq-bman1.dtsi"
};

11
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* P3041 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10 0>;
};
&lbc {
compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
interrupts = <25 2 0 0>;
@ -243,6 +248,8 @@
};
};
/include/ "qoriq-bman1-portals.dtsi"
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -434,4 +441,6 @@
crypto: crypto@300000 {
fsl,iommu-parent = <&pamu1>;
};
/include/ "qoriq-bman1.dtsi"
};

11
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* P4080/P4040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10 0>;
};
&lbc {
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
interrupts = <25 2 0 0>;
@ -243,6 +248,8 @@
};
/include/ "qoriq-bman1-portals.dtsi"
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -490,4 +497,6 @@
crypto: crypto@300000 {
fsl,iommu-parent = <&pamu1>;
};
/include/ "qoriq-bman1.dtsi"
};

11
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* P5020/5010 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&lbc {
compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
interrupts = <25 2 0 0>;
@ -240,6 +245,8 @@
};
};
/include/ "qoriq-bman1-portals.dtsi"
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -421,6 +428,8 @@
fsl,iommu-parent = <&pamu1>;
};
/include/ "qoriq-bman1.dtsi"
/include/ "qoriq-raid1.0-0.dtsi"
raideng@320000 {
fsl,iommu-parent = <&pamu1>;

11
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* P5040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2012 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* software, even if advised of the possibility of such damage.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&lbc {
compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
interrupts = <25 2 0 0>;
@ -195,6 +200,8 @@
};
};
/include/ "qoriq-bman1-portals.dtsi"
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -399,4 +406,6 @@
crypto@300000 {
fsl,iommu-parent = <&pamu4>;
};
/include/ "qoriq-bman1.dtsi"
};

65
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* T1040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
@ -218,6 +223,63 @@
};
};
&bportals {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
bman-portal@0 {
compatible = "fsl,bman-portal";
reg = <0x0 0x4000>, <0x1000000 0x1000>;
interrupts = <105 2 0 0>;
};
bman-portal@4000 {
compatible = "fsl,bman-portal";
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
interrupts = <107 2 0 0>;
};
bman-portal@8000 {
compatible = "fsl,bman-portal";
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
interrupts = <109 2 0 0>;
};
bman-portal@c000 {
compatible = "fsl,bman-portal";
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
interrupts = <111 2 0 0>;
};
bman-portal@10000 {
compatible = "fsl,bman-portal";
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
interrupts = <113 2 0 0>;
};
bman-portal@14000 {
compatible = "fsl,bman-portal";
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
interrupts = <115 2 0 0>;
};
bman-portal@18000 {
compatible = "fsl,bman-portal";
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
interrupts = <117 2 0 0>;
};
bman-portal@1c000 {
compatible = "fsl,bman-portal";
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
interrupts = <119 2 0 0>;
};
bman-portal@20000 {
compatible = "fsl,bman-portal";
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
interrupts = <121 2 0 0>;
};
bman-portal@24000 {
compatible = "fsl,bman-portal";
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
interrupts = <123 2 0 0>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -401,4 +463,5 @@
fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
};
/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-bman1.dtsi"
};

105
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* T2081 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
@ -224,6 +229,103 @@
};
};
&bportals {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
bman-portal@0 {
compatible = "fsl,bman-portal";
reg = <0x0 0x4000>, <0x1000000 0x1000>;
interrupts = <105 2 0 0>;
};
bman-portal@4000 {
compatible = "fsl,bman-portal";
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
interrupts = <107 2 0 0>;
};
bman-portal@8000 {
compatible = "fsl,bman-portal";
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
interrupts = <109 2 0 0>;
};
bman-portal@c000 {
compatible = "fsl,bman-portal";
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
interrupts = <111 2 0 0>;
};
bman-portal@10000 {
compatible = "fsl,bman-portal";
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
interrupts = <113 2 0 0>;
};
bman-portal@14000 {
compatible = "fsl,bman-portal";
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
interrupts = <115 2 0 0>;
};
bman-portal@18000 {
compatible = "fsl,bman-portal";
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
interrupts = <117 2 0 0>;
};
bman-portal@1c000 {
compatible = "fsl,bman-portal";
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
interrupts = <119 2 0 0>;
};
bman-portal@20000 {
compatible = "fsl,bman-portal";
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
interrupts = <121 2 0 0>;
};
bman-portal@24000 {
compatible = "fsl,bman-portal";
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
interrupts = <123 2 0 0>;
};
bman-portal@28000 {
compatible = "fsl,bman-portal";
reg = <0x28000 0x4000>, <0x100a000 0x1000>;
interrupts = <125 2 0 0>;
};
bman-portal@2c000 {
compatible = "fsl,bman-portal";
reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
interrupts = <127 2 0 0>;
};
bman-portal@30000 {
compatible = "fsl,bman-portal";
reg = <0x30000 0x4000>, <0x100c000 0x1000>;
interrupts = <129 2 0 0>;
};
bman-portal@34000 {
compatible = "fsl,bman-portal";
reg = <0x34000 0x4000>, <0x100d000 0x1000>;
interrupts = <131 2 0 0>;
};
bman-portal@38000 {
compatible = "fsl,bman-portal";
reg = <0x38000 0x4000>, <0x100e000 0x1000>;
interrupts = <133 2 0 0>;
};
bman-portal@3c000 {
compatible = "fsl,bman-portal";
reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
interrupts = <135 2 0 0>;
};
bman-portal@40000 {
compatible = "fsl,bman-portal";
reg = <0x40000 0x4000>, <0x1010000 0x1000>;
interrupts = <137 2 0 0>;
};
bman-portal@44000 {
compatible = "fsl,bman-portal";
reg = <0x44000 0x4000>, <0x1011000 0x1000>;
interrupts = <139 2 0 0>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -400,6 +502,7 @@
phy_type = "utmi";
};
/include/ "qoriq-sec5.2-0.dtsi"
/include/ "qoriq-bman1.dtsi"
L2_1: l2-cache-controller@c20000 {
/* Cluster 0 L2 cache */

265
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
View File

@ -1,7 +1,7 @@
/*
* T4240 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2012 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&bman_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x10000 0>;
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
@ -294,6 +299,263 @@
};
};
&bportals {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
bman-portal@0 {
compatible = "fsl,bman-portal";
reg = <0x0 0x4000>, <0x1000000 0x1000>;
interrupts = <105 2 0 0>;
};
bman-portal@4000 {
compatible = "fsl,bman-portal";
reg = <0x4000 0x4000>, <0x1001000 0x1000>;
interrupts = <107 2 0 0>;
};
bman-portal@8000 {
compatible = "fsl,bman-portal";
reg = <0x8000 0x4000>, <0x1002000 0x1000>;
interrupts = <109 2 0 0>;
};
bman-portal@c000 {
compatible = "fsl,bman-portal";
reg = <0xc000 0x4000>, <0x1003000 0x1000>;
interrupts = <111 2 0 0>;
};
bman-portal@10000 {
compatible = "fsl,bman-portal";
reg = <0x10000 0x4000>, <0x1004000 0x1000>;
interrupts = <113 2 0 0>;
};
bman-portal@14000 {
compatible = "fsl,bman-portal";
reg = <0x14000 0x4000>, <0x1005000 0x1000>;
interrupts = <115 2 0 0>;
};
bman-portal@18000 {
compatible = "fsl,bman-portal";
reg = <0x18000 0x4000>, <0x1006000 0x1000>;
interrupts = <117 2 0 0>;
};
bman-portal@1c000 {
compatible = "fsl,bman-portal";
reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
interrupts = <119 2 0 0>;
};
bman-portal@20000 {
compatible = "fsl,bman-portal";
reg = <0x20000 0x4000>, <0x1008000 0x1000>;
interrupts = <121 2 0 0>;
};
bman-portal@24000 {
compatible = "fsl,bman-portal";
reg = <0x24000 0x4000>, <0x1009000 0x1000>;
interrupts = <123 2 0 0>;
};
bman-portal@28000 {
compatible = "fsl,bman-portal";
reg = <0x28000 0x4000>, <0x100a000 0x1000>;
interrupts = <125 2 0 0>;
};
bman-portal@2c000 {
compatible = "fsl,bman-portal";
reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
interrupts = <127 2 0 0>;
};
bman-portal@30000 {
compatible = "fsl,bman-portal";
reg = <0x30000 0x4000>, <0x100c000 0x1000>;
interrupts = <129 2 0 0>;
};
bman-portal@34000 {
compatible = "fsl,bman-portal";
reg = <0x34000 0x4000>, <0x100d000 0x1000>;
interrupts = <131 2 0 0>;
};
bman-portal@38000 {
compatible = "fsl,bman-portal";
reg = <0x38000 0x4000>, <0x100e000 0x1000>;
interrupts = <133 2 0 0>;
};
bman-portal@3c000 {
compatible = "fsl,bman-portal";
reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
interrupts = <135 2 0 0>;
};
bman-portal@40000 {
compatible = "fsl,bman-portal";
reg = <0x40000 0x4000>, <0x1010000 0x1000>;
interrupts = <137 2 0 0>;
};
bman-portal@44000 {
compatible = "fsl,bman-portal";
reg = <0x44000 0x4000>, <0x1011000 0x1000>;
interrupts = <139 2 0 0>;
};
bman-portal@48000 {
compatible = "fsl,bman-portal";
reg = <0x48000 0x4000>, <0x1012000 0x1000>;
interrupts = <141 2 0 0>;
};
bman-portal@4c000 {
compatible = "fsl,bman-portal";
reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
interrupts = <143 2 0 0>;
};
bman-portal@50000 {
compatible = "fsl,bman-portal";
reg = <0x50000 0x4000>, <0x1014000 0x1000>;
interrupts = <145 2 0 0>;
};
bman-portal@54000 {
compatible = "fsl,bman-portal";
reg = <0x54000 0x4000>, <0x1015000 0x1000>;
interrupts = <147 2 0 0>;
};
bman-portal@58000 {
compatible = "fsl,bman-portal";
reg = <0x58000 0x4000>, <0x1016000 0x1000>;
interrupts = <149 2 0 0>;
};
bman-portal@5c000 {
compatible = "fsl,bman-portal";
reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
interrupts = <151 2 0 0>;
};
bman-portal@60000 {
compatible = "fsl,bman-portal";
reg = <0x60000 0x4000>, <0x1018000 0x1000>;
interrupts = <153 2 0 0>;
};
bman-portal@64000 {
compatible = "fsl,bman-portal";
reg = <0x64000 0x4000>, <0x1019000 0x1000>;
interrupts = <155 2 0 0>;
};
bman-portal@68000 {
compatible = "fsl,bman-portal";
reg = <0x68000 0x4000>, <0x101a000 0x1000>;
interrupts = <157 2 0 0>;
};
bman-portal@6c000 {
compatible = "fsl,bman-portal";
reg = <0x6c000 0x4000>, <0x101b000 0x1000>;
interrupts = <159 2 0 0>;
};
bman-portal@70000 {
compatible = "fsl,bman-portal";
reg = <0x70000 0x4000>, <0x101c000 0x1000>;
interrupts = <161 2 0 0>;
};
bman-portal@74000 {
compatible = "fsl,bman-portal";
reg = <0x74000 0x4000>, <0x101d000 0x1000>;
interrupts = <163 2 0 0>;
};
bman-portal@78000 {
compatible = "fsl,bman-portal";
reg = <0x78000 0x4000>, <0x101e000 0x1000>;
interrupts = <165 2 0 0>;
};
bman-portal@7c000 {
compatible = "fsl,bman-portal";
reg = <0x7c000 0x4000>, <0x101f000 0x1000>;
interrupts = <167 2 0 0>;
};
bman-portal@80000 {
compatible = "fsl,bman-portal";
reg = <0x80000 0x4000>, <0x1020000 0x1000>;
interrupts = <169 2 0 0>;
};
bman-portal@84000 {
compatible = "fsl,bman-portal";
reg = <0x84000 0x4000>, <0x1021000 0x1000>;
interrupts = <171 2 0 0>;
};
bman-portal@88000 {
compatible = "fsl,bman-portal";
reg = <0x88000 0x4000>, <0x1022000 0x1000>;
interrupts = <173 2 0 0>;
};
bman-portal@8c000 {
compatible = "fsl,bman-portal";
reg = <0x8c000 0x4000>, <0x1023000 0x1000>;
interrupts = <175 2 0 0>;
};
bman-portal@90000 {
compatible = "fsl,bman-portal";
reg = <0x90000 0x4000>, <0x1024000 0x1000>;
interrupts = <385 2 0 0>;
};
bman-portal@94000 {
compatible = "fsl,bman-portal";
reg = <0x94000 0x4000>, <0x1025000 0x1000>;
interrupts = <387 2 0 0>;
};
bman-portal@98000 {
compatible = "fsl,bman-portal";
reg = <0x98000 0x4000>, <0x1026000 0x1000>;
interrupts = <389 2 0 0>;
};
bman-portal@9c000 {
compatible = "fsl,bman-portal";
reg = <0x9c000 0x4000>, <0x1027000 0x1000>;
interrupts = <391 2 0 0>;
};
bman-portal@a0000 {
compatible = "fsl,bman-portal";
reg = <0xa0000 0x4000>, <0x1028000 0x1000>;
interrupts = <393 2 0 0>;
};
bman-portal@a4000 {
compatible = "fsl,bman-portal";
reg = <0xa4000 0x4000>, <0x1029000 0x1000>;
interrupts = <395 2 0 0>;
};
bman-portal@a8000 {
compatible = "fsl,bman-portal";
reg = <0xa8000 0x4000>, <0x102a000 0x1000>;
interrupts = <397 2 0 0>;
};
bman-portal@ac000 {
compatible = "fsl,bman-portal";
reg = <0xac000 0x4000>, <0x102b000 0x1000>;
interrupts = <399 2 0 0>;
};
bman-portal@b0000 {
compatible = "fsl,bman-portal";
reg = <0xb0000 0x4000>, <0x102c000 0x1000>;
interrupts = <401 2 0 0>;
};
bman-portal@b4000 {
compatible = "fsl,bman-portal";
reg = <0xb4000 0x4000>, <0x102d000 0x1000>;
interrupts = <403 2 0 0>;
};
bman-portal@b8000 {
compatible = "fsl,bman-portal";
reg = <0xb8000 0x4000>, <0x102e000 0x1000>;
interrupts = <405 2 0 0>;
};
bman-portal@bc000 {
compatible = "fsl,bman-portal";
reg = <0xbc000 0x4000>, <0x102f000 0x1000>;
interrupts = <407 2 0 0>;
};
bman-portal@c0000 {
compatible = "fsl,bman-portal";
reg = <0xc0000 0x4000>, <0x1030000 0x1000>;
interrupts = <409 2 0 0>;
};
bman-portal@c4000 {
compatible = "fsl,bman-portal";
reg = <0xc4000 0x4000>, <0x1031000 0x1000>;
interrupts = <411 2 0 0>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
@ -486,6 +748,7 @@
/include/ "qoriq-sata2-0.dtsi"
/include/ "qoriq-sata2-1.dtsi"
/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-bman1.dtsi"
L2_1: l2-cache-controller@c20000 {
compatible = "fsl,t4240-l2-cache-controller";

15
arch/powerpc/boot/dts/kmcoge4.dts
View File

@ -25,10 +25,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x200000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

15
arch/powerpc/boot/dts/oca4080.dts
View File

@ -49,10 +49,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x200000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

18
arch/powerpc/boot/dts/p1023rdb.dts
View File

@ -1,7 +1,7 @@
/*
* P1023 RDB Device Tree Source
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
*
* Author: Chunhe Lan <Chunhe.Lan@freescale.com>
*
@ -47,6 +47,21 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
bportals: bman-portals@ff200000 {
ranges = <0x0 0xf 0xff200000 0x200000>;
};
soc: soc@ff600000 {
ranges = <0x0 0x0 0xff600000 0x200000>;
@ -228,7 +243,6 @@
0x0 0x100000>;
};
};
};
/include/ "fsl/p1023si-post.dtsi"

17
arch/powerpc/boot/dts/p2041rdb.dts
View File

@ -1,7 +1,7 @@
/*
* P2041RDB Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -45,10 +45,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x200000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

17
arch/powerpc/boot/dts/p3041ds.dts
View File

@ -1,7 +1,7 @@
/*
* P3041DS Device Tree Source
*
* Copyright 2010-2011 Freescale Semiconductor Inc.
* Copyright 2010 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -45,10 +45,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x200000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

17
arch/powerpc/boot/dts/p4080ds.dts
View File

@ -1,7 +1,7 @@
/*
* P4080DS Device Tree Source
*
* Copyright 2009-2011 Freescale Semiconductor Inc.
* Copyright 2009 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -45,10 +45,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x200000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

17
arch/powerpc/boot/dts/p5020ds.dts
View File

@ -1,7 +1,7 @@
/*
* P5020DS Device Tree Source
*
* Copyright 2010-2011 Freescale Semiconductor Inc.
* Copyright 2010 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -45,10 +45,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x200000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

17
arch/powerpc/boot/dts/p5040ds.dts
View File

@ -1,7 +1,7 @@
/*
* P5040DS Device Tree Source
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2012 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -45,10 +45,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01008000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x200000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

17
arch/powerpc/boot/dts/t104xqds.dtsi
View File

@ -1,7 +1,7 @@
/*
* T104xQDS Device Tree Source
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -38,6 +38,17 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
@ -77,6 +88,10 @@
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x2000000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

14
arch/powerpc/boot/dts/t104xrdb.dtsi
View File

@ -33,6 +33,16 @@
*/
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
@ -69,6 +79,10 @@
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x2000000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

19
arch/powerpc/boot/dts/t208xqds.dtsi
View File

@ -1,7 +1,7 @@
/*
* T2080/T2081 QDS Device Tree Source
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -39,6 +39,17 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
@ -78,6 +89,10 @@
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x2000000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
@ -137,7 +152,7 @@
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
interrupts = <0x1 0x1 0 0>;
interrupts = <0xb 0x1 0 0>;
};
};

15
arch/powerpc/boot/dts/t208xrdb.dtsi
View File

@ -39,6 +39,17 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
@ -79,6 +90,10 @@
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x2000000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

17
arch/powerpc/boot/dts/t4240qds.dts
View File

@ -1,7 +1,7 @@
/*
* T4240QDS Device Tree Source
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2012 - 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -100,10 +100,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x2000000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

15
arch/powerpc/boot/dts/t4240rdb.dts
View File

@ -69,10 +69,25 @@
device_type = "memory";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
dcsr: dcsr@f00000000 {
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
};
bportals: bman-portals@ff4000000 {
ranges = <0x0 0xf 0xf4000000 0x2000000>;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;

6
arch/powerpc/boot/libfdt-wrapper.c
View File

@ -44,12 +44,12 @@
#define offset_devp(off) \
({ \
int _offset = (off); \
unsigned long _offset = (off); \
check_err(_offset) ? NULL : (void *)(_offset+1); \
})
#define devp_offset_find(devp) (((int)(devp))-1)
#define devp_offset(devp) (devp ? ((int)(devp))-1 : 0)
#define devp_offset_find(devp) (((unsigned long)(devp))-1)
#define devp_offset(devp) (devp ? ((unsigned long)(devp))-1 : 0)
static void *fdt;
static void *buf; /* = NULL */

14
arch/powerpc/boot/libfdt_env.h
View File

@ -4,15 +4,17 @@
#include <types.h>
#include <string.h>
#include "of.h"
typedef u32 uint32_t;
typedef u64 uint64_t;
typedef unsigned long uintptr_t;
#define fdt16_to_cpu(x) (x)
#define cpu_to_fdt16(x) (x)
#define fdt32_to_cpu(x) (x)
#define cpu_to_fdt32(x) (x)
#define fdt64_to_cpu(x) (x)
#define cpu_to_fdt64(x) (x)
#define fdt16_to_cpu(x) be16_to_cpu(x)
#define cpu_to_fdt16(x) cpu_to_be16(x)
#define fdt32_to_cpu(x) be32_to_cpu(x)
#define cpu_to_fdt32(x) cpu_to_be32(x)
#define fdt64_to_cpu(x) be64_to_cpu(x)
#define cpu_to_fdt64(x) cpu_to_be64(x)
#endif /* _ARCH_POWERPC_BOOT_LIBFDT_ENV_H */

8
arch/powerpc/boot/of.h
View File

@ -24,11 +24,19 @@ void of_console_init(void);
typedef u32 __be32;
#ifdef __LITTLE_ENDIAN__
#define cpu_to_be16(x) swab16(x)
#define be16_to_cpu(x) swab16(x)
#define cpu_to_be32(x) swab32(x)
#define be32_to_cpu(x) swab32(x)
#define cpu_to_be64(x) swab64(x)
#define be64_to_cpu(x) swab64(x)
#else
#define cpu_to_be16(x) (x)
#define be16_to_cpu(x) (x)
#define cpu_to_be32(x) (x)
#define be32_to_cpu(x) (x)
#define cpu_to_be64(x) (x)
#define be64_to_cpu(x) (x)
#endif
#define PROM_ERROR (-1u)

33
arch/powerpc/boot/planetcore.c
View File

@ -131,36 +131,3 @@ void planetcore_set_stdout_path(const char *table)
setprop_str(chosen, "linux,stdout-path", path);
}
void planetcore_set_serial_speed(const char *table)
{
void *chosen, *stdout;
u64 baud;
u32 baud32;
int len;
chosen = finddevice("/chosen");
if (!chosen)
return;
len = getprop(chosen, "linux,stdout-path", prop_buf, MAX_PROP_LEN);
if (len <= 0)
return;
stdout = finddevice(prop_buf);
if (!stdout) {
printf("planetcore_set_serial_speed: "
"Bad /chosen/linux,stdout-path.\r\n");
return;
}
if (!planetcore_get_decimal(table, PLANETCORE_KEY_SERIAL_BAUD,
&baud)) {
printf("planetcore_set_serial_speed: No SB tag.\r\n");
return;
}
baud32 = baud;
setprop(stdout, "current-speed", &baud32, 4);
}

3
arch/powerpc/boot/planetcore.h
View File

@ -43,7 +43,4 @@ void planetcore_set_mac_addrs(const char *table);
*/
void planetcore_set_stdout_path(const char *table);
/* Sets the current-speed property in the serial node. */
void planetcore_set_serial_speed(const char *table);
#endif

2
arch/powerpc/boot/wrapper
View File

@ -277,7 +277,7 @@ treeboot-iss4xx-mpic)
platformo="$object/treeboot-iss4xx.o"
;;
epapr)
platformo="$object/epapr.o $object/epapr-wrapper.o"
platformo="$object/pseries-head.o $object/epapr.o $object/epapr-wrapper.o"
link_address='0x20000000'
pie=-pie
;;

3
arch/powerpc/configs/cell_defconfig
View File

@ -28,7 +28,6 @@ CONFIG_PS3_ROM=m
CONFIG_PS3_FLASH=m
CONFIG_PS3_LPM=m
CONFIG_PPC_IBM_CELL_BLADE=y
CONFIG_PPC_CELLEB=y
CONFIG_RTAS_FLASH=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
@ -113,7 +112,6 @@ CONFIG_IDE=y
CONFIG_BLK_DEV_GENERIC=y
CONFIG_BLK_DEV_AEC62XX=y
CONFIG_BLK_DEV_SIIMAGE=y
CONFIG_BLK_DEV_CELLEB=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=y
@ -156,7 +154,6 @@ CONFIG_SERIAL_TXX9_NR_UARTS=2
CONFIG_SERIAL_TXX9_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_HVC_RTAS=y
CONFIG_HVC_BEAT=y
CONFIG_IPMI_HANDLER=m
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m

152
arch/powerpc/configs/celleb_defconfig
View File

@ -1,152 +0,0 @@
CONFIG_PPC64=y
CONFIG_TUNE_CELL=y
CONFIG_ALTIVEC=y
CONFIG_SMP=y
CONFIG_NR_CPUS=4
CONFIG_SYSVIPC=y
CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=15
CONFIG_BLK_DEV_INITRD=y
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_PPC_POWERNV is not set
# CONFIG_PPC_PSERIES is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_CELLEB=y
CONFIG_SPU_FS=y
# CONFIG_CBE_THERM is not set
CONFIG_UDBG_RTAS_CONSOLE=y
# CONFIG_RTAS_PROC is not set
CONFIG_BINFMT_MISC=m
CONFIG_KEXEC=y
CONFIG_NUMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_SYN_COOKIES=y
CONFIG_IPV6=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_TUNNEL=m
CONFIG_NETFILTER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_IDE=y
CONFIG_BLK_DEV_IDECD=m
CONFIG_BLK_DEV_GENERIC=y
CONFIG_BLK_DEV_CELLEB=y
CONFIG_SCSI=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=m
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_BLK_DEV_DM=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_MIRROR=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_NETDEVICES=y
CONFIG_SPIDER_NET=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO_I8042 is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_NONSTANDARD=y
CONFIG_SERIAL_TXX9_NR_UARTS=3
CONFIG_SERIAL_TXX9_CONSOLE=y
CONFIG_HVC_RTAS=y
CONFIG_HVC_BEAT=y
# CONFIG_HW_RANDOM is not set
CONFIG_GEN_RTC=y
CONFIG_I2C=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_EHCI_HCD=m
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_STORAGE=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT2_FS_XIP=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_HUGETLBFS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFSD=m
CONFIG_NFSD_V3=y
CONFIG_NFSD_V3_ACL=y
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_LIBCRC32C=m
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_XMON=y
CONFIG_XMON_DEFAULT=y
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
# CONFIG_CRYPTO_HW is not set

7
arch/powerpc/configs/corenet32_smp_defconfig
View File

@ -99,6 +99,8 @@ CONFIG_E1000E=y
CONFIG_AT803X_PHY=y
CONFIG_VITESSE_PHY=y
CONFIG_FIXED_PHY=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
@ -114,11 +116,14 @@ CONFIG_NVRAM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_FSL_SPI=y
CONFIG_SPI_FSL_ESPI=y
# CONFIG_HWMON is not set
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_INA2XX=y
CONFIG_USB_HID=m
CONFIG_USB=y
CONFIG_USB_MON=y

15
arch/powerpc/configs/corenet64_smp_defconfig
View File

@ -12,6 +12,10 @@ CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_SCHED=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
@ -75,6 +79,10 @@ CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_EEPROM_LEGACY=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=y
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_CHR_DEV_SG=y
CONFIG_ATA=y
CONFIG_SATA_FSL=y
CONFIG_SATA_SIL24=y
@ -85,6 +93,8 @@ CONFIG_FSL_XGMAC_MDIO=y
CONFIG_E1000E=y
CONFIG_VITESSE_PHY=y
CONFIG_FIXED_PHY=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
@ -99,11 +109,14 @@ CONFIG_SERIAL_8250_RSA=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_FSL_SPI=y
CONFIG_SPI_FSL_ESPI=y
# CONFIG_HWMON is not set
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_INA2XX=y
CONFIG_USB_HID=m
CONFIG_USB=y
CONFIG_USB_MON=y

3
arch/powerpc/configs/mpc85xx_defconfig
View File

@ -150,8 +150,7 @@ CONFIG_SPI=y
CONFIG_SPI_FSL_SPI=y
CONFIG_SPI_FSL_ESPI=y
CONFIG_GPIO_MPC8XXX=y
CONFIG_HWMON=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM90=y
CONFIG_FB=y
CONFIG_FB_FSL_DIU=y
# CONFIG_VGA_CONSOLE is not set

2
arch/powerpc/configs/mpc85xx_smp_defconfig
View File

@ -143,7 +143,7 @@ CONFIG_SPI=y
CONFIG_SPI_FSL_SPI=y
CONFIG_SPI_FSL_ESPI=y
CONFIG_GPIO_MPC8XXX=y
# CONFIG_HWMON is not set
CONFIG_SENSORS_LM90=y
CONFIG_FB=y
CONFIG_FB_FSL_DIU=y
# CONFIG_VGA_CONSOLE is not set

3
arch/powerpc/configs/ppc64_defconfig
View File

@ -36,7 +36,6 @@ CONFIG_PS3_ROM=m
CONFIG_PS3_FLASH=m
CONFIG_PS3_LPM=m
CONFIG_PPC_IBM_CELL_BLADE=y
CONFIG_PPC_CELLEB=y
CONFIG_PPC_CELL_QPACE=y
CONFIG_RTAS_FLASH=m
CONFIG_IBMEBUS=y
@ -89,7 +88,6 @@ CONFIG_IDE=y
CONFIG_BLK_DEV_IDECD=y
CONFIG_BLK_DEV_GENERIC=y
CONFIG_BLK_DEV_AMD74XX=y
CONFIG_BLK_DEV_CELLEB=y
CONFIG_BLK_DEV_IDE_PMAC=y
CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
CONFIG_BLK_DEV_SD=y
@ -196,7 +194,6 @@ CONFIG_SERIAL_TXX9_CONSOLE=y
CONFIG_SERIAL_JSM=m
CONFIG_HVC_CONSOLE=y
CONFIG_HVC_RTAS=y
CONFIG_HVC_BEAT=y
CONFIG_HVCS=m
CONFIG_VIRTIO_CONSOLE=m
CONFIG_IBM_BSR=m

4
arch/powerpc/include/asm/Kbuild
View File

@ -1,6 +1,8 @@
generic-y += clkdev.h
generic-y += div64.h
generic-y += irq_regs.h
generic-y += irq_work.h
generic-y += local64.h
generic-y += mcs_spinlock.h
generic-y += preempt.h
generic-y += rwsem.h

3
arch/powerpc/include/asm/cache.h
View File

@ -76,9 +76,6 @@ extern void _set_L3CR(unsigned long);
#define _set_L3CR(val) do { } while(0)
#endif
extern void cacheable_memzero(void *p, unsigned int nb);
extern void *cacheable_memcpy(void *, const void *, unsigned int);
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_CACHE_H */

8
arch/powerpc/include/asm/cputable.h
View File

@ -100,7 +100,7 @@ struct cpu_spec {
/*
* Processor specific routine to flush tlbs.
*/
void (*flush_tlb)(unsigned long inval_selector);
void (*flush_tlb)(unsigned int action);
};
@ -114,6 +114,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
extern const char *powerpc_base_platform;
/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
enum {
TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */
TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
};
#endif /* __ASSEMBLY__ */
/* CPU kernel features */

12
arch/powerpc/include/asm/dbdma.h
View File

@ -42,12 +42,12 @@ struct dbdma_regs {
* DBDMA command structure. These fields are all little-endian!
*/
struct dbdma_cmd {
unsigned short req_count; /* requested byte transfer count */
unsigned short command; /* command word (has bit-fields) */
unsigned int phy_addr; /* physical data address */
unsigned int cmd_dep; /* command-dependent field */
unsigned short res_count; /* residual count after completion */
unsigned short xfer_status; /* transfer status */
__le16 req_count; /* requested byte transfer count */
__le16 command; /* command word (has bit-fields) */
__le32 phy_addr; /* physical data address */
__le32 cmd_dep; /* command-dependent field */
__le16 res_count; /* residual count after completion */
__le16 xfer_status; /* transfer status */
};
/* DBDMA command values in command field */

2
arch/powerpc/include/asm/dcr-native.h
View File

@ -31,7 +31,7 @@ typedef struct {
static inline bool dcr_map_ok_native(dcr_host_native_t host)
{
return 1;
return true;
}
#define dcr_map_native(dev, dcr_n, dcr_c) \

6
arch/powerpc/include/asm/device.h
View File

@ -8,6 +8,9 @@
struct dma_map_ops;
struct device_node;
#ifdef CONFIG_PPC64
struct pci_dn;
#endif
/*
* Arch extensions to struct device.
@ -34,6 +37,9 @@ struct dev_archdata {
#ifdef CONFIG_SWIOTLB
dma_addr_t max_direct_dma_addr;
#endif
#ifdef CONFIG_PPC64
struct pci_dn *pci_data;
#endif
#ifdef CONFIG_EEH
struct eeh_dev *edev;
#endif

1
arch/powerpc/include/asm/div64.h
View File

@ -1 +0,0 @@
#include <asm-generic/div64.h>

4
arch/powerpc/include/asm/dma-mapping.h
View File

@ -191,11 +191,11 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
struct dev_archdata *sd = &dev->archdata;
if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr)
return 0;
return false;
#endif
if (!dev->dma_mask)
return 0;
return false;
return addr + size - 1 <= *dev->dma_mask;
}

29
arch/powerpc/include/asm/eeh.h
View File

@ -29,7 +29,7 @@
struct pci_dev;
struct pci_bus;
struct device_node;
struct pci_dn;
#ifdef CONFIG_EEH
@ -136,14 +136,14 @@ struct eeh_dev {
struct eeh_pe *pe; /* Associated PE */
struct list_head list; /* Form link list in the PE */
struct pci_controller *phb; /* Associated PHB */
struct device_node *dn; /* Associated device node */
struct pci_dn *pdn; /* Associated PCI device node */
struct pci_dev *pdev; /* Associated PCI device */
struct pci_bus *bus; /* PCI bus for partial hotplug */
};
static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
{
return edev ? edev->dn : NULL;
return edev ? edev->pdn : NULL;
}
static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
@ -200,8 +200,7 @@ struct eeh_ops {
char *name;
int (*init)(void);
int (*post_init)(void);
void* (*of_probe)(struct device_node *dn, void *flag);
int (*dev_probe)(struct pci_dev *dev, void *flag);
void* (*probe)(struct pci_dn *pdn, void *data);
int (*set_option)(struct eeh_pe *pe, int option);
int (*get_pe_addr)(struct eeh_pe *pe);
int (*get_state)(struct eeh_pe *pe, int *state);
@ -211,10 +210,10 @@ struct eeh_ops {
int (*configure_bridge)(struct eeh_pe *pe);
int (*err_inject)(struct eeh_pe *pe, int type, int func,
unsigned long addr, unsigned long mask);
int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
int (*write_config)(struct device_node *dn, int where, int size, u32 val);
int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
int (*next_error)(struct eeh_pe **pe);
int (*restore_config)(struct device_node *dn);
int (*restore_config)(struct pci_dn *pdn);
};
extern int eeh_subsystem_flags;
@ -272,7 +271,7 @@ void eeh_pe_restore_bars(struct eeh_pe *pe);
const char *eeh_pe_loc_get(struct eeh_pe *pe);
struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
void *eeh_dev_init(struct device_node *dn, void *data);
void *eeh_dev_init(struct pci_dn *pdn, void *data);
void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
int eeh_init(void);
int __init eeh_ops_register(struct eeh_ops *ops);
@ -280,8 +279,8 @@ int __exit eeh_ops_unregister(const char *name);
int eeh_check_failure(const volatile void __iomem *token);
int eeh_dev_check_failure(struct eeh_dev *edev);
void eeh_addr_cache_build(void);
void eeh_add_device_early(struct device_node *);
void eeh_add_device_tree_early(struct device_node *);
void eeh_add_device_early(struct pci_dn *);
void eeh_add_device_tree_early(struct pci_dn *);
void eeh_add_device_late(struct pci_dev *);
void eeh_add_device_tree_late(struct pci_bus *);
void eeh_add_sysfs_files(struct pci_bus *);
@ -323,7 +322,7 @@ static inline int eeh_init(void)
return 0;
}
static inline void *eeh_dev_init(struct device_node *dn, void *data)
static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
{
return NULL;
}
@ -339,9 +338,9 @@ static inline int eeh_check_failure(const volatile void __iomem *token)
static inline void eeh_addr_cache_build(void) { }
static inline void eeh_add_device_early(struct device_node *dn) { }
static inline void eeh_add_device_early(struct pci_dn *pdn) { }
static inline void eeh_add_device_tree_early(struct device_node *dn) { }
static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
static inline void eeh_add_device_late(struct pci_dev *dev) { }

10
arch/powerpc/include/asm/firmware.h
View File

@ -42,7 +42,7 @@
#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000)
/* Free ASM_CONST(0x0000000001000000) */
#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000)
#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000)
@ -75,8 +75,6 @@ enum {
FW_FEATURE_POWERNV_ALWAYS = 0,
FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
FW_FEATURE_CELLEB_ALWAYS = 0,
FW_FEATURE_NATIVE_POSSIBLE = 0,
FW_FEATURE_NATIVE_ALWAYS = 0,
FW_FEATURE_POSSIBLE =
@ -89,9 +87,6 @@ enum {
#ifdef CONFIG_PPC_PS3
FW_FEATURE_PS3_POSSIBLE |
#endif
#ifdef CONFIG_PPC_CELLEB
FW_FEATURE_CELLEB_POSSIBLE |
#endif
#ifdef CONFIG_PPC_NATIVE
FW_FEATURE_NATIVE_ALWAYS |
#endif
@ -106,9 +101,6 @@ enum {
#ifdef CONFIG_PPC_PS3
FW_FEATURE_PS3_ALWAYS &
#endif
#ifdef CONFIG_PPC_CELLEB
FW_FEATURE_CELLEB_ALWAYS &
#endif
#ifdef CONFIG_PPC_NATIVE
FW_FEATURE_NATIVE_ALWAYS &
#endif

6
arch/powerpc/include/asm/iommu.h
View File

@ -29,6 +29,7 @@
#include <linux/bitops.h>
#include <asm/machdep.h>
#include <asm/types.h>
#include <asm/pci-bridge.h>
#define IOMMU_PAGE_SHIFT_4K 12
#define IOMMU_PAGE_SIZE_4K (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K)
@ -78,6 +79,9 @@ struct iommu_table {
struct iommu_group *it_group;
#endif
void (*set_bypass)(struct iommu_table *tbl, bool enable);
#ifdef CONFIG_PPC_POWERNV
void *data;
#endif
};
/* Pure 2^n version of get_order */
@ -169,7 +173,7 @@ extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
struct dma_attrs *attrs);
extern void iommu_init_early_pSeries(void);
extern void iommu_init_early_dart(void);
extern void iommu_init_early_dart(struct pci_controller_ops *controller_ops);
extern void iommu_init_early_pasemi(void);
extern void alloc_dart_table(void);

2
arch/powerpc/include/asm/irq_regs.h
View File

@ -1,2 +0,0 @@
#include <asm-generic/irq_regs.h>

16
arch/powerpc/include/asm/kvm_book3s_64.h
View File

@ -290,11 +290,11 @@ static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing,
pte_t old_pte, new_pte = __pte(0);
while (1) {
old_pte = pte_val(*ptep);
old_pte = *ptep;
/*
* wait until _PAGE_BUSY is clear then set it atomically
*/
if (unlikely(old_pte & _PAGE_BUSY)) {
if (unlikely(pte_val(old_pte) & _PAGE_BUSY)) {
cpu_relax();
continue;
}
@ -305,16 +305,18 @@ static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing,
return __pte(0);
#endif
/* If pte is not present return None */
if (unlikely(!(old_pte & _PAGE_PRESENT)))
if (unlikely(!(pte_val(old_pte) & _PAGE_PRESENT)))
return __pte(0);
new_pte = pte_mkyoung(old_pte);
if (writing && pte_write(old_pte))
new_pte = pte_mkdirty(new_pte);
if (old_pte == __cmpxchg_u64((unsigned long *)ptep, old_pte,
new_pte))
if (pte_val(old_pte) == __cmpxchg_u64((unsigned long *)ptep,
pte_val(old_pte),
pte_val(new_pte))) {
break;
}
}
return new_pte;
}
@ -335,7 +337,7 @@ static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
{
if (key)
return PP_RWRX <= pp && pp <= PP_RXRX;
return 1;
return true;
}
static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
@ -373,7 +375,7 @@ static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
if (pagesize <= PAGE_SIZE)
return 1;
return true;
return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
}

2
arch/powerpc/include/asm/kvm_host.h
View File

@ -585,7 +585,7 @@ struct kvm_vcpu_arch {
pgd_t *pgdir;
u8 io_gpr; /* GPR used as IO source/target */
u8 mmio_is_bigendian;
u8 mmio_host_swabbed;
u8 mmio_sign_extend;
u8 osi_needed;
u8 osi_enabled;

1
arch/powerpc/include/asm/local64.h
View File

@ -1 +0,0 @@
#include <asm-generic/local64.h>

19
arch/powerpc/include/asm/machdep.h
View File

@ -103,9 +103,6 @@ struct machdep_calls {
#endif
#endif /* CONFIG_PPC64 */
void (*pci_dma_dev_setup)(struct pci_dev *dev);
void (*pci_dma_bus_setup)(struct pci_bus *bus);
/* Platform set_dma_mask and dma_get_required_mask overrides */
int (*dma_set_mask)(struct device *dev, u64 dma_mask);
u64 (*dma_get_required_mask)(struct device *dev);
@ -125,9 +122,8 @@ struct machdep_calls {
unsigned int (*get_irq)(void);
/* PCI stuff */
/* Called after scanning the bus, before allocating resources */
/* Called after allocating resources */
void (*pcibios_fixup)(void);
int (*pci_probe_mode)(struct pci_bus *);
void (*pci_irq_fixup)(struct pci_dev *dev);
int (*pcibios_root_bridge_prepare)(struct pci_host_bridge
*bridge);
@ -237,18 +233,13 @@ struct machdep_calls {
/* Called for each PCI bus in the system when it's probed */
void (*pcibios_fixup_bus)(struct pci_bus *);
/* Called when pci_enable_device() is called. Returns 0 to
* allow assignment/enabling of the device. */
int (*pcibios_enable_device_hook)(struct pci_dev *);
/* Called after scan and before resource survey */
void (*pcibios_fixup_phb)(struct pci_controller *hose);
/* Called during PCI resource reassignment */
resource_size_t (*pcibios_window_alignment)(struct pci_bus *, unsigned long type);
/* Reset the secondary bus of bridge */
void (*pcibios_reset_secondary_bus)(struct pci_dev *dev);
#ifdef CONFIG_PCI_IOV
void (*pcibios_fixup_sriov)(struct pci_dev *pdev);
resource_size_t (*pcibios_iov_resource_alignment)(struct pci_dev *, int resno);
#endif /* CONFIG_PCI_IOV */
/* Called to shutdown machine specific hardware not already controlled
* by other drivers.

1
arch/powerpc/include/asm/mmu-hash64.h
View File

@ -112,6 +112,7 @@
#define TLBIEL_INVAL_SET_SHIFT 12
#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
#define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
#ifndef __ASSEMBLY__

1
arch/powerpc/include/asm/mpc85xx.h
View File

@ -61,6 +61,7 @@
#define SVR_T4240 0x824000
#define SVR_T4120 0x824001
#define SVR_T4160 0x824100
#define SVR_T4080 0x824102
#define SVR_C291 0x850000
#define SVR_C292 0x850020
#define SVR_C293 0x850030

17
arch/powerpc/include/asm/mpic.h
View File

@ -34,10 +34,6 @@
#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
#define MPIC_GREG_GCONF_MCK 0x08000000
#define MPIC_GREG_GLOBAL_CONF_1 0x00030
#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
#define MPIC_GREG_VENDOR_0 0x00040
#define MPIC_GREG_VENDOR_1 0x00050
#define MPIC_GREG_VENDOR_2 0x00060
@ -396,14 +392,7 @@ extern struct bus_type mpic_subsys;
#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
/* Get the version of primary MPIC */
#ifdef CONFIG_MPIC
extern u32 fsl_mpic_primary_get_version(void);
#else
static inline u32 fsl_mpic_primary_get_version(void)
{
return 0;
}
#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
@ -496,11 +485,5 @@ extern unsigned int mpic_get_coreint_irq(void);
/* Fetch Machine Check interrupt from primary mpic */
extern unsigned int mpic_get_mcirq(void);
/* Set the EPIC clock ratio */
void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
/* Enable/Disable EPIC serial interrupt mode */
void mpic_set_serial_int(struct mpic *mpic, int enable);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MPIC_H */

4
arch/powerpc/include/asm/nmi.h Normal file
View File

@ -0,0 +1,4 @@
#ifndef _ASM_NMI_H
#define _ASM_NMI_H
#endif /* _ASM_NMI_H */

50
arch/powerpc/include/asm/nvram.h
View File

@ -9,12 +9,43 @@
#ifndef _ASM_POWERPC_NVRAM_H
#define _ASM_POWERPC_NVRAM_H
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <uapi/asm/nvram.h>
/*
* Set oops header version to distinguish between old and new format header.
* lnx,oops-log partition max size is 4000, header version > 4000 will
* help in identifying new header.
*/
#define OOPS_HDR_VERSION 5000
struct err_log_info {
__be32 error_type;
__be32 seq_num;
};
struct nvram_os_partition {
const char *name;
int req_size; /* desired size, in bytes */
int min_size; /* minimum acceptable size (0 means req_size) */
long size; /* size of data portion (excluding err_log_info) */
long index; /* offset of data portion of partition */
bool os_partition; /* partition initialized by OS, not FW */
};
struct oops_log_info {
__be16 version;
__be16 report_length;
__be64 timestamp;
} __attribute__((packed));
extern struct nvram_os_partition oops_log_partition;
#ifdef CONFIG_PPC_PSERIES
extern struct nvram_os_partition rtas_log_partition;
extern int nvram_write_error_log(char * buff, int length,
unsigned int err_type, unsigned int err_seq);
extern int nvram_read_error_log(char * buff, int length,
@ -50,6 +81,23 @@ extern void pmac_xpram_write(int xpaddr, u8 data);
/* Synchronize NVRAM */
extern void nvram_sync(void);
/* Initialize NVRAM OS partition */
extern int __init nvram_init_os_partition(struct nvram_os_partition *part);
/* Initialize NVRAM oops partition */
extern void __init nvram_init_oops_partition(int rtas_partition_exists);
/* Read a NVRAM partition */
extern int nvram_read_partition(struct nvram_os_partition *part, char *buff,
int length, unsigned int *err_type,
unsigned int *error_log_cnt);
/* Write to NVRAM OS partition */
extern int nvram_write_os_partition(struct nvram_os_partition *part,
char *buff, int length,
unsigned int err_type,
unsigned int error_log_cnt);
/* Determine NVRAM size */
extern ssize_t nvram_get_size(void);

735
arch/powerpc/include/asm/opal-api.h Normal file
View File

@ -0,0 +1,735 @@
/*
* OPAL API definitions.
*
* Copyright 2011-2015 IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __OPAL_API_H
#define __OPAL_API_H
/****** OPAL APIs ******/
/* Return codes */
#define OPAL_SUCCESS 0
#define OPAL_PARAMETER -1
#define OPAL_BUSY -2
#define OPAL_PARTIAL -3
#define OPAL_CONSTRAINED -4
#define OPAL_CLOSED -5
#define OPAL_HARDWARE -6
#define OPAL_UNSUPPORTED -7
#define OPAL_PERMISSION -8
#define OPAL_NO_MEM -9
#define OPAL_RESOURCE -10
#define OPAL_INTERNAL_ERROR -11
#define OPAL_BUSY_EVENT -12
#define OPAL_HARDWARE_FROZEN -13
#define OPAL_WRONG_STATE -14
#define OPAL_ASYNC_COMPLETION -15
#define OPAL_EMPTY -16
#define OPAL_I2C_TIMEOUT -17
#define OPAL_I2C_INVALID_CMD -18
#define OPAL_I2C_LBUS_PARITY -19
#define OPAL_I2C_BKEND_OVERRUN -20
#define OPAL_I2C_BKEND_ACCESS -21
#define OPAL_I2C_ARBT_LOST -22
#define OPAL_I2C_NACK_RCVD -23
#define OPAL_I2C_STOP_ERR -24
/* API Tokens (in r0) */
#define OPAL_INVALID_CALL -1
#define OPAL_TEST 0
#define OPAL_CONSOLE_WRITE 1
#define OPAL_CONSOLE_READ 2
#define OPAL_RTC_READ 3
#define OPAL_RTC_WRITE 4
#define OPAL_CEC_POWER_DOWN 5
#define OPAL_CEC_REBOOT 6
#define OPAL_READ_NVRAM 7
#define OPAL_WRITE_NVRAM 8
#define OPAL_HANDLE_INTERRUPT 9
#define OPAL_POLL_EVENTS 10
#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
#define OPAL_PCI_CONFIG_READ_BYTE 13
#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
#define OPAL_PCI_CONFIG_READ_WORD 15
#define OPAL_PCI_CONFIG_WRITE_BYTE 16
#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
#define OPAL_PCI_CONFIG_WRITE_WORD 18
#define OPAL_SET_XIVE 19
#define OPAL_GET_XIVE 20
#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
#define OPAL_PCI_EEH_FREEZE_STATUS 23
#define OPAL_PCI_SHPC 24
#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
#define OPAL_PCI_EEH_FREEZE_CLEAR 26
#define OPAL_PCI_PHB_MMIO_ENABLE 27
#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
#define OPAL_PCI_SET_PE 31
#define OPAL_PCI_SET_PELTV 32
#define OPAL_PCI_SET_MVE 33
#define OPAL_PCI_SET_MVE_ENABLE 34
#define OPAL_PCI_GET_XIVE_REISSUE 35
#define OPAL_PCI_SET_XIVE_REISSUE 36
#define OPAL_PCI_SET_XIVE_PE 37
#define OPAL_GET_XIVE_SOURCE 38
#define OPAL_GET_MSI_32 39
#define OPAL_GET_MSI_64 40
#define OPAL_START_CPU 41
#define OPAL_QUERY_CPU_STATUS 42
#define OPAL_WRITE_OPPANEL 43 /* unimplemented */
#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
#define OPAL_PCI_RESET 49
#define OPAL_PCI_GET_HUB_DIAG_DATA 50
#define OPAL_PCI_GET_PHB_DIAG_DATA 51
#define OPAL_PCI_FENCE_PHB 52
#define OPAL_PCI_REINIT 53
#define OPAL_PCI_MASK_PE_ERROR 54
#define OPAL_SET_SLOT_LED_STATUS 55
#define OPAL_GET_EPOW_STATUS 56
#define OPAL_SET_SYSTEM_ATTENTION_LED 57
#define OPAL_RESERVED1 58
#define OPAL_RESERVED2 59
#define OPAL_PCI_NEXT_ERROR 60
#define OPAL_PCI_EEH_FREEZE_STATUS2 61
#define OPAL_PCI_POLL 62
#define OPAL_PCI_MSI_EOI 63
#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
#define OPAL_XSCOM_READ 65
#define OPAL_XSCOM_WRITE 66
#define OPAL_LPC_READ 67
#define OPAL_LPC_WRITE 68
#define OPAL_RETURN_CPU 69
#define OPAL_REINIT_CPUS 70
#define OPAL_ELOG_READ 71
#define OPAL_ELOG_WRITE 72
#define OPAL_ELOG_ACK 73
#define OPAL_ELOG_RESEND 74
#define OPAL_ELOG_SIZE 75
#define OPAL_FLASH_VALIDATE 76
#define OPAL_FLASH_MANAGE 77
#define OPAL_FLASH_UPDATE 78
#define OPAL_RESYNC_TIMEBASE 79
#define OPAL_CHECK_TOKEN 80
#define OPAL_DUMP_INIT 81
#define OPAL_DUMP_INFO 82
#define OPAL_DUMP_READ 83
#define OPAL_DUMP_ACK 84
#define OPAL_GET_MSG 85
#define OPAL_CHECK_ASYNC_COMPLETION 86
#define OPAL_SYNC_HOST_REBOOT 87
#define OPAL_SENSOR_READ 88
#define OPAL_GET_PARAM 89
#define OPAL_SET_PARAM 90
#define OPAL_DUMP_RESEND 91
#define OPAL_ELOG_SEND 92 /* Deprecated */
#define OPAL_PCI_SET_PHB_CAPI_MODE 93
#define OPAL_DUMP_INFO2 94
#define OPAL_WRITE_OPPANEL_ASYNC 95
#define OPAL_PCI_ERR_INJECT 96
#define OPAL_PCI_EEH_FREEZE_SET 97
#define OPAL_HANDLE_HMI 98
#define OPAL_CONFIG_CPU_IDLE_STATE 99
#define OPAL_SLW_SET_REG 100
#define OPAL_REGISTER_DUMP_REGION 101
#define OPAL_UNREGISTER_DUMP_REGION 102
#define OPAL_WRITE_TPO 103
#define OPAL_READ_TPO 104
#define OPAL_GET_DPO_STATUS 105
#define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */
#define OPAL_IPMI_SEND 107
#define OPAL_IPMI_RECV 108
#define OPAL_I2C_REQUEST 109
#define OPAL_FLASH_READ 110
#define OPAL_FLASH_WRITE 111
#define OPAL_FLASH_ERASE 112
#define OPAL_LAST 112
/* Device tree flags */
/* Flags set in power-mgmt nodes in device tree if
* respective idle states are supported in the platform.
*/
#define OPAL_PM_NAP_ENABLED 0x00010000
#define OPAL_PM_SLEEP_ENABLED 0x00020000
#define OPAL_PM_WINKLE_ENABLED 0x00040000
#define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
#ifndef __ASSEMBLY__
/* Other enums */
enum OpalFreezeState {
OPAL_EEH_STOPPED_NOT_FROZEN = 0,
OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
OPAL_EEH_STOPPED_DMA_FREEZE = 2,
OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
OPAL_EEH_STOPPED_RESET = 4,
OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
};
enum OpalEehFreezeActionToken {
OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
};
enum OpalPciStatusToken {
OPAL_EEH_NO_ERROR = 0,
OPAL_EEH_IOC_ERROR = 1,
OPAL_EEH_PHB_ERROR = 2,
OPAL_EEH_PE_ERROR = 3,
OPAL_EEH_PE_MMIO_ERROR = 4,
OPAL_EEH_PE_DMA_ERROR = 5
};
enum OpalPciErrorSeverity {
OPAL_EEH_SEV_NO_ERROR = 0,
OPAL_EEH_SEV_IOC_DEAD = 1,
OPAL_EEH_SEV_PHB_DEAD = 2,
OPAL_EEH_SEV_PHB_FENCED = 3,
OPAL_EEH_SEV_PE_ER = 4,
OPAL_EEH_SEV_INF = 5
};
enum OpalErrinjectType {
OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
};
enum OpalErrinjectFunc {
/* IOA bus specific errors */
OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
};
enum OpalMmioWindowType {
OPAL_M32_WINDOW_TYPE = 1,
OPAL_M64_WINDOW_TYPE = 2,
OPAL_IO_WINDOW_TYPE = 3
};
enum OpalExceptionHandler {
OPAL_MACHINE_CHECK_HANDLER = 1,
OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
OPAL_SOFTPATCH_HANDLER = 3
};
enum OpalPendingState {
OPAL_EVENT_OPAL_INTERNAL = 0x1,
OPAL_EVENT_NVRAM = 0x2,
OPAL_EVENT_RTC = 0x4,
OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
OPAL_EVENT_CONSOLE_INPUT = 0x10,
OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
OPAL_EVENT_ERROR_LOG = 0x40,
OPAL_EVENT_EPOW = 0x80,
OPAL_EVENT_LED_STATUS = 0x100,
OPAL_EVENT_PCI_ERROR = 0x200,
OPAL_EVENT_DUMP_AVAIL = 0x400,
OPAL_EVENT_MSG_PENDING = 0x800,
};
enum OpalThreadStatus {
OPAL_THREAD_INACTIVE = 0x0,
OPAL_THREAD_STARTED = 0x1,
OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
};
enum OpalPciBusCompare {
OpalPciBusAny = 0, /* Any bus number match */
OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
OpalPciBusAll = 7, /* Match bus number exactly */
};
enum OpalDeviceCompare {
OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
OPAL_COMPARE_RID_DEVICE_NUMBER = 1
};
enum OpalFuncCompare {
OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
};
enum OpalPeAction {
OPAL_UNMAP_PE = 0,
OPAL_MAP_PE = 1
};
enum OpalPeltvAction {
OPAL_REMOVE_PE_FROM_DOMAIN = 0,
OPAL_ADD_PE_TO_DOMAIN = 1
};
enum OpalMveEnableAction {
OPAL_DISABLE_MVE = 0,
OPAL_ENABLE_MVE = 1
};
enum OpalM64Action {
OPAL_DISABLE_M64 = 0,
OPAL_ENABLE_M64_SPLIT = 1,
OPAL_ENABLE_M64_NON_SPLIT = 2
};
enum OpalPciResetScope {
OPAL_RESET_PHB_COMPLETE = 1,
OPAL_RESET_PCI_LINK = 2,
OPAL_RESET_PHB_ERROR = 3,
OPAL_RESET_PCI_HOT = 4,
OPAL_RESET_PCI_FUNDAMENTAL = 5,
OPAL_RESET_PCI_IODA_TABLE = 6
};
enum OpalPciReinitScope {
/*
* Note: we chose values that do not overlap
* OpalPciResetScope as OPAL v2 used the same
* enum for both
*/
OPAL_REINIT_PCI_DEV = 1000
};
enum OpalPciResetState {
OPAL_DEASSERT_RESET = 0,
OPAL_ASSERT_RESET = 1
};
/*
* Address cycle types for LPC accesses. These also correspond
* to the content of the first cell of the "reg" property for
* device nodes on the LPC bus
*/
enum OpalLPCAddressType {
OPAL_LPC_MEM = 0,
OPAL_LPC_IO = 1,
OPAL_LPC_FW = 2,
};
enum opal_msg_type {
OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
* additional params function-specific
*/
OPAL_MSG_MEM_ERR,
OPAL_MSG_EPOW,
OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */
OPAL_MSG_HMI_EVT,
OPAL_MSG_DPO,
OPAL_MSG_TYPE_MAX,
};
struct opal_msg {
__be32 msg_type;
__be32 reserved;
__be64 params[8];
};
/* System parameter permission */
enum OpalSysparamPerm {
OPAL_SYSPARAM_READ = 0x1,
OPAL_SYSPARAM_WRITE = 0x2,
OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
};
enum {
OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
};
struct opal_ipmi_msg {
uint8_t version;
uint8_t netfn;
uint8_t cmd;
uint8_t data[];
};
/* FSP memory errors handling */
enum OpalMemErr_Version {
OpalMemErr_V1 = 1,
};
enum OpalMemErrType {
OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
OPAL_MEM_ERR_TYPE_DYN_DALLOC,
};
/* Memory Reilience error type */
enum OpalMemErr_ResilErrType {
OPAL_MEM_RESILIENCE_CE = 0,
OPAL_MEM_RESILIENCE_UE,
OPAL_MEM_RESILIENCE_UE_SCRUB,
};
/* Dynamic Memory Deallocation type */
enum OpalMemErr_DynErrType {
OPAL_MEM_DYNAMIC_DEALLOC = 0,
};
struct OpalMemoryErrorData {
enum OpalMemErr_Version version:8; /* 0x00 */
enum OpalMemErrType type:8; /* 0x01 */
__be16 flags; /* 0x02 */
uint8_t reserved_1[4]; /* 0x04 */
union {
/* Memory Resilience corrected/uncorrected error info */
struct {
enum OpalMemErr_ResilErrType resil_err_type:8;
uint8_t reserved_1[7];
__be64 physical_address_start;
__be64 physical_address_end;
} resilience;
/* Dynamic memory deallocation error info */
struct {
enum OpalMemErr_DynErrType dyn_err_type:8;
uint8_t reserved_1[7];
__be64 physical_address_start;
__be64 physical_address_end;
} dyn_dealloc;
} u;
};
/* HMI interrupt event */
enum OpalHMI_Version {
OpalHMIEvt_V1 = 1,
};
enum OpalHMI_Severity {
OpalHMI_SEV_NO_ERROR = 0,
OpalHMI_SEV_WARNING = 1,
OpalHMI_SEV_ERROR_SYNC = 2,
OpalHMI_SEV_FATAL = 3,
};
enum OpalHMI_Disposition {
OpalHMI_DISPOSITION_RECOVERED = 0,
OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
};
enum OpalHMI_ErrType {
OpalHMI_ERROR_MALFUNC_ALERT = 0,
OpalHMI_ERROR_PROC_RECOV_DONE,
OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
OpalHMI_ERROR_PROC_RECOV_MASKED,
OpalHMI_ERROR_TFAC,
OpalHMI_ERROR_TFMR_PARITY,
OpalHMI_ERROR_HA_OVERFLOW_WARN,
OpalHMI_ERROR_XSCOM_FAIL,
OpalHMI_ERROR_XSCOM_DONE,
OpalHMI_ERROR_SCOM_FIR,
OpalHMI_ERROR_DEBUG_TRIG_FIR,
OpalHMI_ERROR_HYP_RESOURCE,
OpalHMI_ERROR_CAPP_RECOVERY,
};
struct OpalHMIEvent {
uint8_t version; /* 0x00 */
uint8_t severity; /* 0x01 */
uint8_t type; /* 0x02 */
uint8_t disposition; /* 0x03 */
uint8_t reserved_1[4]; /* 0x04 */
__be64 hmer;
/* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
__be64 tfmr;
};
enum {
OPAL_P7IOC_DIAG_TYPE_NONE = 0,
OPAL_P7IOC_DIAG_TYPE_RGC = 1,
OPAL_P7IOC_DIAG_TYPE_BI = 2,
OPAL_P7IOC_DIAG_TYPE_CI = 3,
OPAL_P7IOC_DIAG_TYPE_MISC = 4,
OPAL_P7IOC_DIAG_TYPE_I2C = 5,
OPAL_P7IOC_DIAG_TYPE_LAST = 6
};
struct OpalIoP7IOCErrorData {
__be16 type;
/* GEM */
__be64 gemXfir;
__be64 gemRfir;
__be64 gemRirqfir;
__be64 gemMask;
__be64 gemRwof;
/* LEM */
__be64 lemFir;
__be64 lemErrMask;
__be64 lemAction0;
__be64 lemAction1;
__be64 lemWof;
union {
struct OpalIoP7IOCRgcErrorData {
__be64 rgcStatus; /* 3E1C10 */
__be64 rgcLdcp; /* 3E1C18 */
}rgc;
struct OpalIoP7IOCBiErrorData {
__be64 biLdcp0; /* 3C0100, 3C0118 */
__be64 biLdcp1; /* 3C0108, 3C0120 */
__be64 biLdcp2; /* 3C0110, 3C0128 */
__be64 biFenceStatus; /* 3C0130, 3C0130 */
uint8_t biDownbound; /* BI Downbound or Upbound */
}bi;
struct OpalIoP7IOCCiErrorData {
__be64 ciPortStatus; /* 3Dn008 */
__be64 ciPortLdcp; /* 3Dn010 */
uint8_t ciPort; /* Index of CI port: 0/1 */
}ci;
};
};
/**
* This structure defines the overlay which will be used to store PHB error
* data upon request.
*/
enum {
OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
};
enum {
OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
};
enum {
OPAL_P7IOC_NUM_PEST_REGS = 128,
OPAL_PHB3_NUM_PEST_REGS = 256
};
struct OpalIoPhbErrorCommon {
__be32 version;
__be32 ioType;
__be32 len;
};
struct OpalIoP7IOCPhbErrorData {
struct OpalIoPhbErrorCommon common;
__be32 brdgCtl;
// P7IOC utl regs
__be32 portStatusReg;
__be32 rootCmplxStatus;
__be32 busAgentStatus;
// P7IOC cfg regs
__be32 deviceStatus;
__be32 slotStatus;
__be32 linkStatus;
__be32 devCmdStatus;
__be32 devSecStatus;
// cfg AER regs
__be32 rootErrorStatus;
__be32 uncorrErrorStatus;
__be32 corrErrorStatus;
__be32 tlpHdr1;
__be32 tlpHdr2;
__be32 tlpHdr3;
__be32 tlpHdr4;
__be32 sourceId;
__be32 rsv3;
// Record data about the call to allocate a buffer.
__be64 errorClass;
__be64 correlator;
//P7IOC MMIO Error Regs
__be64 p7iocPlssr; // n120
__be64 p7iocCsr; // n110
__be64 lemFir; // nC00
__be64 lemErrorMask; // nC18
__be64 lemWOF; // nC40
__be64 phbErrorStatus; // nC80
__be64 phbFirstErrorStatus; // nC88
__be64 phbErrorLog0; // nCC0
__be64 phbErrorLog1; // nCC8
__be64 mmioErrorStatus; // nD00
__be64 mmioFirstErrorStatus; // nD08
__be64 mmioErrorLog0; // nD40
__be64 mmioErrorLog1; // nD48
__be64 dma0ErrorStatus; // nD80
__be64 dma0FirstErrorStatus; // nD88
__be64 dma0ErrorLog0; // nDC0
__be64 dma0ErrorLog1; // nDC8
__be64 dma1ErrorStatus; // nE00
__be64 dma1FirstErrorStatus; // nE08
__be64 dma1ErrorLog0; // nE40
__be64 dma1ErrorLog1; // nE48
__be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
__be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
};
struct OpalIoPhb3ErrorData {
struct OpalIoPhbErrorCommon common;
__be32 brdgCtl;
/* PHB3 UTL regs */
__be32 portStatusReg;
__be32 rootCmplxStatus;
__be32 busAgentStatus;
/* PHB3 cfg regs */
__be32 deviceStatus;
__be32 slotStatus;
__be32 linkStatus;
__be32 devCmdStatus;
__be32 devSecStatus;
/* cfg AER regs */
__be32 rootErrorStatus;
__be32 uncorrErrorStatus;
__be32 corrErrorStatus;
__be32 tlpHdr1;
__be32 tlpHdr2;
__be32 tlpHdr3;
__be32 tlpHdr4;
__be32 sourceId;
__be32 rsv3;
/* Record data about the call to allocate a buffer */
__be64 errorClass;
__be64 correlator;
/* PHB3 MMIO Error Regs */
__be64 nFir; /* 000 */
__be64 nFirMask; /* 003 */
__be64 nFirWOF; /* 008 */
__be64 phbPlssr; /* 120 */
__be64 phbCsr; /* 110 */
__be64 lemFir; /* C00 */
__be64 lemErrorMask; /* C18 */
__be64 lemWOF; /* C40 */
__be64 phbErrorStatus; /* C80 */
__be64 phbFirstErrorStatus; /* C88 */
__be64 phbErrorLog0; /* CC0 */
__be64 phbErrorLog1; /* CC8 */
__be64 mmioErrorStatus; /* D00 */
__be64 mmioFirstErrorStatus; /* D08 */
__be64 mmioErrorLog0; /* D40 */
__be64 mmioErrorLog1; /* D48 */
__be64 dma0ErrorStatus; /* D80 */
__be64 dma0FirstErrorStatus; /* D88 */
__be64 dma0ErrorLog0; /* DC0 */
__be64 dma0ErrorLog1; /* DC8 */
__be64 dma1ErrorStatus; /* E00 */
__be64 dma1FirstErrorStatus; /* E08 */
__be64 dma1ErrorLog0; /* E40 */
__be64 dma1ErrorLog1; /* E48 */
__be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
__be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
};
enum {
OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
};
typedef struct oppanel_line {
__be64 line;
__be64 line_len;
} oppanel_line_t;
/*
* SG entries
*
* WARNING: The current implementation requires each entry
* to represent a block that is 4k aligned *and* each block
* size except the last one in the list to be as well.
*/
struct opal_sg_entry {
__be64 data;
__be64 length;
};
/*
* Candiate image SG list.
*
* length = VER | length
*/
struct opal_sg_list {
__be64 length;
__be64 next;
struct opal_sg_entry entry[];
};
/*
* Dump region ID range usable by the OS
*/
#define OPAL_DUMP_REGION_HOST_START 0x80
#define OPAL_DUMP_REGION_LOG_BUF 0x80
#define OPAL_DUMP_REGION_HOST_END 0xFF
/* CAPI modes for PHB */
enum {
OPAL_PHB_CAPI_MODE_PCIE = 0,
OPAL_PHB_CAPI_MODE_CAPI = 1,
OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
};
/* OPAL I2C request */
struct opal_i2c_request {
uint8_t type;
#define OPAL_I2C_RAW_READ 0
#define OPAL_I2C_RAW_WRITE 1
#define OPAL_I2C_SM_READ 2
#define OPAL_I2C_SM_WRITE 3
uint8_t flags;
#define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
uint8_t subaddr_sz; /* Max 4 */
uint8_t reserved;
__be16 addr; /* 7 or 10 bit address */
__be16 reserved2;
__be32 subaddr; /* Sub-address if any */
__be32 size; /* Data size */
__be64 buffer_ra; /* Buffer real address */
};
#endif /* __ASSEMBLY__ */
#endif /* __OPAL_API_H */

770
arch/powerpc/include/asm/opal.h
View File

@ -9,755 +9,17 @@
* 2 of the License, or (at your option) any later version.
*/
#ifndef __OPAL_H
#define __OPAL_H
#ifndef _ASM_POWERPC_OPAL_H
#define _ASM_POWERPC_OPAL_H
#ifndef __ASSEMBLY__
/*
* SG entry
*
* WARNING: The current implementation requires each entry
* to represent a block that is 4k aligned *and* each block
* size except the last one in the list to be as well.
*/
struct opal_sg_entry {
__be64 data;
__be64 length;
};
/* SG list */
struct opal_sg_list {
__be64 length;
__be64 next;
struct opal_sg_entry entry[];
};
/* We calculate number of sg entries based on PAGE_SIZE */
#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
#endif /* __ASSEMBLY__ */
/****** OPAL APIs ******/
/* Return codes */
#define OPAL_SUCCESS 0
#define OPAL_PARAMETER -1
#define OPAL_BUSY -2
#define OPAL_PARTIAL -3
#define OPAL_CONSTRAINED -4
#define OPAL_CLOSED -5
#define OPAL_HARDWARE -6
#define OPAL_UNSUPPORTED -7
#define OPAL_PERMISSION -8
#define OPAL_NO_MEM -9
#define OPAL_RESOURCE -10
#define OPAL_INTERNAL_ERROR -11
#define OPAL_BUSY_EVENT -12
#define OPAL_HARDWARE_FROZEN -13
#define OPAL_WRONG_STATE -14
#define OPAL_ASYNC_COMPLETION -15
#define OPAL_I2C_TIMEOUT -17
#define OPAL_I2C_INVALID_CMD -18
#define OPAL_I2C_LBUS_PARITY -19
#define OPAL_I2C_BKEND_OVERRUN -20
#define OPAL_I2C_BKEND_ACCESS -21
#define OPAL_I2C_ARBT_LOST -22
#define OPAL_I2C_NACK_RCVD -23
#define OPAL_I2C_STOP_ERR -24
/* API Tokens (in r0) */
#define OPAL_INVALID_CALL -1
#define OPAL_CONSOLE_WRITE 1
#define OPAL_CONSOLE_READ 2
#define OPAL_RTC_READ 3
#define OPAL_RTC_WRITE 4
#define OPAL_CEC_POWER_DOWN 5
#define OPAL_CEC_REBOOT 6
#define OPAL_READ_NVRAM 7
#define OPAL_WRITE_NVRAM 8
#define OPAL_HANDLE_INTERRUPT 9
#define OPAL_POLL_EVENTS 10
#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
#define OPAL_PCI_CONFIG_READ_BYTE 13
#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
#define OPAL_PCI_CONFIG_READ_WORD 15
#define OPAL_PCI_CONFIG_WRITE_BYTE 16
#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
#define OPAL_PCI_CONFIG_WRITE_WORD 18
#define OPAL_SET_XIVE 19
#define OPAL_GET_XIVE 20
#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
#define OPAL_PCI_EEH_FREEZE_STATUS 23
#define OPAL_PCI_SHPC 24
#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
#define OPAL_PCI_EEH_FREEZE_CLEAR 26
#define OPAL_PCI_PHB_MMIO_ENABLE 27
#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
#define OPAL_PCI_SET_PE 31
#define OPAL_PCI_SET_PELTV 32
#define OPAL_PCI_SET_MVE 33
#define OPAL_PCI_SET_MVE_ENABLE 34
#define OPAL_PCI_GET_XIVE_REISSUE 35
#define OPAL_PCI_SET_XIVE_REISSUE 36
#define OPAL_PCI_SET_XIVE_PE 37
#define OPAL_GET_XIVE_SOURCE 38
#define OPAL_GET_MSI_32 39
#define OPAL_GET_MSI_64 40
#define OPAL_START_CPU 41
#define OPAL_QUERY_CPU_STATUS 42
#define OPAL_WRITE_OPPANEL 43
#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
#define OPAL_PCI_RESET 49
#define OPAL_PCI_GET_HUB_DIAG_DATA 50
#define OPAL_PCI_GET_PHB_DIAG_DATA 51
#define OPAL_PCI_FENCE_PHB 52
#define OPAL_PCI_REINIT 53
#define OPAL_PCI_MASK_PE_ERROR 54
#define OPAL_SET_SLOT_LED_STATUS 55
#define OPAL_GET_EPOW_STATUS 56
#define OPAL_SET_SYSTEM_ATTENTION_LED 57
#define OPAL_RESERVED1 58
#define OPAL_RESERVED2 59
#define OPAL_PCI_NEXT_ERROR 60
#define OPAL_PCI_EEH_FREEZE_STATUS2 61
#define OPAL_PCI_POLL 62
#define OPAL_PCI_MSI_EOI 63
#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
#define OPAL_XSCOM_READ 65
#define OPAL_XSCOM_WRITE 66
#define OPAL_LPC_READ 67
#define OPAL_LPC_WRITE 68
#define OPAL_RETURN_CPU 69
#define OPAL_REINIT_CPUS 70
#define OPAL_ELOG_READ 71
#define OPAL_ELOG_WRITE 72
#define OPAL_ELOG_ACK 73
#define OPAL_ELOG_RESEND 74
#define OPAL_ELOG_SIZE 75
#define OPAL_FLASH_VALIDATE 76
#define OPAL_FLASH_MANAGE 77
#define OPAL_FLASH_UPDATE 78
#define OPAL_RESYNC_TIMEBASE 79
#define OPAL_CHECK_TOKEN 80
#define OPAL_DUMP_INIT 81
#define OPAL_DUMP_INFO 82
#define OPAL_DUMP_READ 83
#define OPAL_DUMP_ACK 84
#define OPAL_GET_MSG 85
#define OPAL_CHECK_ASYNC_COMPLETION 86
#define OPAL_SYNC_HOST_REBOOT 87
#define OPAL_SENSOR_READ 88
#define OPAL_GET_PARAM 89
#define OPAL_SET_PARAM 90
#define OPAL_DUMP_RESEND 91
#define OPAL_PCI_SET_PHB_CXL_MODE 93
#define OPAL_DUMP_INFO2 94
#define OPAL_PCI_ERR_INJECT 96
#define OPAL_PCI_EEH_FREEZE_SET 97
#define OPAL_HANDLE_HMI 98
#define OPAL_CONFIG_CPU_IDLE_STATE 99
#define OPAL_SLW_SET_REG 100
#define OPAL_REGISTER_DUMP_REGION 101
#define OPAL_UNREGISTER_DUMP_REGION 102
#define OPAL_WRITE_TPO 103
#define OPAL_READ_TPO 104
#define OPAL_IPMI_SEND 107
#define OPAL_IPMI_RECV 108
#define OPAL_I2C_REQUEST 109
/* Device tree flags */
/* Flags set in power-mgmt nodes in device tree if
* respective idle states are supported in the platform.
*/
#define OPAL_PM_NAP_ENABLED 0x00010000
#define OPAL_PM_SLEEP_ENABLED 0x00020000
#define OPAL_PM_WINKLE_ENABLED 0x00040000
#define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000
#include <asm/opal-api.h>
#ifndef __ASSEMBLY__
#include <linux/notifier.h>
/* Other enums */
enum OpalVendorApiTokens {
OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
};
enum OpalFreezeState {
OPAL_EEH_STOPPED_NOT_FROZEN = 0,
OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
OPAL_EEH_STOPPED_DMA_FREEZE = 2,
OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
OPAL_EEH_STOPPED_RESET = 4,
OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
};
enum OpalEehFreezeActionToken {
OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
};
enum OpalPciStatusToken {
OPAL_EEH_NO_ERROR = 0,
OPAL_EEH_IOC_ERROR = 1,
OPAL_EEH_PHB_ERROR = 2,
OPAL_EEH_PE_ERROR = 3,
OPAL_EEH_PE_MMIO_ERROR = 4,
OPAL_EEH_PE_DMA_ERROR = 5
};
enum OpalPciErrorSeverity {
OPAL_EEH_SEV_NO_ERROR = 0,
OPAL_EEH_SEV_IOC_DEAD = 1,
OPAL_EEH_SEV_PHB_DEAD = 2,
OPAL_EEH_SEV_PHB_FENCED = 3,
OPAL_EEH_SEV_PE_ER = 4,
OPAL_EEH_SEV_INF = 5
};
enum OpalErrinjectType {
OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
};
enum OpalErrinjectFunc {
/* IOA bus specific errors */
OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
};
enum OpalShpcAction {
OPAL_SHPC_GET_LINK_STATE = 0,
OPAL_SHPC_GET_SLOT_STATE = 1
};
enum OpalShpcLinkState {
OPAL_SHPC_LINK_DOWN = 0,
OPAL_SHPC_LINK_UP = 1
};
enum OpalMmioWindowType {
OPAL_M32_WINDOW_TYPE = 1,
OPAL_M64_WINDOW_TYPE = 2,
OPAL_IO_WINDOW_TYPE = 3
};
enum OpalShpcSlotState {
OPAL_SHPC_DEV_NOT_PRESENT = 0,
OPAL_SHPC_DEV_PRESENT = 1
};
enum OpalExceptionHandler {
OPAL_MACHINE_CHECK_HANDLER = 1,
OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
OPAL_SOFTPATCH_HANDLER = 3
};
enum OpalPendingState {
OPAL_EVENT_OPAL_INTERNAL = 0x1,
OPAL_EVENT_NVRAM = 0x2,
OPAL_EVENT_RTC = 0x4,
OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
OPAL_EVENT_CONSOLE_INPUT = 0x10,
OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
OPAL_EVENT_ERROR_LOG = 0x40,
OPAL_EVENT_EPOW = 0x80,
OPAL_EVENT_LED_STATUS = 0x100,
OPAL_EVENT_PCI_ERROR = 0x200,
OPAL_EVENT_DUMP_AVAIL = 0x400,
OPAL_EVENT_MSG_PENDING = 0x800,
};
enum OpalMessageType {
OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
* additional params function-specific
*/
OPAL_MSG_MEM_ERR,
OPAL_MSG_EPOW,
OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */
OPAL_MSG_HMI_EVT,
OPAL_MSG_TYPE_MAX,
};
enum OpalThreadStatus {
OPAL_THREAD_INACTIVE = 0x0,
OPAL_THREAD_STARTED = 0x1,
OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
};
enum OpalPciBusCompare {
OpalPciBusAny = 0, /* Any bus number match */
OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
OpalPciBusAll = 7, /* Match bus number exactly */
};
enum OpalDeviceCompare {
OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
OPAL_COMPARE_RID_DEVICE_NUMBER = 1
};
enum OpalFuncCompare {
OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
};
enum OpalPeAction {
OPAL_UNMAP_PE = 0,
OPAL_MAP_PE = 1
};
enum OpalPeltvAction {
OPAL_REMOVE_PE_FROM_DOMAIN = 0,
OPAL_ADD_PE_TO_DOMAIN = 1
};
enum OpalMveEnableAction {
OPAL_DISABLE_MVE = 0,
OPAL_ENABLE_MVE = 1
};
enum OpalM64EnableAction {
OPAL_DISABLE_M64 = 0,
OPAL_ENABLE_M64_SPLIT = 1,
OPAL_ENABLE_M64_NON_SPLIT = 2
};
enum OpalPciResetScope {
OPAL_RESET_PHB_COMPLETE = 1,
OPAL_RESET_PCI_LINK = 2,
OPAL_RESET_PHB_ERROR = 3,
OPAL_RESET_PCI_HOT = 4,
OPAL_RESET_PCI_FUNDAMENTAL = 5,
OPAL_RESET_PCI_IODA_TABLE = 6
};
enum OpalPciReinitScope {
OPAL_REINIT_PCI_DEV = 1000
};
enum OpalPciResetState {
OPAL_DEASSERT_RESET = 0,
OPAL_ASSERT_RESET = 1
};
enum OpalPciMaskAction {
OPAL_UNMASK_ERROR_TYPE = 0,
OPAL_MASK_ERROR_TYPE = 1
};
enum OpalSlotLedType {
OPAL_SLOT_LED_ID_TYPE = 0,
OPAL_SLOT_LED_FAULT_TYPE = 1
};
enum OpalLedAction {
OPAL_TURN_OFF_LED = 0,
OPAL_TURN_ON_LED = 1,
OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
};
enum OpalEpowStatus {
OPAL_EPOW_NONE = 0,
OPAL_EPOW_UPS = 1,
OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
OPAL_EPOW_OVER_INTERNAL_TEMP = 3
};
/*
* Address cycle types for LPC accesses. These also correspond
* to the content of the first cell of the "reg" property for
* device nodes on the LPC bus
*/
enum OpalLPCAddressType {
OPAL_LPC_MEM = 0,
OPAL_LPC_IO = 1,
OPAL_LPC_FW = 2,
};
/* System parameter permission */
enum OpalSysparamPerm {
OPAL_SYSPARAM_READ = 0x1,
OPAL_SYSPARAM_WRITE = 0x2,
OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
};
struct opal_msg {
__be32 msg_type;
__be32 reserved;
__be64 params[8];
};
enum {
OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
};
struct opal_ipmi_msg {
uint8_t version;
uint8_t netfn;
uint8_t cmd;
uint8_t data[];
};
/* FSP memory errors handling */
enum OpalMemErr_Version {
OpalMemErr_V1 = 1,
};
enum OpalMemErrType {
OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
OPAL_MEM_ERR_TYPE_DYN_DALLOC,
OPAL_MEM_ERR_TYPE_SCRUB,
};
/* Memory Reilience error type */
enum OpalMemErr_ResilErrType {
OPAL_MEM_RESILIENCE_CE = 0,
OPAL_MEM_RESILIENCE_UE,
OPAL_MEM_RESILIENCE_UE_SCRUB,
};
/* Dynamic Memory Deallocation type */
enum OpalMemErr_DynErrType {
OPAL_MEM_DYNAMIC_DEALLOC = 0,
};
/* OpalMemoryErrorData->flags */
#define OPAL_MEM_CORRECTED_ERROR 0x0001
#define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
#define OPAL_MEM_ACK_REQUIRED 0x8000
struct OpalMemoryErrorData {
enum OpalMemErr_Version version:8; /* 0x00 */
enum OpalMemErrType type:8; /* 0x01 */
__be16 flags; /* 0x02 */
uint8_t reserved_1[4]; /* 0x04 */
union {
/* Memory Resilience corrected/uncorrected error info */
struct {
enum OpalMemErr_ResilErrType resil_err_type:8;
uint8_t reserved_1[7];
__be64 physical_address_start;
__be64 physical_address_end;
} resilience;
/* Dynamic memory deallocation error info */
struct {
enum OpalMemErr_DynErrType dyn_err_type:8;
uint8_t reserved_1[7];
__be64 physical_address_start;
__be64 physical_address_end;
} dyn_dealloc;
} u;
};
/* HMI interrupt event */
enum OpalHMI_Version {
OpalHMIEvt_V1 = 1,
};
enum OpalHMI_Severity {
OpalHMI_SEV_NO_ERROR = 0,
OpalHMI_SEV_WARNING = 1,
OpalHMI_SEV_ERROR_SYNC = 2,
OpalHMI_SEV_FATAL = 3,
};
enum OpalHMI_Disposition {
OpalHMI_DISPOSITION_RECOVERED = 0,
OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
};
enum OpalHMI_ErrType {
OpalHMI_ERROR_MALFUNC_ALERT = 0,
OpalHMI_ERROR_PROC_RECOV_DONE,
OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
OpalHMI_ERROR_PROC_RECOV_MASKED,
OpalHMI_ERROR_TFAC,
OpalHMI_ERROR_TFMR_PARITY,
OpalHMI_ERROR_HA_OVERFLOW_WARN,
OpalHMI_ERROR_XSCOM_FAIL,
OpalHMI_ERROR_XSCOM_DONE,
OpalHMI_ERROR_SCOM_FIR,
OpalHMI_ERROR_DEBUG_TRIG_FIR,
OpalHMI_ERROR_HYP_RESOURCE,
};
struct OpalHMIEvent {
uint8_t version; /* 0x00 */
uint8_t severity; /* 0x01 */
uint8_t type; /* 0x02 */
uint8_t disposition; /* 0x03 */
uint8_t reserved_1[4]; /* 0x04 */
__be64 hmer;
/* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
__be64 tfmr;
};
enum {
OPAL_P7IOC_DIAG_TYPE_NONE = 0,
OPAL_P7IOC_DIAG_TYPE_RGC = 1,
OPAL_P7IOC_DIAG_TYPE_BI = 2,
OPAL_P7IOC_DIAG_TYPE_CI = 3,
OPAL_P7IOC_DIAG_TYPE_MISC = 4,
OPAL_P7IOC_DIAG_TYPE_I2C = 5,
OPAL_P7IOC_DIAG_TYPE_LAST = 6
};
struct OpalIoP7IOCErrorData {
__be16 type;
/* GEM */
__be64 gemXfir;
__be64 gemRfir;
__be64 gemRirqfir;
__be64 gemMask;
__be64 gemRwof;
/* LEM */
__be64 lemFir;
__be64 lemErrMask;
__be64 lemAction0;
__be64 lemAction1;
__be64 lemWof;
union {
struct OpalIoP7IOCRgcErrorData {
__be64 rgcStatus; /* 3E1C10 */
__be64 rgcLdcp; /* 3E1C18 */
}rgc;
struct OpalIoP7IOCBiErrorData {
__be64 biLdcp0; /* 3C0100, 3C0118 */
__be64 biLdcp1; /* 3C0108, 3C0120 */
__be64 biLdcp2; /* 3C0110, 3C0128 */
__be64 biFenceStatus; /* 3C0130, 3C0130 */
u8 biDownbound; /* BI Downbound or Upbound */
}bi;
struct OpalIoP7IOCCiErrorData {
__be64 ciPortStatus; /* 3Dn008 */
__be64 ciPortLdcp; /* 3Dn010 */
u8 ciPort; /* Index of CI port: 0/1 */
}ci;
};
};
/**
* This structure defines the overlay which will be used to store PHB error
* data upon request.
*/
enum {
OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
};
enum {
OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
};
enum {
OPAL_P7IOC_NUM_PEST_REGS = 128,
OPAL_PHB3_NUM_PEST_REGS = 256
};
/* CAPI modes for PHB */
enum {
OPAL_PHB_CAPI_MODE_PCIE = 0,
OPAL_PHB_CAPI_MODE_CAPI = 1,
OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
};
struct OpalIoPhbErrorCommon {
__be32 version;
__be32 ioType;
__be32 len;
};
struct OpalIoP7IOCPhbErrorData {
struct OpalIoPhbErrorCommon common;
__be32 brdgCtl;
// P7IOC utl regs
__be32 portStatusReg;
__be32 rootCmplxStatus;
__be32 busAgentStatus;
// P7IOC cfg regs
__be32 deviceStatus;
__be32 slotStatus;
__be32 linkStatus;
__be32 devCmdStatus;
__be32 devSecStatus;
// cfg AER regs
__be32 rootErrorStatus;
__be32 uncorrErrorStatus;
__be32 corrErrorStatus;
__be32 tlpHdr1;
__be32 tlpHdr2;
__be32 tlpHdr3;
__be32 tlpHdr4;
__be32 sourceId;
__be32 rsv3;
// Record data about the call to allocate a buffer.
__be64 errorClass;
__be64 correlator;
//P7IOC MMIO Error Regs
__be64 p7iocPlssr; // n120
__be64 p7iocCsr; // n110
__be64 lemFir; // nC00
__be64 lemErrorMask; // nC18
__be64 lemWOF; // nC40
__be64 phbErrorStatus; // nC80
__be64 phbFirstErrorStatus; // nC88
__be64 phbErrorLog0; // nCC0
__be64 phbErrorLog1; // nCC8
__be64 mmioErrorStatus; // nD00
__be64 mmioFirstErrorStatus; // nD08
__be64 mmioErrorLog0; // nD40
__be64 mmioErrorLog1; // nD48
__be64 dma0ErrorStatus; // nD80
__be64 dma0FirstErrorStatus; // nD88
__be64 dma0ErrorLog0; // nDC0
__be64 dma0ErrorLog1; // nDC8
__be64 dma1ErrorStatus; // nE00
__be64 dma1FirstErrorStatus; // nE08
__be64 dma1ErrorLog0; // nE40
__be64 dma1ErrorLog1; // nE48
__be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
__be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
};
struct OpalIoPhb3ErrorData {
struct OpalIoPhbErrorCommon common;
__be32 brdgCtl;
/* PHB3 UTL regs */
__be32 portStatusReg;
__be32 rootCmplxStatus;
__be32 busAgentStatus;
/* PHB3 cfg regs */
__be32 deviceStatus;
__be32 slotStatus;
__be32 linkStatus;
__be32 devCmdStatus;
__be32 devSecStatus;
/* cfg AER regs */
__be32 rootErrorStatus;
__be32 uncorrErrorStatus;
__be32 corrErrorStatus;
__be32 tlpHdr1;
__be32 tlpHdr2;
__be32 tlpHdr3;
__be32 tlpHdr4;
__be32 sourceId;
__be32 rsv3;
/* Record data about the call to allocate a buffer */
__be64 errorClass;
__be64 correlator;
__be64 nFir; /* 000 */
__be64 nFirMask; /* 003 */
__be64 nFirWOF; /* 008 */
/* PHB3 MMIO Error Regs */
__be64 phbPlssr; /* 120 */
__be64 phbCsr; /* 110 */
__be64 lemFir; /* C00 */
__be64 lemErrorMask; /* C18 */
__be64 lemWOF; /* C40 */
__be64 phbErrorStatus; /* C80 */
__be64 phbFirstErrorStatus; /* C88 */
__be64 phbErrorLog0; /* CC0 */
__be64 phbErrorLog1; /* CC8 */
__be64 mmioErrorStatus; /* D00 */
__be64 mmioFirstErrorStatus; /* D08 */
__be64 mmioErrorLog0; /* D40 */
__be64 mmioErrorLog1; /* D48 */
__be64 dma0ErrorStatus; /* D80 */
__be64 dma0FirstErrorStatus; /* D88 */
__be64 dma0ErrorLog0; /* DC0 */
__be64 dma0ErrorLog1; /* DC8 */
__be64 dma1ErrorStatus; /* E00 */
__be64 dma1FirstErrorStatus; /* E08 */
__be64 dma1ErrorLog0; /* E40 */
__be64 dma1ErrorLog1; /* E48 */
__be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
__be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
};
enum {
OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
};
typedef struct oppanel_line {
const char * line;
uint64_t line_len;
} oppanel_line_t;
/* OPAL I2C request */
struct opal_i2c_request {
uint8_t type;
#define OPAL_I2C_RAW_READ 0
#define OPAL_I2C_RAW_WRITE 1
#define OPAL_I2C_SM_READ 2
#define OPAL_I2C_SM_WRITE 3
uint8_t flags;
#define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
uint8_t subaddr_sz; /* Max 4 */
uint8_t reserved;
__be16 addr; /* 7 or 10 bit address */
__be16 reserved2;
__be32 subaddr; /* Sub-address if any */
__be32 size; /* Data size */
__be64 buffer_ra; /* Buffer real address */
};
/* We calculate number of sg entries based on PAGE_SIZE */
#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
/* /sys/firmware/opal */
extern struct kobject *opal_kobj;
@ -932,6 +194,13 @@ int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
struct opal_i2c_request *oreq);
int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
uint64_t size, uint64_t token);
int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
uint64_t size, uint64_t token);
int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
uint64_t token);
/* Internal functions */
extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
int depth, void *data);
@ -946,8 +215,10 @@ extern void hvc_opal_init_early(void);
extern int opal_notifier_register(struct notifier_block *nb);
extern int opal_notifier_unregister(struct notifier_block *nb);
extern int opal_message_notifier_register(enum OpalMessageType msg_type,
extern int opal_message_notifier_register(enum opal_msg_type msg_type,
struct notifier_block *nb);
extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
struct notifier_block *nb);
extern void opal_notifier_enable(void);
extern void opal_notifier_disable(void);
extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
@ -962,7 +233,7 @@ extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
struct rtc_time;
extern unsigned long opal_get_boot_time(void);
extern void opal_nvram_init(void);
extern void opal_flash_init(void);
extern void opal_flash_update_init(void);
extern void opal_flash_term_callback(void);
extern int opal_elog_init(void);
extern void opal_platform_dump_init(void);
@ -983,13 +254,8 @@ struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
unsigned long vmalloc_size);
void opal_free_sg_list(struct opal_sg_list *sg);
/*
* Dump region ID range usable by the OS
*/
#define OPAL_DUMP_REGION_HOST_START 0x80
#define OPAL_DUMP_REGION_LOG_BUF 0x80
#define OPAL_DUMP_REGION_HOST_END 0xFF
extern int opal_error_code(int rc);
#endif /* __ASSEMBLY__ */
#endif /* __OPAL_H */
#endif /* _ASM_POWERPC_OPAL_H */

4
arch/powerpc/include/asm/paca.h
View File

@ -106,9 +106,9 @@ struct paca_struct {
#endif /* CONFIG_PPC_STD_MMU_64 */
#ifdef CONFIG_PPC_BOOK3E
u64 exgen[8] __attribute__((aligned(0x80)));
u64 exgen[8] __aligned(0x40);
/* Keep pgd in the same cacheline as the start of extlb */
pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
pgd_t *pgd __aligned(0x40); /* Current PGD */
pgd_t *kernel_pgd; /* Kernel PGD */
/* Shared by all threads of a core -- points to tcd of first thread */

60
arch/powerpc/include/asm/pci-bridge.h
View File

@ -14,6 +14,24 @@
struct device_node;
/*
* PCI controller operations
*/
struct pci_controller_ops {
void (*dma_dev_setup)(struct pci_dev *dev);
void (*dma_bus_setup)(struct pci_bus *bus);
int (*probe_mode)(struct pci_bus *);
/* Called when pci_enable_device() is called. Returns true to
* allow assignment/enabling of the device. */
bool (*enable_device_hook)(struct pci_dev *);
/* Called during PCI resource reassignment */
resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
void (*reset_secondary_bus)(struct pci_dev *dev);
};
/*
* Structure of a PCI controller (host bridge)
*/
@ -46,6 +64,7 @@ struct pci_controller {
resource_size_t isa_mem_phys;
resource_size_t isa_mem_size;
struct pci_controller_ops controller_ops;
struct pci_ops *ops;
unsigned int __iomem *cfg_addr;
void __iomem *cfg_data;
@ -89,6 +108,7 @@ struct pci_controller {
#ifdef CONFIG_PPC64
unsigned long buid;
struct pci_dn *pci_data;
#endif /* CONFIG_PPC64 */
void *private_data;
@ -154,31 +174,51 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
struct iommu_table;
struct pci_dn {
int flags;
#define PCI_DN_FLAG_IOV_VF 0x01
int busno; /* pci bus number */
int devfn; /* pci device and function number */
int vendor_id; /* Vendor ID */
int device_id; /* Device ID */
int class_code; /* Device class code */
struct pci_dn *parent;
struct pci_controller *phb; /* for pci devices */
struct iommu_table *iommu_table; /* for phb's or bridges */
struct device_node *node; /* back-pointer to the device_node */
int pci_ext_config_space; /* for pci devices */
struct pci_dev *pcidev; /* back-pointer to the pci device */
#ifdef CONFIG_EEH
struct eeh_dev *edev; /* eeh device */
#endif
#define IODA_INVALID_PE (-1)
#ifdef CONFIG_PPC_POWERNV
int pe_number;
#ifdef CONFIG_PCI_IOV
u16 vfs_expanded; /* number of VFs IOV BAR expanded */
u16 num_vfs; /* number of VFs enabled*/
int offset; /* PE# for the first VF PE */
#define M64_PER_IOV 4
int m64_per_iov;
#define IODA_INVALID_M64 (-1)
int m64_wins[PCI_SRIOV_NUM_BARS][M64_PER_IOV];
#endif /* CONFIG_PCI_IOV */
#endif
struct list_head child_list;
struct list_head list;
};
/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
int devfn);
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
extern void * update_dn_pci_info(struct device_node *dn, void *data);
extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev);
extern void remove_dev_pci_data(struct pci_dev *pdev);
extern void *update_dn_pci_info(struct device_node *dn, void *data);
static inline int pci_device_from_OF_node(struct device_node *np,
u8 *bus, u8 *devfn)
@ -191,20 +231,12 @@ static inline int pci_device_from_OF_node(struct device_node *np,
}
#if defined(CONFIG_EEH)
static inline struct eeh_dev *of_node_to_eeh_dev(struct device_node *dn)
static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
{
/*
* For those OF nodes whose parent isn't PCI bridge, they
* don't have PCI_DN actually. So we have to skip them for
* any EEH operations.
*/
if (!dn || !PCI_DN(dn))
return NULL;
return PCI_DN(dn)->edev;
return pdn ? pdn->edev : NULL;
}
#else
#define of_node_to_eeh_dev(x) (NULL)
#define pdn_to_eeh_dev(x) (NULL)
#endif
/** Find the bus corresponding to the indicated device node */

2
arch/powerpc/include/asm/pci.h
View File

@ -22,7 +22,7 @@
#include <asm-generic/pci-dma-compat.h>
/* Return values for ppc_md.pci_probe_mode function */
/* Return values for pci_controller_ops.probe_mode function */
#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */

8
arch/powerpc/include/asm/ppc-pci.h
View File

@ -23,8 +23,6 @@ extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
extern struct list_head hose_list;
extern void find_and_init_phbs(void);
extern struct pci_dev *isa_bridge_pcidev; /* may be NULL if no ISA bus */
/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
@ -33,9 +31,14 @@ extern struct pci_dev *isa_bridge_pcidev; /* may be NULL if no ISA bus */
/* PCI device_node operations */
struct device_node;
struct pci_dn;
typedef void *(*traverse_func)(struct device_node *me, void *data);
void *traverse_pci_devices(struct device_node *start, traverse_func pre,
void *data);
void *traverse_pci_dn(struct pci_dn *root,
void *(*fn)(struct pci_dn *, void *),
void *data);
extern void pci_devs_phb_init(void);
extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
@ -76,7 +79,6 @@ static inline const char *eeh_driver_name(struct pci_dev *pdev)
#endif /* CONFIG_EEH */
#else /* CONFIG_PCI */
static inline void find_and_init_phbs(void) { }
static inline void init_pci_config_tokens(void) { }
#endif /* !CONFIG_PCI */

192
arch/powerpc/include/asm/ppc_asm.h
View File

@ -637,105 +637,105 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945)
/* AltiVec Registers (VPRs) */
#define vr0 0
#define vr1 1
#define vr2 2
#define vr3 3
#define vr4 4
#define vr5 5
#define vr6 6
#define vr7 7
#define vr8 8
#define vr9 9
#define vr10 10
#define vr11 11
#define vr12 12
#define vr13 13
#define vr14 14
#define vr15 15
#define vr16 16
#define vr17 17
#define vr18 18
#define vr19 19
#define vr20 20
#define vr21 21
#define vr22 22
#define vr23 23
#define vr24 24
#define vr25 25
#define vr26 26
#define vr27 27
#define vr28 28
#define vr29 29
#define vr30 30
#define vr31 31
#define v0 0
#define v1 1
#define v2 2
#define v3 3
#define v4 4
#define v5 5
#define v6 6
#define v7 7
#define v8 8
#define v9 9
#define v10 10
#define v11 11
#define v12 12
#define v13 13
#define v14 14
#define v15 15
#define v16 16
#define v17 17
#define v18 18
#define v19 19
#define v20 20
#define v21 21
#define v22 22
#define v23 23
#define v24 24
#define v25 25
#define v26 26
#define v27 27
#define v28 28
#define v29 29
#define v30 30
#define v31 31
/* VSX Registers (VSRs) */
#define vsr0 0
#define vsr1 1
#define vsr2 2
#define vsr3 3
#define vsr4 4
#define vsr5 5
#define vsr6 6
#define vsr7 7
#define vsr8 8
#define vsr9 9
#define vsr10 10
#define vsr11 11
#define vsr12 12
#define vsr13 13
#define vsr14 14
#define vsr15 15
#define vsr16 16
#define vsr17 17
#define vsr18 18
#define vsr19 19
#define vsr20 20
#define vsr21 21
#define vsr22 22
#define vsr23 23
#define vsr24 24
#define vsr25 25
#define vsr26 26
#define vsr27 27
#define vsr28 28
#define vsr29 29
#define vsr30 30
#define vsr31 31
#define vsr32 32
#define vsr33 33
#define vsr34 34
#define vsr35 35
#define vsr36 36
#define vsr37 37
#define vsr38 38
#define vsr39 39
#define vsr40 40
#define vsr41 41
#define vsr42 42
#define vsr43 43
#define vsr44 44
#define vsr45 45
#define vsr46 46
#define vsr47 47
#define vsr48 48
#define vsr49 49
#define vsr50 50
#define vsr51 51
#define vsr52 52
#define vsr53 53
#define vsr54 54
#define vsr55 55
#define vsr56 56
#define vsr57 57
#define vsr58 58
#define vsr59 59
#define vsr60 60
#define vsr61 61
#define vsr62 62
#define vsr63 63
#define vs0 0
#define vs1 1
#define vs2 2
#define vs3 3
#define vs4 4
#define vs5 5
#define vs6 6
#define vs7 7
#define vs8 8
#define vs9 9
#define vs10 10
#define vs11 11
#define vs12 12
#define vs13 13
#define vs14 14
#define vs15 15
#define vs16 16
#define vs17 17
#define vs18 18
#define vs19 19
#define vs20 20
#define vs21 21
#define vs22 22
#define vs23 23
#define vs24 24
#define vs25 25
#define vs26 26
#define vs27 27
#define vs28 28
#define vs29 29
#define vs30 30
#define vs31 31
#define vs32 32
#define vs33 33
#define vs34 34
#define vs35 35
#define vs36 36
#define vs37 37
#define vs38 38
#define vs39 39
#define vs40 40
#define vs41 41
#define vs42 42
#define vs43 43
#define vs44 44
#define vs45 45
#define vs46 46
#define vs47 47
#define vs48 48
#define vs49 49
#define vs50 50
#define vs51 51
#define vs52 52
#define vs53 53
#define vs54 54
#define vs55 55
#define vs56 56
#define vs57 57
#define vs58 58
#define vs59 59
#define vs60 60
#define vs61 61
#define vs62 62
#define vs63 63
/* SPE Registers (EVPRs) */

33
arch/powerpc/include/asm/rtas.h
View File

@ -4,6 +4,7 @@
#include <linux/spinlock.h>
#include <asm/page.h>
#include <linux/time.h>
/*
* Definitions for talking to the RTAS on CHRP machines.
@ -273,6 +274,7 @@ inline uint32_t rtas_ext_event_company_id(struct rtas_ext_event_log_v6 *ext_log)
#define PSERIES_ELOG_SECT_ID_MANUFACT_INFO (('M' << 8) | 'I')
#define PSERIES_ELOG_SECT_ID_CALL_HOME (('C' << 8) | 'H')
#define PSERIES_ELOG_SECT_ID_USER_DEF (('U' << 8) | 'D')
#define PSERIES_ELOG_SECT_ID_HOTPLUG (('H' << 8) | 'P')
/* Vendor specific Platform Event Log Format, Version 6, section header */
struct pseries_errorlog {
@ -296,6 +298,31 @@ inline uint16_t pseries_errorlog_length(struct pseries_errorlog *sect)
return be16_to_cpu(sect->length);
}
/* RTAS pseries hotplug errorlog section */
struct pseries_hp_errorlog {
u8 resource;
u8 action;
u8 id_type;
u8 reserved;
union {
__be32 drc_index;
__be32 drc_count;
char drc_name[1];
} _drc_u;
};
#define PSERIES_HP_ELOG_RESOURCE_CPU 1
#define PSERIES_HP_ELOG_RESOURCE_MEM 2
#define PSERIES_HP_ELOG_RESOURCE_SLOT 3
#define PSERIES_HP_ELOG_RESOURCE_PHB 4
#define PSERIES_HP_ELOG_ACTION_ADD 1
#define PSERIES_HP_ELOG_ACTION_REMOVE 2
#define PSERIES_HP_ELOG_ID_DRC_NAME 1
#define PSERIES_HP_ELOG_ID_DRC_INDEX 2
#define PSERIES_HP_ELOG_ID_DRC_COUNT 3
struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log,
uint16_t section_id);
@ -327,7 +354,7 @@ extern int rtas_suspend_cpu(struct rtas_suspend_me_data *data);
extern int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data);
extern int rtas_online_cpus_mask(cpumask_var_t cpus);
extern int rtas_offline_cpus_mask(cpumask_var_t cpus);
extern int rtas_ibm_suspend_me(u64 handle, int *vasi_return);
extern int rtas_ibm_suspend_me(u64 handle);
struct rtc_time;
extern unsigned long rtas_get_boot_time(void);
@ -343,8 +370,12 @@ extern int early_init_dt_scan_rtas(unsigned long node,
extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
#ifdef CONFIG_PPC_PSERIES
extern time64_t last_rtas_event;
extern int clobbering_unread_rtas_event(void);
extern int pseries_devicetree_update(s32 scope);
extern void post_mobility_fixup(void);
#else
static inline int clobbering_unread_rtas_event(void) { return 0; }
#endif
#ifdef CONFIG_PPC_RTAS_DAEMON

1
arch/powerpc/include/asm/setup.h
View File

@ -7,7 +7,6 @@
extern void ppc_printk_progress(char *s, unsigned short hex);
extern unsigned int rtas_data;
extern int mem_init_done; /* set on boot once kmalloc can be called */
extern unsigned long long memory_limit;
extern unsigned long klimit;
extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);

5
arch/powerpc/include/asm/smp.h
View File

@ -42,7 +42,7 @@ struct smp_ops_t {
#ifdef CONFIG_PPC_SMP_MUXED_IPI
void (*cause_ipi)(int cpu, unsigned long data);
#endif
int (*probe)(void);
void (*probe)(void);
int (*kick_cpu)(int nr);
void (*setup_cpu)(int nr);
void (*bringup_done)(void);
@ -125,7 +125,6 @@ extern irqreturn_t smp_ipi_demux(void);
void smp_init_pSeries(void);
void smp_init_cell(void);
void smp_init_celleb(void);
void smp_setup_cpu_maps(void);
extern int __cpu_disable(void);
@ -175,7 +174,7 @@ static inline void set_hard_smp_processor_id(int cpu, int phys)
extern int smt_enabled_at_boot;
extern int smp_mpic_probe(void);
extern void smp_mpic_probe(void);
extern void smp_mpic_setup_cpu(int cpu);
extern int smp_generic_kick_cpu(int nr);
extern int smp_generic_cpu_bootable(unsigned int nr);

26
arch/powerpc/include/asm/swab.h
View File

@ -9,30 +9,4 @@
#include <uapi/asm/swab.h>
static __inline__ __u16 ld_le16(const volatile __u16 *addr)
{
__u16 val;
__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
return val;
}
static __inline__ void st_le16(volatile __u16 *addr, const __u16 val)
{
__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
}
static __inline__ __u32 ld_le32(const volatile __u32 *addr)
{
__u32 val;
__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
return val;
}
static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
{
__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
}
#endif /* _ASM_POWERPC_SWAB_H */

1
arch/powerpc/include/asm/systbl.h
View File

@ -367,3 +367,4 @@ SYSCALL_SPU(getrandom)
SYSCALL_SPU(memfd_create)
SYSCALL_SPU(bpf)
COMPAT_SYS(execveat)
PPC64ONLY(switch_endian)

13
arch/powerpc/include/asm/ucc_slow.h
View File

@ -251,19 +251,6 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
*/
void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
/* ucc_slow_poll_transmitter_now
* Immediately forces a poll of the transmitter for data to be sent.
* Typically, the hardware performs a periodic poll for data that the
* transmit routine has set up to be transmitted. In cases where
* this polling cycle is not soon enough, this optional routine can
* be invoked to force a poll right away, instead. Proper use for
* each transmission for which this functionality is desired is to
* call the transmit routine and then this routine right after.
*
* uccs - (In) pointer to the slow UCC structure.
*/
void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs);
/* ucc_slow_graceful_stop_tx
* Smoothly stops transmission on a specified slow UCC.
*

2
arch/powerpc/include/asm/unistd.h
View File

@ -12,7 +12,7 @@
#include <uapi/asm/unistd.h>
#define __NR_syscalls 363
#define __NR_syscalls 364
#define __NR__exit __NR_exit
#define NR_syscalls __NR_syscalls

4
arch/powerpc/include/asm/vga.h
View File

@ -25,12 +25,12 @@
static inline void scr_writew(u16 val, volatile u16 *addr)
{
st_le16(addr, val);
*addr = cpu_to_le16(val);
}
static inline u16 scr_readw(volatile const u16 *addr)
{
return ld_le16(addr);
return le16_to_cpu(*addr);
}
#define VT_BUF_HAVE_MEMCPYW

2
arch/powerpc/include/asm/xics.h
View File

@ -146,7 +146,7 @@ extern void xics_update_irq_servers(void);
extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join);
extern void xics_mask_unknown_vec(unsigned int vec);
extern irqreturn_t xics_ipi_dispatch(int cpu);
extern int xics_smp_probe(void);
extern void xics_smp_probe(void);
extern void xics_register_ics(struct ics *ics);
extern void xics_teardown_cpu(void);
extern void xics_kexec_teardown_cpu(int secondary);

2
arch/powerpc/include/uapi/asm/ptrace.h
View File

@ -136,7 +136,7 @@ struct pt_regs {
#endif /* __powerpc64__ */
/*
* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
* Get/set all the altivec registers v0..v31, vscr, vrsave, in one go.
* The transfer totals 34 quadword. Quadwords 0-31 contain the
* corresponding vector registers. Quadword 32 contains the vscr as the
* last word (offset 12) within that quadword. Quadword 33 contains the

2
arch/powerpc/include/uapi/asm/tm.h
View File

@ -11,7 +11,7 @@
#define TM_CAUSE_RESCHED 0xde
#define TM_CAUSE_TLBI 0xdc
#define TM_CAUSE_FAC_UNAV 0xda
#define TM_CAUSE_SYSCALL 0xd8 /* future use */
#define TM_CAUSE_SYSCALL 0xd8
#define TM_CAUSE_MISC 0xd6 /* future use */
#define TM_CAUSE_SIGNAL 0xd4
#define TM_CAUSE_ALIGNMENT 0xd2

1
arch/powerpc/include/uapi/asm/unistd.h
View File

@ -385,5 +385,6 @@
#define __NR_memfd_create 360
#define __NR_bpf 361
#define __NR_execveat 362
#define __NR_switch_endian 363
#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */

4
arch/powerpc/kernel/Makefile
View File

@ -33,7 +33,8 @@ obj-y := cputable.o ptrace.o syscalls.o \
signal.o sysfs.o cacheinfo.o time.o \
prom.o traps.o setup-common.o \
udbg.o misc.o io.o dma.o \
misc_$(CONFIG_WORD_SIZE).o vdso32/
misc_$(CONFIG_WORD_SIZE).o vdso32/ \
of_platform.o prom_parse.o
obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
signal_64.o ptrace32.o \
paca.o nvram_64.o firmware.o
@ -47,7 +48,6 @@ obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o
obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
obj-$(CONFIG_PPC_P7_NAP) += idle_power7.o
obj-$(CONFIG_PPC_OF) += of_platform.o prom_parse.o
procfs-y := proc_powerpc.o
obj-$(CONFIG_PROC_FS) += $(procfs-y)
rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI) := rtas_pci.o

44
arch/powerpc/kernel/cacheinfo.c
View File

@ -61,11 +61,21 @@ struct cache_type_info {
};
/* These are used to index the cache_type_info array. */
#define CACHE_TYPE_UNIFIED 0
#define CACHE_TYPE_INSTRUCTION 1
#define CACHE_TYPE_DATA 2
#define CACHE_TYPE_UNIFIED 0 /* cache-size, cache-block-size, etc. */
#define CACHE_TYPE_UNIFIED_D 1 /* d-cache-size, d-cache-block-size, etc */
#define CACHE_TYPE_INSTRUCTION 2
#define CACHE_TYPE_DATA 3
static const struct cache_type_info cache_type_info[] = {
{
/* Embedded systems that use cache-size, cache-block-size,
* etc. for the Unified (typically L2) cache. */
.name = "Unified",
.size_prop = "cache-size",
.line_size_props = { "cache-line-size",
"cache-block-size", },
.nr_sets_prop = "cache-sets",
},
{
/* PowerPC Processor binding says the [di]-cache-*
* must be equal on unified caches, so just use
@ -293,7 +303,8 @@ static struct cache *cache_find_first_sibling(struct cache *cache)
{
struct cache *iter;
if (cache->type == CACHE_TYPE_UNIFIED)
if (cache->type == CACHE_TYPE_UNIFIED ||
cache->type == CACHE_TYPE_UNIFIED_D)
return cache;
list_for_each_entry(iter, &cache_list, list)
@ -324,16 +335,29 @@ static bool cache_node_is_unified(const struct device_node *np)
return of_get_property(np, "cache-unified", NULL);
}
static struct cache *cache_do_one_devnode_unified(struct device_node *node,
int level)
/*
* Unified caches can have two different sets of tags. Most embedded
* use cache-size, etc. for the unified cache size, but open firmware systems
* use d-cache-size, etc. Check on initialization for which type we have, and
* return the appropriate structure type. Assume it's embedded if it isn't
* open firmware. If it's yet a 3rd type, then there will be missing entries
* in /sys/devices/system/cpu/cpu0/cache/index2/, and this code will need
* to be extended further.
*/
static int cache_is_unified_d(const struct device_node *np)
{
struct cache *cache;
return of_get_property(np,
cache_type_info[CACHE_TYPE_UNIFIED_D].size_prop, NULL) ?
CACHE_TYPE_UNIFIED_D : CACHE_TYPE_UNIFIED;
}
/*
*/
static struct cache *cache_do_one_devnode_unified(struct device_node *node, int level)
{
pr_debug("creating L%d ucache for %s\n", level, node->full_name);
cache = new_cache(CACHE_TYPE_UNIFIED, level, node);
return cache;
return new_cache(cache_is_unified_d(node), level, node);
}
static struct cache *cache_do_one_devnode_split(struct device_node *node,

10
arch/powerpc/kernel/cpu_setup_power.S
View File

@ -137,15 +137,11 @@ __init_HFSCR:
/*
* Clear the TLB using the specified IS form of tlbiel instruction
* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
*
* r3 = IS field
*/
__init_tlb_power7:
li r3,0xc00 /* IS field = 0b11 */
_GLOBAL(__flush_tlb_power7)
li r6,128
mtctr r6
mr r7,r3 /* IS field */
li r7,0xc00 /* IS field = 0b11 */
ptesync
2: tlbiel r7
addi r7,r7,0x1000
@ -154,11 +150,9 @@ _GLOBAL(__flush_tlb_power7)
1: blr
__init_tlb_power8:
li r3,0xc00 /* IS field = 0b11 */
_GLOBAL(__flush_tlb_power8)
li r6,512
mtctr r6
mr r7,r3 /* IS field */
li r7,0xc00 /* IS field = 0b11 */
ptesync
2: tlbiel r7
addi r7,r7,0x1000

4
arch/powerpc/kernel/cputable.c
View File

@ -71,8 +71,8 @@ extern void __restore_cpu_power7(void);
extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
extern void __restore_cpu_power8(void);
extern void __restore_cpu_a2(void);
extern void __flush_tlb_power7(unsigned long inval_selector);
extern void __flush_tlb_power8(unsigned long inval_selector);
extern void __flush_tlb_power7(unsigned int action);
extern void __flush_tlb_power8(unsigned int action);
extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
#endif /* CONFIG_PPC64 */

11
arch/powerpc/kernel/dma-swiotlb.c
View File

@ -116,16 +116,13 @@ void __init swiotlb_detect_4g(void)
}
}
static int __init swiotlb_late_init(void)
static int __init check_swiotlb_enabled(void)
{
if (ppc_swiotlb_enable) {
if (ppc_swiotlb_enable)
swiotlb_print_info();
set_pci_dma_ops(&swiotlb_dma_ops);
ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
} else {
else
swiotlb_free();
}
return 0;
}
subsys_initcall(swiotlb_late_init);
subsys_initcall(check_swiotlb_enabled);

176
arch/powerpc/kernel/eeh.c
View File

@ -164,30 +164,34 @@ __setup("eeh=", eeh_setup);
*/
static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
{
struct device_node *dn = eeh_dev_to_of_node(edev);
struct pci_dn *pdn = eeh_dev_to_pdn(edev);
u32 cfg;
int cap, i;
int n = 0, l = 0;
char buffer[128];
n += scnprintf(buf+n, len-n, "%s\n", dn->full_name);
pr_warn("EEH: of node=%s\n", dn->full_name);
n += scnprintf(buf+n, len-n, "%04x:%02x:%02x:%01x\n",
edev->phb->global_number, pdn->busno,
PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
pr_warn("EEH: of node=%04x:%02x:%02x:%01x\n",
edev->phb->global_number, pdn->busno,
PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg);
eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg);
eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);
n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
/* Gather bridge-specific registers */
if (edev->mode & EEH_DEV_BRIDGE) {
eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg);
eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg);
eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
pr_warn("EEH: Bridge control: %04x\n", cfg);
}
@ -195,11 +199,11 @@ static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
/* Dump out the PCI-X command and status regs */
cap = edev->pcix_cap;
if (cap) {
eeh_ops->read_config(dn, cap, 4, &cfg);
eeh_ops->read_config(pdn, cap, 4, &cfg);
n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
eeh_ops->read_config(dn, cap+4, 4, &cfg);
eeh_ops->read_config(pdn, cap+4, 4, &cfg);
n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
pr_warn("EEH: PCI-X status: %08x\n", cfg);
}
@ -211,7 +215,7 @@ static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
pr_warn("EEH: PCI-E capabilities and status follow:\n");
for (i=0; i<=8; i++) {
eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
if ((i % 4) == 0) {
@ -238,7 +242,7 @@ static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
pr_warn("EEH: PCI-E AER capability register set follows:\n");
for (i=0; i<=13; i++) {
eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
if ((i % 4) == 0) {
@ -414,11 +418,11 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
int ret;
int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
unsigned long flags;
struct device_node *dn;
struct pci_dn *pdn;
struct pci_dev *dev;
struct eeh_pe *pe, *parent_pe, *phb_pe;
int rc = 0;
const char *location;
const char *location = NULL;
eeh_stats.total_mmio_ffs++;
@ -429,15 +433,14 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
eeh_stats.no_dn++;
return 0;
}
dn = eeh_dev_to_of_node(edev);
dev = eeh_dev_to_pci_dev(edev);
pe = eeh_dev_to_pe(edev);
/* Access to IO BARs might get this far and still not want checking. */
if (!pe) {
eeh_stats.ignored_check++;
pr_debug("EEH: Ignored check for %s %s\n",
eeh_pci_name(dev), dn->full_name);
pr_debug("EEH: Ignored check for %s\n",
eeh_pci_name(dev));
return 0;
}
@ -473,10 +476,13 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
if (pe->state & EEH_PE_ISOLATED) {
pe->check_count++;
if (pe->check_count % EEH_MAX_FAILS == 0) {
location = of_get_property(dn, "ibm,loc-code", NULL);
pdn = eeh_dev_to_pdn(edev);
if (pdn->node)
location = of_get_property(pdn->node, "ibm,loc-code", NULL);
printk(KERN_ERR "EEH: %d reads ignored for recovering device at "
"location=%s driver=%s pci addr=%s\n",
pe->check_count, location,
pe->check_count,
location ? location : "unknown",
eeh_driver_name(dev), eeh_pci_name(dev));
printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n",
eeh_driver_name(dev));
@ -667,6 +673,55 @@ int eeh_pci_enable(struct eeh_pe *pe, int function)
return rc;
}
static void *eeh_disable_and_save_dev_state(void *data, void *userdata)
{
struct eeh_dev *edev = data;
struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
struct pci_dev *dev = userdata;
/*
* The caller should have disabled and saved the
* state for the specified device
*/
if (!pdev || pdev == dev)
return NULL;
/* Ensure we have D0 power state */
pci_set_power_state(pdev, PCI_D0);
/* Save device state */
pci_save_state(pdev);
/*
* Disable device to avoid any DMA traffic and
* interrupt from the device
*/
pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
return NULL;
}
static void *eeh_restore_dev_state(void *data, void *userdata)
{
struct eeh_dev *edev = data;
struct pci_dn *pdn = eeh_dev_to_pdn(edev);
struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
struct pci_dev *dev = userdata;
if (!pdev)
return NULL;
/* Apply customization from firmware */
if (pdn && eeh_ops->restore_config)
eeh_ops->restore_config(pdn);
/* The caller should restore state for the specified device */
if (pdev != dev)
pci_save_state(pdev);
return NULL;
}
/**
* pcibios_set_pcie_slot_reset - Set PCI-E reset state
* @dev: pci device struct
@ -689,13 +744,19 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state stat
switch (state) {
case pcie_deassert_reset:
eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
eeh_unfreeze_pe(pe, false);
eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
break;
case pcie_hot_reset:
eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
eeh_ops->reset(pe, EEH_RESET_HOT);
break;
case pcie_warm_reset:
eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
break;
@ -815,15 +876,15 @@ out:
*/
void eeh_save_bars(struct eeh_dev *edev)
{
struct pci_dn *pdn;
int i;
struct device_node *dn;
if (!edev)
pdn = eeh_dev_to_pdn(edev);
if (!pdn)
return;
dn = eeh_dev_to_of_node(edev);
for (i = 0; i < 16; i++)
eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]);
eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);
/*
* For PCI bridges including root port, we need enable bus
@ -914,7 +975,7 @@ static struct notifier_block eeh_reboot_nb = {
int eeh_init(void)
{
struct pci_controller *hose, *tmp;
struct device_node *phb;
struct pci_dn *pdn;
static int cnt = 0;
int ret = 0;
@ -949,20 +1010,9 @@ int eeh_init(void)
return ret;
/* Enable EEH for all adapters */
if (eeh_has_flag(EEH_PROBE_MODE_DEVTREE)) {
list_for_each_entry_safe(hose, tmp,
&hose_list, list_node) {
phb = hose->dn;
traverse_pci_devices(phb, eeh_ops->of_probe, NULL);
}
} else if (eeh_has_flag(EEH_PROBE_MODE_DEV)) {
list_for_each_entry_safe(hose, tmp,
&hose_list, list_node)
pci_walk_bus(hose->bus, eeh_ops->dev_probe, NULL);
} else {
pr_warn("%s: Invalid probe mode %x",
__func__, eeh_subsystem_flags);
return -EINVAL;
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
pdn = hose->pci_data;
traverse_pci_dn(pdn, eeh_ops->probe, NULL);
}
/*
@ -987,8 +1037,8 @@ int eeh_init(void)
core_initcall_sync(eeh_init);
/**
* eeh_add_device_early - Enable EEH for the indicated device_node
* @dn: device node for which to set up EEH
* eeh_add_device_early - Enable EEH for the indicated device node
* @pdn: PCI device node for which to set up EEH
*
* This routine must be used to perform EEH initialization for PCI
* devices that were added after system boot (e.g. hotplug, dlpar).
@ -998,44 +1048,41 @@ core_initcall_sync(eeh_init);
* on the CEC architecture, type of the device, on earlier boot
* command-line arguments & etc.
*/
void eeh_add_device_early(struct device_node *dn)
void eeh_add_device_early(struct pci_dn *pdn)
{
struct pci_controller *phb;
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
/*
* If we're doing EEH probe based on PCI device, we
* would delay the probe until late stage because
* the PCI device isn't available this moment.
*/
if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE))
if (!edev || !eeh_enabled())
return;
if (!of_node_to_eeh_dev(dn))
return;
phb = of_node_to_eeh_dev(dn)->phb;
/* USB Bus children of PCI devices will not have BUID's */
if (NULL == phb || 0 == phb->buid)
phb = edev->phb;
if (NULL == phb ||
(eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid))
return;
eeh_ops->of_probe(dn, NULL);
eeh_ops->probe(pdn, NULL);
}
/**
* eeh_add_device_tree_early - Enable EEH for the indicated device
* @dn: device node
* @pdn: PCI device node
*
* This routine must be used to perform EEH initialization for the
* indicated PCI device that was added after system boot (e.g.
* hotplug, dlpar).
*/
void eeh_add_device_tree_early(struct device_node *dn)
void eeh_add_device_tree_early(struct pci_dn *pdn)
{
struct device_node *sib;
struct pci_dn *n;
for_each_child_of_node(dn, sib)
eeh_add_device_tree_early(sib);
eeh_add_device_early(dn);
if (!pdn)
return;
list_for_each_entry(n, &pdn->child_list, list)
eeh_add_device_tree_early(n);
eeh_add_device_early(pdn);
}
EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
@ -1048,7 +1095,7 @@ EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
*/
void eeh_add_device_late(struct pci_dev *dev)
{
struct device_node *dn;
struct pci_dn *pdn;
struct eeh_dev *edev;
if (!dev || !eeh_enabled())
@ -1056,8 +1103,8 @@ void eeh_add_device_late(struct pci_dev *dev)
pr_debug("EEH: Adding device %s\n", pci_name(dev));
dn = pci_device_to_OF_node(dev);
edev = of_node_to_eeh_dev(dn);
pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
edev = pdn_to_eeh_dev(pdn);
if (edev->pdev == dev) {
pr_debug("EEH: Already referenced !\n");
return;
@ -1089,13 +1136,6 @@ void eeh_add_device_late(struct pci_dev *dev)
edev->pdev = dev;
dev->dev.archdata.edev = edev;
/*
* We have to do the EEH probe here because the PCI device
* hasn't been created yet in the early stage.
*/
if (eeh_has_flag(EEH_PROBE_MODE_DEV))
eeh_ops->dev_probe(dev, NULL);
eeh_addr_cache_insert_dev(dev);
}

25
arch/powerpc/kernel/eeh_cache.c
View File

@ -171,30 +171,27 @@ eeh_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
{
struct device_node *dn;
struct pci_dn *pdn;
struct eeh_dev *edev;
int i;
dn = pci_device_to_OF_node(dev);
if (!dn) {
pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
if (!pdn) {
pr_warn("PCI: no pci dn found for dev=%s\n",
pci_name(dev));
return;
}
edev = of_node_to_eeh_dev(dn);
edev = pdn_to_eeh_dev(pdn);
if (!edev) {
pr_warn("PCI: no EEH dev found for dn=%s\n",
dn->full_name);
pr_warn("PCI: no EEH dev found for %s\n",
pci_name(dev));
return;
}
/* Skip any devices for which EEH is not enabled. */
if (!edev->pe) {
#ifdef DEBUG
pr_info("PCI: skip building address cache for=%s - %s\n",
pci_name(dev), dn->full_name);
#endif
dev_dbg(&dev->dev, "EEH: Skip building address cache\n");
return;
}
@ -282,18 +279,18 @@ void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
*/
void eeh_addr_cache_build(void)
{
struct device_node *dn;
struct pci_dn *pdn;
struct eeh_dev *edev;
struct pci_dev *dev = NULL;
spin_lock_init(&pci_io_addr_cache_root.piar_lock);
for_each_pci_dev(dev) {
dn = pci_device_to_OF_node(dev);
if (!dn)
pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
if (!pdn)
continue;
edev = of_node_to_eeh_dev(dn);
edev = pdn_to_eeh_dev(pdn);
if (!edev)
continue;

14
arch/powerpc/kernel/eeh_dev.c
View File

@ -43,13 +43,13 @@
/**
* eeh_dev_init - Create EEH device according to OF node
* @dn: device node
* @pdn: PCI device node
* @data: PHB
*
* It will create EEH device according to the given OF node. The function
* might be called by PCI emunation, DR, PHB hotplug.
*/
void *eeh_dev_init(struct device_node *dn, void *data)
void *eeh_dev_init(struct pci_dn *pdn, void *data)
{
struct pci_controller *phb = data;
struct eeh_dev *edev;
@ -63,8 +63,8 @@ void *eeh_dev_init(struct device_node *dn, void *data)
}
/* Associate EEH device with OF node */
PCI_DN(dn)->edev = edev;
edev->dn = dn;
pdn->edev = edev;
edev->pdn = pdn;
edev->phb = phb;
INIT_LIST_HEAD(&edev->list);
@ -80,16 +80,16 @@ void *eeh_dev_init(struct device_node *dn, void *data)
*/
void eeh_dev_phb_init_dynamic(struct pci_controller *phb)
{
struct device_node *dn = phb->dn;
struct pci_dn *root = phb->pci_data;
/* EEH PE for PHB */
eeh_phb_pe_create(phb);
/* EEH device for PHB */
eeh_dev_init(dn, phb);
eeh_dev_init(root, phb);
/* EEH devices for children OF nodes */
traverse_pci_devices(dn, eeh_dev_init, phb);
traverse_pci_dn(root, eeh_dev_init, phb);
}
/**

22
arch/powerpc/kernel/eeh_driver.c
View File

@ -83,28 +83,6 @@ static inline void eeh_pcid_put(struct pci_dev *pdev)
module_put(pdev->driver->driver.owner);
}
#if 0
static void print_device_node_tree(struct pci_dn *pdn, int dent)
{
int i;
struct device_node *pc;
if (!pdn)
return;
for (i = 0; i < dent; i++)
printk(" ");
printk("dn=%s mode=%x \tcfg_addr=%x pe_addr=%x \tfull=%s\n",
pdn->node->name, pdn->eeh_mode, pdn->eeh_config_addr,
pdn->eeh_pe_config_addr, pdn->node->full_name);
dent += 3;
pc = pdn->node->child;
while (pc) {
print_device_node_tree(PCI_DN(pc), dent);
pc = pc->sibling;
}
}
#endif
/**
* eeh_disable_irq - Disable interrupt for the recovering device
* @dev: PCI device

129
arch/powerpc/kernel/eeh_pe.c
View File

@ -291,27 +291,25 @@ struct eeh_pe *eeh_pe_get(struct eeh_dev *edev)
*/
static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
{
struct device_node *dn;
struct eeh_dev *parent;
struct pci_dn *pdn = eeh_dev_to_pdn(edev);
/*
* It might have the case for the indirect parent
* EEH device already having associated PE, but
* the direct parent EEH device doesn't have yet.
*/
dn = edev->dn->parent;
while (dn) {
pdn = pdn ? pdn->parent : NULL;
while (pdn) {
/* We're poking out of PCI territory */
if (!PCI_DN(dn)) return NULL;
parent = of_node_to_eeh_dev(dn);
/* We're poking out of PCI territory */
if (!parent) return NULL;
parent = pdn_to_eeh_dev(pdn);
if (!parent)
return NULL;
if (parent->pe)
return parent->pe;
dn = dn->parent;
pdn = pdn->parent;
}
return NULL;
@ -330,6 +328,13 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
{
struct eeh_pe *pe, *parent;
/* Check if the PE number is valid */
if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%d\n",
__func__, edev->config_addr, edev->phb->global_number);
return -EINVAL;
}
/*
* Search the PE has been existing or not according
* to the PE address. If that has been existing, the
@ -338,21 +343,18 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
*/
pe = eeh_pe_get(edev);
if (pe && !(pe->type & EEH_PE_INVALID)) {
if (!edev->pe_config_addr) {
pr_err("%s: PE with addr 0x%x already exists\n",
__func__, edev->config_addr);
return -EEXIST;
}
/* Mark the PE as type of PCI bus */
pe->type = EEH_PE_BUS;
edev->pe = pe;
/* Put the edev to PE */
list_add_tail(&edev->list, &pe->edevs);
pr_debug("EEH: Add %s to Bus PE#%x\n",
edev->dn->full_name, pe->addr);
pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
edev->phb->global_number,
edev->config_addr >> 8,
PCI_SLOT(edev->config_addr & 0xFF),
PCI_FUNC(edev->config_addr & 0xFF),
pe->addr);
return 0;
} else if (pe && (pe->type & EEH_PE_INVALID)) {
list_add_tail(&edev->list, &pe->edevs);
@ -368,9 +370,14 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
parent->type &= ~(EEH_PE_INVALID | EEH_PE_KEEP);
parent = parent->parent;
}
pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n",
edev->dn->full_name, pe->addr, pe->parent->addr);
pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
"PE#%x, Parent PE#%x\n",
edev->phb->global_number,
edev->config_addr >> 8,
PCI_SLOT(edev->config_addr & 0xFF),
PCI_FUNC(edev->config_addr & 0xFF),
pe->addr, pe->parent->addr);
return 0;
}
@ -409,8 +416,13 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
list_add_tail(&pe->child, &parent->child_list);
list_add_tail(&edev->list, &pe->edevs);
edev->pe = pe;
pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n",
edev->dn->full_name, pe->addr, pe->parent->addr);
pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
"Device PE#%x, Parent PE#%x\n",
edev->phb->global_number,
edev->config_addr >> 8,
PCI_SLOT(edev->config_addr & 0xFF),
PCI_FUNC(edev->config_addr & 0xFF),
pe->addr, pe->parent->addr);
return 0;
}
@ -430,8 +442,11 @@ int eeh_rmv_from_parent_pe(struct eeh_dev *edev)
int cnt;
if (!edev->pe) {
pr_debug("%s: No PE found for EEH device %s\n",
__func__, edev->dn->full_name);
pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
__func__, edev->phb->global_number,
edev->config_addr >> 8,
PCI_SLOT(edev->config_addr & 0xFF),
PCI_FUNC(edev->config_addr & 0xFF));
return -EEXIST;
}
@ -653,9 +668,9 @@ void eeh_pe_state_clear(struct eeh_pe *pe, int state)
* blocked on normal path during the stage. So we need utilize
* eeh operations, which is always permitted.
*/
static void eeh_bridge_check_link(struct eeh_dev *edev,
struct device_node *dn)
static void eeh_bridge_check_link(struct eeh_dev *edev)
{
struct pci_dn *pdn = eeh_dev_to_pdn(edev);
int cap;
uint32_t val;
int timeout = 0;
@ -675,32 +690,32 @@ static void eeh_bridge_check_link(struct eeh_dev *edev,
/* Check slot status */
cap = edev->pcie_cap;
eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val);
eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
if (!(val & PCI_EXP_SLTSTA_PDS)) {
pr_debug(" No card in the slot (0x%04x) !\n", val);
return;
}
/* Check power status if we have the capability */
eeh_ops->read_config(dn, cap + PCI_EXP_SLTCAP, 2, &val);
eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
if (val & PCI_EXP_SLTCAP_PCP) {
eeh_ops->read_config(dn, cap + PCI_EXP_SLTCTL, 2, &val);
eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
if (val & PCI_EXP_SLTCTL_PCC) {
pr_debug(" In power-off state, power it on ...\n");
val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
eeh_ops->write_config(dn, cap + PCI_EXP_SLTCTL, 2, val);
eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
msleep(2 * 1000);
}
}
/* Enable link */
eeh_ops->read_config(dn, cap + PCI_EXP_LNKCTL, 2, &val);
eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
val &= ~PCI_EXP_LNKCTL_LD;
eeh_ops->write_config(dn, cap + PCI_EXP_LNKCTL, 2, val);
eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
/* Check link */
eeh_ops->read_config(dn, cap + PCI_EXP_LNKCAP, 4, &val);
eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
pr_debug(" No link reporting capability (0x%08x) \n", val);
msleep(1000);
@ -713,7 +728,7 @@ static void eeh_bridge_check_link(struct eeh_dev *edev,
msleep(20);
timeout += 20;
eeh_ops->read_config(dn, cap + PCI_EXP_LNKSTA, 2, &val);
eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
if (val & PCI_EXP_LNKSTA_DLLLA)
break;
}
@ -728,9 +743,9 @@ static void eeh_bridge_check_link(struct eeh_dev *edev,
#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
static void eeh_restore_bridge_bars(struct eeh_dev *edev,
struct device_node *dn)
static void eeh_restore_bridge_bars(struct eeh_dev *edev)
{
struct pci_dn *pdn = eeh_dev_to_pdn(edev);
int i;
/*
@ -738,49 +753,49 @@ static void eeh_restore_bridge_bars(struct eeh_dev *edev,
* Bus numbers and windows: 0x18 - 0x30
*/
for (i = 4; i < 13; i++)
eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
/* Rom: 0x38 */
eeh_ops->write_config(dn, 14*4, 4, edev->config_space[14]);
eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
/* Cache line & Latency timer: 0xC 0xD */
eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
SAVED_BYTE(PCI_CACHE_LINE_SIZE));
eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
SAVED_BYTE(PCI_LATENCY_TIMER));
/* Max latency, min grant, interrupt ping and line: 0x3C */
eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
/* PCI Command: 0x4 */
eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]);
eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1]);
/* Check the PCIe link is ready */
eeh_bridge_check_link(edev, dn);
eeh_bridge_check_link(edev);
}
static void eeh_restore_device_bars(struct eeh_dev *edev,
struct device_node *dn)
static void eeh_restore_device_bars(struct eeh_dev *edev)
{
struct pci_dn *pdn = eeh_dev_to_pdn(edev);
int i;
u32 cmd;
for (i = 4; i < 10; i++)
eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
/* 12 == Expansion ROM Address */
eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
SAVED_BYTE(PCI_CACHE_LINE_SIZE));
eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
SAVED_BYTE(PCI_LATENCY_TIMER));
/* max latency, min grant, interrupt pin and line */
eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
/*
* Restore PERR & SERR bits, some devices require it,
* don't touch the other command bits
*/
eeh_ops->read_config(dn, PCI_COMMAND, 4, &cmd);
eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
if (edev->config_space[1] & PCI_COMMAND_PARITY)
cmd |= PCI_COMMAND_PARITY;
else
@ -789,7 +804,7 @@ static void eeh_restore_device_bars(struct eeh_dev *edev,
cmd |= PCI_COMMAND_SERR;
else
cmd &= ~PCI_COMMAND_SERR;
eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
}
/**
@ -804,16 +819,16 @@ static void eeh_restore_device_bars(struct eeh_dev *edev,
static void *eeh_restore_one_device_bars(void *data, void *flag)
{
struct eeh_dev *edev = (struct eeh_dev *)data;
struct device_node *dn = eeh_dev_to_of_node(edev);
struct pci_dn *pdn = eeh_dev_to_pdn(edev);
/* Do special restore for bridges */
if (edev->mode & EEH_DEV_BRIDGE)
eeh_restore_bridge_bars(edev, dn);
eeh_restore_bridge_bars(edev);
else
eeh_restore_device_bars(edev, dn);
eeh_restore_device_bars(edev);
if (eeh_ops->restore_config)
eeh_ops->restore_config(dn);
if (eeh_ops->restore_config && pdn)
eeh_ops->restore_config(pdn);
return NULL;
}

24
arch/powerpc/kernel/entry_64.S
View File

@ -34,6 +34,7 @@
#include <asm/ftrace.h>
#include <asm/hw_irq.h>
#include <asm/context_tracking.h>
#include <asm/tm.h>
/*
* System calls.
@ -145,6 +146,24 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
andi. r11,r10,_TIF_SYSCALL_DOTRACE
bne syscall_dotrace
.Lsyscall_dotrace_cont:
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
BEGIN_FTR_SECTION
b 1f
END_FTR_SECTION_IFCLR(CPU_FTR_TM)
extrdi. r11, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
beq+ 1f
/* Doom the transaction and don't perform the syscall: */
mfmsr r11
li r12, 1
rldimi r11, r12, MSR_TM_LG, 63-MSR_TM_LG
mtmsrd r11, 0
li r11, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
TABORT(R11)
b .Lsyscall_exit
1:
#endif
cmpldi 0,r0,NR_syscalls
bge- syscall_enosys
@ -356,6 +375,11 @@ _GLOBAL(ppc64_swapcontext)
bl sys_swapcontext
b .Lsyscall_exit
_GLOBAL(ppc_switch_endian)
bl save_nvgprs
bl sys_switch_endian
b .Lsyscall_exit
_GLOBAL(ret_from_fork)
bl schedule_tail
REST_NVGPRS(r1)

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