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Merge branches 'arm', 'at91', 'ep93xx', 'iop', 'ks8695', 'misc', 'mxc', 'ns9x', 'orion', 'pxa', 'sa1100', 's3c' and 'sparsemem' into devel

Browse Source
This commit is contained in:
Russell King 2008-04-19 17:17:25 +01:00 committed by Russell King
commit d1964dab60
287 changed files with 21741 additions and 7098 deletions
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6
MAINTAINERS
View File

@ -480,6 +480,12 @@ M: kernel@wantstofly.org
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/GUMSTIX MACHINE SUPPORT
P: Steve Sakoman
M: sakoman@gmail.com
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/HP JORNADA 7XX MACHINE SUPPORT
P: Kristoffer Ericson
M: kristoffer.ericson@gmail.com

23
arch/arm/Kconfig
View File

@ -255,6 +255,7 @@ config ARCH_EP93XX
select ARM_AMBA
select ARM_VIC
select GENERIC_GPIO
select HAVE_GPIO_LIB
help
This enables support for the Cirrus EP93xx series of CPUs.
@ -377,15 +378,17 @@ config ARCH_MXC
help
Support for Freescale MXC/iMX-based family of processors
config ARCH_ORION
config ARCH_ORION5X
bool "Marvell Orion"
depends on MMU
select PCI
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select PLAT_ORION
help
Support for Marvell Orion System on Chip family.
Support for the following Marvell Orion 5x series SoCs:
Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.)
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
@ -422,10 +425,15 @@ config ARCH_SA1100
bool "SA1100-based"
select ISA
select ARCH_DISCONTIGMEM_ENABLE
select ARCH_SPARSEMEM_ENABLE
select ARCH_SELECT_MEMORY_MODEL
select ARCH_MTD_XIP
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select TICK_ONESHOT
select HAVE_IDE
select HAVE_GPIO_LIB
help
Support for StrongARM 11x0 based boards.
@ -516,7 +524,7 @@ source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-orion/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
@ -563,6 +571,9 @@ config ARCH_ACORN
config PLAT_IOP
bool
config PLAT_ORION
bool
source arch/arm/mm/Kconfig
config IWMMXT
@ -774,6 +785,12 @@ config ARCH_DISCONTIGMEM_ENABLE
or have huge holes in the physical address space for other reasons.
See <file:Documentation/vm/numa> for more.
config ARCH_SPARSEMEM_ENABLE
bool
config ARCH_SELECT_MEMORY_MODEL
bool
config NODES_SHIFT
int
default "4" if ARCH_LH7A40X

4
arch/arm/Makefile
View File

@ -134,12 +134,11 @@ endif
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000
machine-$(CONFIG_ARCH_DAVINCI) := davinci
machine-$(CONFIG_ARCH_KS8695) := ks8695
incdir-$(CONFIG_ARCH_MXC) := mxc
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_ORION) := orion
machine-$(CONFIG_ARCH_ORION5X) := orion5x
machine-$(CONFIG_ARCH_MSM7X00A) := msm
ifeq ($(CONFIG_ARCH_EBSA110),y)
@ -185,6 +184,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/
# If we have a common platform directory, then include it in the build.
core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/
core-$(CONFIG_PLAT_ORION) += arch/arm/plat-orion/
core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/
core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/
core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/

8
arch/arm/boot/Makefile
View File

@ -61,9 +61,15 @@ endif
quiet_cmd_uimage = UIMAGE $@
cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
-C none -a $(ZRELADDR) -e $(ZRELADDR) \
-C none -a $(LOADADDR) -e $(LOADADDR) \
-n 'Linux-$(KERNELRELEASE)' -d $< $@
ifeq ($(CONFIG_ZBOOT_ROM),y)
$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
else
$(obj)/uImage: LOADADDR=$(ZRELADDR)
endif
$(obj)/uImage: $(obj)/zImage FORCE
$(call if_changed,uimage)
@echo ' Image $@ is ready'

183
arch/arm/common/scoop.c
View File

@ -16,6 +16,7 @@
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/hardware/scoop.h>
/* PCMCIA to Scoop linkage
@ -30,10 +31,9 @@
struct scoop_pcmcia_config *platform_scoop_config;
EXPORT_SYMBOL(platform_scoop_config);
#define SCOOP_REG(d,adr) (*(volatile unsigned short*)(d +(adr)))
struct scoop_dev {
void *base;
void __iomem *base;
struct gpio_chip gpio;
spinlock_t scoop_lock;
unsigned short suspend_clr;
unsigned short suspend_set;
@ -44,13 +44,84 @@ void reset_scoop(struct device *dev)
{
struct scoop_dev *sdev = dev_get_drvdata(dev);
SCOOP_REG(sdev->base,SCOOP_MCR) = 0x0100; // 00
SCOOP_REG(sdev->base,SCOOP_CDR) = 0x0000; // 04
SCOOP_REG(sdev->base,SCOOP_CCR) = 0x0000; // 10
SCOOP_REG(sdev->base,SCOOP_IMR) = 0x0000; // 18
SCOOP_REG(sdev->base,SCOOP_IRM) = 0x00FF; // 14
SCOOP_REG(sdev->base,SCOOP_ISR) = 0x0000; // 1C
SCOOP_REG(sdev->base,SCOOP_IRM) = 0x0000;
iowrite16(0x0100, sdev->base + SCOOP_MCR); // 00
iowrite16(0x0000, sdev->base + SCOOP_CDR); // 04
iowrite16(0x0000, sdev->base + SCOOP_CCR); // 10
iowrite16(0x0000, sdev->base + SCOOP_IMR); // 18
iowrite16(0x00FF, sdev->base + SCOOP_IRM); // 14
iowrite16(0x0000, sdev->base + SCOOP_ISR); // 1C
iowrite16(0x0000, sdev->base + SCOOP_IRM);
}
static void __scoop_gpio_set(struct scoop_dev *sdev,
unsigned offset, int value)
{
unsigned short gpwr;
gpwr = ioread16(sdev->base + SCOOP_GPWR);
if (value)
gpwr |= 1 << (offset + 1);
else
gpwr &= ~(1 << (offset + 1));
iowrite16(gpwr, sdev->base + SCOOP_GPWR);
}
static void scoop_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
unsigned long flags;
spin_lock_irqsave(&sdev->scoop_lock, flags);
__scoop_gpio_set(sdev, offset, value);
spin_unlock_irqrestore(&sdev->scoop_lock, flags);
}
static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
/* XXX: I'm usure, but it seems so */
return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1));
}
static int scoop_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
unsigned long flags;
unsigned short gpcr;
spin_lock_irqsave(&sdev->scoop_lock, flags);
gpcr = ioread16(sdev->base + SCOOP_GPCR);
gpcr &= ~(1 << (offset + 1));
iowrite16(gpcr, sdev->base + SCOOP_GPCR);
spin_unlock_irqrestore(&sdev->scoop_lock, flags);
return 0;
}
static int scoop_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
unsigned long flags;
unsigned short gpcr;
spin_lock_irqsave(&sdev->scoop_lock, flags);
__scoop_gpio_set(sdev, offset, value);
gpcr = ioread16(sdev->base + SCOOP_GPCR);
gpcr |= 1 << (offset + 1);
iowrite16(gpcr, sdev->base + SCOOP_GPCR);
spin_unlock_irqrestore(&sdev->scoop_lock, flags);
return 0;
}
unsigned short set_scoop_gpio(struct device *dev, unsigned short bit)
@ -60,8 +131,8 @@ unsigned short set_scoop_gpio(struct device *dev, unsigned short bit)
struct scoop_dev *sdev = dev_get_drvdata(dev);
spin_lock_irqsave(&sdev->scoop_lock, flag);
gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) | bit;
SCOOP_REG(sdev->base, SCOOP_GPWR) = gpio_bit;
gpio_bit = ioread16(sdev->base + SCOOP_GPWR) | bit;
iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
spin_unlock_irqrestore(&sdev->scoop_lock, flag);
return gpio_bit;
@ -74,8 +145,8 @@ unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit)
struct scoop_dev *sdev = dev_get_drvdata(dev);
spin_lock_irqsave(&sdev->scoop_lock, flag);
gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) & ~bit;
SCOOP_REG(sdev->base,SCOOP_GPWR) = gpio_bit;
gpio_bit = ioread16(sdev->base + SCOOP_GPWR) & ~bit;
iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
spin_unlock_irqrestore(&sdev->scoop_lock, flag);
return gpio_bit;
@ -87,13 +158,13 @@ EXPORT_SYMBOL(reset_scoop_gpio);
unsigned short read_scoop_reg(struct device *dev, unsigned short reg)
{
struct scoop_dev *sdev = dev_get_drvdata(dev);
return SCOOP_REG(sdev->base,reg);
return ioread16(sdev->base + reg);
}
void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data)
{
struct scoop_dev *sdev = dev_get_drvdata(dev);
SCOOP_REG(sdev->base,reg)=data;
iowrite16(data, sdev->base + reg);
}
EXPORT_SYMBOL(reset_scoop);
@ -104,9 +175,9 @@ static void check_scoop_reg(struct scoop_dev *sdev)
{
unsigned short mcr;
mcr = SCOOP_REG(sdev->base, SCOOP_MCR);
mcr = ioread16(sdev->base + SCOOP_MCR);
if ((mcr & 0x100) == 0)
SCOOP_REG(sdev->base, SCOOP_MCR) = 0x0101;
iowrite16(0x0101, sdev->base + SCOOP_MCR);
}
#ifdef CONFIG_PM
@ -115,8 +186,8 @@ static int scoop_suspend(struct platform_device *dev, pm_message_t state)
struct scoop_dev *sdev = platform_get_drvdata(dev);
check_scoop_reg(sdev);
sdev->scoop_gpwr = SCOOP_REG(sdev->base, SCOOP_GPWR);
SCOOP_REG(sdev->base, SCOOP_GPWR) = (sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set;
sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR);
iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR);
return 0;
}
@ -126,7 +197,7 @@ static int scoop_resume(struct platform_device *dev)
struct scoop_dev *sdev = platform_get_drvdata(dev);
check_scoop_reg(sdev);
SCOOP_REG(sdev->base,SCOOP_GPWR) = sdev->scoop_gpwr;
iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR);
return 0;
}
@ -135,11 +206,13 @@ static int scoop_resume(struct platform_device *dev)
#define scoop_resume NULL
#endif
int __init scoop_probe(struct platform_device *pdev)
static int __devinit scoop_probe(struct platform_device *pdev)
{
struct scoop_dev *devptr;
struct scoop_config *inf;
struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
int ret;
int temp;
if (!mem)
return -EINVAL;
@ -154,40 +227,78 @@ int __init scoop_probe(struct platform_device *pdev)
devptr->base = ioremap(mem->start, mem->end - mem->start + 1);
if (!devptr->base) {
kfree(devptr);
return -ENOMEM;
ret = -ENOMEM;
goto err_ioremap;
}
platform_set_drvdata(pdev, devptr);
printk("Sharp Scoop Device found at 0x%08x -> 0x%08x\n",(unsigned int)mem->start,(unsigned int)devptr->base);
printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base);
SCOOP_REG(devptr->base, SCOOP_MCR) = 0x0140;
iowrite16(0x0140, devptr->base + SCOOP_MCR);
reset_scoop(&pdev->dev);
SCOOP_REG(devptr->base, SCOOP_CPR) = 0x0000;
SCOOP_REG(devptr->base, SCOOP_GPCR) = inf->io_dir & 0xffff;
SCOOP_REG(devptr->base, SCOOP_GPWR) = inf->io_out & 0xffff;
iowrite16(0x0000, devptr->base + SCOOP_CPR);
iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR);
iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR);
devptr->suspend_clr = inf->suspend_clr;
devptr->suspend_set = inf->suspend_set;
devptr->gpio.base = -1;
if (inf->gpio_base != 0) {
devptr->gpio.label = pdev->dev.bus_id;
devptr->gpio.base = inf->gpio_base;
devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */
devptr->gpio.set = scoop_gpio_set;
devptr->gpio.get = scoop_gpio_get;
devptr->gpio.direction_input = scoop_gpio_direction_input;
devptr->gpio.direction_output = scoop_gpio_direction_output;
ret = gpiochip_add(&devptr->gpio);
if (ret)
goto err_gpio;
}
return 0;
if (devptr->gpio.base != -1)
temp = gpiochip_remove(&devptr->gpio);
err_gpio:
platform_set_drvdata(pdev, NULL);
err_ioremap:
iounmap(devptr->base);
kfree(devptr);
return ret;
}
static int scoop_remove(struct platform_device *pdev)
static int __devexit scoop_remove(struct platform_device *pdev)
{
struct scoop_dev *sdev = platform_get_drvdata(pdev);
if (sdev) {
iounmap(sdev->base);
kfree(sdev);
platform_set_drvdata(pdev, NULL);
int ret;
if (!sdev)
return -EINVAL;
if (sdev->gpio.base != -1) {
ret = gpiochip_remove(&sdev->gpio);
if (ret) {
dev_err(&pdev->dev, "Can't remove gpio chip: %d\n", ret);
return ret;
}
}
platform_set_drvdata(pdev, NULL);
iounmap(sdev->base);
kfree(sdev);
return 0;
}
static struct platform_driver scoop_driver = {
.probe = scoop_probe,
.remove = scoop_remove,
.remove = __devexit_p(scoop_remove),
.suspend = scoop_suspend,
.resume = scoop_resume,
.driver = {
@ -195,7 +306,7 @@ static struct platform_driver scoop_driver = {
},
};
int __init scoop_init(void)
static int __init scoop_init(void)
{
return platform_driver_register(&scoop_driver);
}

1149
arch/arm/configs/am200epdkit_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/configs/at91rm9200dk_defconfig
View File

@ -620,14 +620,14 @@ CONFIG_I2C_CHARDEV=y
#
# I2C Algorithms
#
# CONFIG_I2C_ALGOBIT is not set
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
CONFIG_I2C_AT91=y
CONFIG_I2C_GPIO=y
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_PCA_ISA is not set

4
arch/arm/configs/at91rm9200ek_defconfig
View File

@ -594,14 +594,14 @@ CONFIG_I2C_CHARDEV=y
#
# I2C Algorithms
#
# CONFIG_I2C_ALGOBIT is not set
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
CONFIG_I2C_AT91=y
CONFIG_I2C_GPIO=y
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_PCA_ISA is not set

534
arch/arm/configs/at91sam9260ek_defconfig
View File

@ -1,43 +1,56 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.19-rc6
# Fri Nov 17 18:42:21 2006
# Linux kernel version: 2.6.24-rc7
# Tue Jan 8 22:20:50 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
@ -53,30 +66,30 @@ CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
@ -108,12 +121,16 @@ CONFIG_ARCH_AT91=y
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
@ -121,29 +138,52 @@ CONFIG_ARCH_AT91=y
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
#
# Boot options
#
#
# Power management
#
#
# Atmel AT91 System-on-Chip
#
# CONFIG_ARCH_AT91RM9200 is not set
CONFIG_ARCH_AT91SAM9260=y
# CONFIG_ARCH_AT91SAM9261 is not set
# CONFIG_ARCH_AT91SAM9263 is not set
# CONFIG_ARCH_AT91SAM9RL is not set
# CONFIG_ARCH_AT91X40 is not set
CONFIG_AT91_PMC_UNIT=y
#
# AT91SAM9260 Board Type
# AT91SAM9260 Variants
#
# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
#
# AT91SAM9260 / AT91SAM9XE Board Type
#
CONFIG_MACH_AT91SAM9260EK=y
# CONFIG_MACH_CAM60 is not set
# CONFIG_MACH_SAM9_L9260 is not set
#
# AT91 Board Options
#
# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
#
# AT91 Feature Selections
#
# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ATMEL_TCLIB is not set
CONFIG_AT91_TIMER_HZ=100
#
# Processor Type
@ -166,19 +206,19 @@ CONFIG_CPU_CP15_MMU=y
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
# CONFIG_OUTER_CACHE is not set
#
# Bus support
#
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
# CONFIG_TICK_ONESHOT is not set
# CONFIG_PREEMPT is not set
# CONFIG_NO_IDLE_HZ is not set
CONFIG_HZ=100
@ -191,8 +231,12 @@ CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
@ -203,6 +247,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# Floating point emulation
@ -228,7 +273,7 @@ CONFIG_BINFMT_ELF=y
# Power management options
#
# CONFIG_PM is not set
# CONFIG_APM is not set
CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
@ -238,13 +283,9 @@ CONFIG_NET=y
#
# Networking options
#
# CONFIG_NETDEBUG is not set
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
@ -263,33 +304,23 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
#
# DCCP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_DCCP is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
#
# TIPC Configuration (EXPERIMENTAL)
#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
@ -302,10 +333,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
@ -315,7 +342,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
@ -324,34 +361,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
#
# Block devices
#
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
@ -360,15 +380,19 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
CONFIG_ATMEL_SSC=y
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
@ -388,6 +412,8 @@ CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
@ -395,43 +421,72 @@ CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
#
# SCSI low-level drivers
#
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
CONFIG_PHYLIB=y
#
# Fusion MPT device support
# MII PHY device drivers
#
# CONFIG_FUSION is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_MACB=y
# CONFIG_AX88796 is not set
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
#
# IEEE 1394 (FireWire) support
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
#
# I2O device support
# USB Network Adapters
#
#
# Network device support
#
# CONFIG_NETDEVICES is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
@ -439,6 +494,7 @@ CONFIG_SCSI_MULTI_LUN=y
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
@ -448,7 +504,6 @@ CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
@ -458,6 +513,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
@ -492,15 +548,60 @@ CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
#
# Watchdog Cards
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
CONFIG_I2C_GPIO=y
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_TINY_USB is not set
# CONFIG_I2C_PCA is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_DS1337 is not set
# CONFIG_SENSORS_DS1374 is not set
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
@ -508,98 +609,70 @@ CONFIG_WATCHDOG_NOWAYOUT=y
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_AT91SAM9_WATCHDOG=y
#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
#
# Ftape, the floppy tape device driver
# Sonics Silicon Backplane
#
# CONFIG_RAW_DRIVER is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
# CONFIG_HWMON is not set
# CONFIG_HWMON_VID is not set
#
# Misc devices
#
# CONFIG_TIFM_CORE is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
# CONFIG_USB_DABUSB is not set
# CONFIG_DVB_CORE is not set
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
# CONFIG_HIDRAW is not set
#
# USB support
# USB Input Devices
#
# CONFIG_USB_HID is not set
#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
@ -610,7 +683,7 @@ CONFIG_USB=y
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_BANDWIDTH is not set
CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
@ -619,9 +692,11 @@ CONFIG_USB_DEVICEFS=y
#
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_BIG_ENDIAN is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
@ -640,6 +715,7 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DEBUG=y
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
@ -649,44 +725,11 @@ CONFIG_USB_STORAGE_DEBUG=y
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_LIBUSUAL is not set
#
# USB Input Devices
#
# CONFIG_USB_HID is not set
#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
# CONFIG_USB_AIPTEK is not set
# CONFIG_USB_WACOM is not set
# CONFIG_USB_ACECAD is not set
# CONFIG_USB_KBTAB is not set
# CONFIG_USB_POWERMATE is not set
# CONFIG_USB_TOUCHSCREEN is not set
# CONFIG_USB_YEALINK is not set
# CONFIG_USB_XPAD is not set
# CONFIG_USB_ATI_REMOTE is not set
# CONFIG_USB_ATI_REMOTE2 is not set
# CONFIG_USB_KEYSPAN_REMOTE is not set
# CONFIG_USB_APPLETOUCH is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET_MII is not set
# CONFIG_USB_USBNET is not set
CONFIG_USB_MON=y
#
@ -708,6 +751,7 @@ CONFIG_USB_MON=y
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
@ -717,6 +761,7 @@ CONFIG_USB_MON=y
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
#
@ -727,13 +772,19 @@ CONFIG_USB_MON=y
# USB Gadget Support
#
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_S3C2410 is not set
CONFIG_USB_GADGET_AT91=y
CONFIG_USB_AT91=y
# CONFIG_USB_GADGET_DUMMY_HCD is not set
@ -745,17 +796,56 @@ CONFIG_USB_FILE_STORAGE=m
# CONFIG_USB_FILE_STORAGE_TEST is not set
CONFIG_USB_G_SERIAL=m
# CONFIG_USB_MIDI_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# Real Time Clock
# RTC interfaces
#
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_AT91SAM9=y
#
# File systems
@ -806,7 +896,6 @@ CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
@ -825,10 +914,7 @@ CONFIG_CRAMFS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NETWORK_FILESYSTEMS=y
# CONFIG_NFS_FS is not set
# CONFIG_NFSD is not set
# CONFIG_SMB_FS is not set
@ -836,17 +922,12 @@ CONFIG_CRAMFS=y
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
@ -887,41 +968,49 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Profiling support
#
# CONFIG_DLM is not set
CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y
@ -932,18 +1021,21 @@ CONFIG_DEBUG_LL=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

581
arch/arm/configs/at91sam9261ek_defconfig
View File

File diff suppressed because it is too large Load Diff

559
arch/arm/configs/at91sam9263ek_defconfig
View File

File diff suppressed because it is too large Load Diff

450
arch/arm/configs/at91sam9rlek_defconfig
View File

@ -1,15 +1,18 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.21
# Mon May 7 16:30:40 2007
# Linux kernel version: 2.6.24-rc7
# Tue Jan 8 22:24:14 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
@ -23,27 +26,28 @@ CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
@ -62,32 +66,30 @@ CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
@ -119,14 +121,16 @@ CONFIG_ARCH_AT91=y
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
@ -134,8 +138,17 @@ CONFIG_ARCH_AT91=y
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
#
# Boot options
#
#
# Power management
#
#
# Atmel AT91 System-on-Chip
#
@ -144,6 +157,8 @@ CONFIG_ARCH_AT91=y
# CONFIG_ARCH_AT91SAM9261 is not set
# CONFIG_ARCH_AT91SAM9263 is not set
CONFIG_ARCH_AT91SAM9RL=y
# CONFIG_ARCH_AT91X40 is not set
CONFIG_AT91_PMC_UNIT=y
#
# AT91SAM9RL Board Type
@ -157,7 +172,9 @@ CONFIG_MACH_AT91SAM9RLEK=y
#
# AT91 Feature Selections
#
# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ATMEL_TCLIB is not set
CONFIG_AT91_TIMER_HZ=100
#
# Processor Type
@ -185,15 +202,14 @@ CONFIG_CPU_CP15_MMU=y
#
# Bus support
#
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
# CONFIG_TICK_ONESHOT is not set
# CONFIG_PREEMPT is not set
# CONFIG_NO_IDLE_HZ is not set
CONFIG_HZ=100
@ -206,9 +222,12 @@ CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
@ -245,6 +264,7 @@ CONFIG_BINFMT_ELF=y
# Power management options
#
# CONFIG_PM is not set
CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
@ -254,7 +274,6 @@ CONFIG_NET=y
#
# Networking options
#
# CONFIG_NETDEBUG is not set
# CONFIG_PACKET is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
@ -271,10 +290,6 @@ CONFIG_UNIX=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
@ -284,7 +299,16 @@ CONFIG_UNIX=y
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
@ -293,21 +317,14 @@ CONFIG_UNIX=y
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
#
# Memory Technology Devices (MTD)
#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_CONCAT=y
@ -327,6 +344,7 @@ CONFIG_MTD_BLOCK=y
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
@ -346,7 +364,6 @@ CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# CONFIG_MTD_OBSOLETE_CHIPS is not set
#
# Mapping drivers for chip access
@ -370,36 +387,23 @@ CONFIG_MTD_DATAFLASH=y
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
#
# NAND Flash Device Drivers
#
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
CONFIG_MTD_NAND_AT91=y
# CONFIG_MTD_NAND_NANDSIM is not set
#
# OneNAND Flash Device Drivers
#
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ONENAND is not set
#
# Parallel port support
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNPACPI is not set
#
# Block devices
#
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
@ -410,12 +414,16 @@ CONFIG_BLK_DEV_RAM_SIZE=24576
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
CONFIG_ATMEL_SSC=y
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
@ -437,6 +445,7 @@ CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
@ -444,47 +453,13 @@ CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
#
# SCSI low-level drivers
#
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_SCSI_DEBUG is not set
#
# Serial ATA (prod) and Parallel ATA (experimental) drivers
#
# CONFIG_ATA is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
#
# I2O device support
#
#
# Network device support
#
# CONFIG_NETDEVICES is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
@ -492,6 +467,7 @@ CONFIG_SCSI_MULTI_LUN=y
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
@ -501,7 +477,6 @@ CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
@ -511,8 +486,10 @@ CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
@ -521,6 +498,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_UCB1400 is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_INPUT_MISC is not set
#
@ -554,37 +532,50 @@ CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
#
# I2C support
# I2C Algorithms
#
# CONFIG_I2C is not set
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
CONFIG_I2C_GPIO=y
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_PCA is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_DS1337 is not set
# CONFIG_SENSORS_DS1374 is not set
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# SPI support
@ -603,59 +594,54 @@ CONFIG_SPI_ATMEL=y
# SPI Protocol Masters
#
# CONFIG_SPI_AT25 is not set
#
# Dallas's 1-wire bus
#
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_HWMON_VID is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
#
# Misc devices
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_AT91SAM9_WATCHDOG=y
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_SYS_FOPS is not set
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
@ -665,9 +651,16 @@ CONFIG_FB_CFB_IMAGEBLIT=y
#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D15605 is not set
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_ATMEL=y
# CONFIG_FB_VIRTUAL is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
@ -675,70 +668,17 @@ CONFIG_FB_ATMEL=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE is not set
#
# Logo configuration
#
# CONFIG_LOGO is not set
#
# Sound
#
CONFIG_SOUND=y
#
# Advanced Linux Sound Architecture
#
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_SEQ_DUMMY=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_SEQUENCER_OSS=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_VERBOSE_PROCFS=y
CONFIG_SND_VERBOSE_PRINTK=y
CONFIG_SND_DEBUG=y
CONFIG_SND_DEBUG_DETECT=y
# CONFIG_SND_PCM_XRUN_DEBUG is not set
#
# Generic devices
#
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_VIRMIDI is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
#
# ALSA ARM devices
#
#
# SoC audio support
#
# CONFIG_SND_SOC is not set
#
# Open Sound System
#
# CONFIG_SOUND_PRIME is not set
#
# HID Devices
#
# CONFIG_SOUND is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
#
# USB support
#
# CONFIG_HIDRAW is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
@ -752,20 +692,73 @@ CONFIG_USB_ARCH_HAS_OHCI=y
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_BLOCK=y
CONFIG_MMC_AT91=y
# CONFIG_MMC_UNSAFE_RESUME is not set
#
# Real Time Clock
# MMC/SD Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
#
# MMC/SD Host Controller Drivers
#
CONFIG_MMC_AT91=y
# CONFIG_MMC_SPI is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_AT91SAM9=y
#
# File systems
@ -816,7 +809,6 @@ CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
@ -836,20 +828,13 @@ CONFIG_CRAMFS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NETWORK_FILESYSTEMS=y
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
@ -890,16 +875,15 @@ CONFIG_NLS_ISO8859_15=y
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=y
#
# Profiling support
#
CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
@ -907,8 +891,8 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
@ -916,6 +900,9 @@ CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
@ -923,10 +910,13 @@ CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y
@ -937,10 +927,7 @@ CONFIG_DEBUG_LL=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
@ -949,9 +936,12 @@ CONFIG_DEBUG_LL=y
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

2
arch/arm/configs/ateb9200_defconfig
View File

@ -714,7 +714,7 @@ CONFIG_I2C_ALGOPCA=m
#
# I2C Hardware Bus support
#
CONFIG_I2C_AT91=m
CONFIG_I2C_GPIO=m
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_PCA_ISA is not set

1228
arch/arm/configs/cam60_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

790
arch/arm/configs/csb337_defconfig
View File

File diff suppressed because it is too large Load Diff

746
arch/arm/configs/csb637_defconfig
View File

File diff suppressed because it is too large Load Diff

1315
arch/arm/configs/ecbat91_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/configs/kafa_defconfig
View File

@ -587,14 +587,14 @@ CONFIG_I2C_CHARDEV=y
#
# I2C Algorithms
#
# CONFIG_I2C_ALGOBIT is not set
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
CONFIG_I2C_AT91=y
CONFIG_I2C_GPIO=y
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_PCA_ISA is not set

1182
arch/arm/configs/magician_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

652
arch/arm/configs/ns9xxx_defconfig
View File

@ -1,621 +1,79 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.20
# Thu Feb 15 20:51:47 2007
#
CONFIG_ARM=y
# CONFIG_GENERIC_TIME is not set
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_UTS_NS is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SHMEM=y
CONFIG_SLAB=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#
# Loadable module support
#
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_KMOD=y
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_L7200 is not set
CONFIG_ARCH_NS9XXX=y
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_OMAP is not set
#
# NS9xxx Implementations
#
CONFIG_MACH_A9M9360=y
CONFIG_MACH_A9M9750=y
CONFIG_MACH_CC7UCAMRY=y
CONFIG_MACH_CC9C=y
CONFIG_MACH_CC9P9210=y
CONFIG_MACH_CC9P9210JS=y
CONFIG_MACH_CC9P9215=y
CONFIG_MACH_CC9P9215JS=y
CONFIG_MACH_CC9P9360DEV=y
CONFIG_PROCESSOR_NS9360=y
CONFIG_BOARD_A9M9750DEV=y
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_ARM926T=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5TJ=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
# CONFIG_ARM_THUMB is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
#
# Bus support
#
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# Kernel Features
#
# CONFIG_PREEMPT is not set
# CONFIG_NO_IDLE_HZ is not set
CONFIG_HZ=100
# CONFIG_AEABI is not set
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE=""
# CONFIG_XIP_KERNEL is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_MACH_CC9P9360JS=y
CONFIG_MACH_CC9P9360VAL=y
CONFIG_MACH_CC9P9750DEV=y
CONFIG_MACH_CC9P9750VAL=y
CONFIG_MACH_CCW9C=y
CONFIG_MACH_INC20OTTER=y
CONFIG_MACH_OTTER=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
# CONFIG_VFP is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
# CONFIG_ARTHUR is not set
#
# Power management options
#
# CONFIG_PM is not set
# CONFIG_APM is not set
#
# Networking
#
# CONFIG_NET is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CDROM_PKTCDVD is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_NETLINK is not set
#
# Serial ATA (prod) and Parallel ATA (experimental) drivers
#
# CONFIG_ATA is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
#
# I2O device support
#
#
# ISDN subsystem
#
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_NET=y
CONFIG_PACKET=m
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_SYN_COOKIES=y
CONFIG_MTD=m
CONFIG_MTD_CONCAT=m
CONFIG_MTD_CHAR=m
CONFIG_MTD_BLOCK=m
CONFIG_MTD_CFI=m
CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_BLK_DEV_LOOP=m
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_NS9XXX_ETH=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
# CONFIG_SERIAL_8250_SHARE_IRQ is not set
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_SERIAL_NS921X=y
CONFIG_SERIAL_NS921X_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
CONFIG_ADC_NS9215=m
CONFIG_I2C=m
CONFIG_I2C_GPIO=m
# CONFIG_HWMON is not set
# CONFIG_HWMON_VID is not set
#
# Misc devices
#
# CONFIG_TIFM_CORE is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
#
# Graphics support
#
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# HID Devices
#
CONFIG_HID=y
#
# USB support
#
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# Real Time Clock
#
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
# CONFIG_HID_DEBUG is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=m
CONFIG_LEDS_TRIGGER_HEARTBEAT=m
CONFIG_RTC_CLASS=m
CONFIG_RTC_DRV_NS9215=m
CONFIG_EXT2_FS=m
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_JFFS2_FS=m
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHEDSTATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_ICEDCC=y
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC32 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
CONFIG_IOMAP_COPY=y

2
arch/arm/configs/orion_defconfig → arch/arm/configs/orion5x_defconfig
View File

@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_MXC is not set
CONFIG_ARCH_ORION=y
CONFIG_ARCH_ORION5X=y
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set

4
arch/arm/configs/picotux200_defconfig
View File

@ -727,14 +727,14 @@ CONFIG_I2C_CHARDEV=m
#
# I2C Algorithms
#
# CONFIG_I2C_ALGOBIT is not set
CONFIG_I2C_ALGOBIT=m
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
CONFIG_I2C_AT91=m
CONFIG_I2C_GPIO=m
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set

1098
arch/arm/configs/sam9_l9260_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

886
arch/arm/configs/tct_hammer_defconfig Normal file
View File

@ -0,0 +1,886 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc7-hammer
# Thu Mar 27 16:39:48 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
CONFIG_NO_IOPORT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_SUPPORTS_AOUT=y
CONFIG_ZONE_DMA=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_GROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
# CONFIG_BUG is not set
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SHMEM is not set
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_SLAB is not set
# CONFIG_SLUB is not set
CONFIG_SLOB=y
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_RT_MUTEXES=y
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_KMOD is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_CLASSIC_RCU=y
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_ORION is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
CONFIG_ARCH_S3C2410=y
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM7X00A is not set
CONFIG_PLAT_S3C24XX=y
# CONFIG_S3C2410_DMA is not set
CONFIG_PLAT_S3C=y
CONFIG_CPU_LLSERIAL_S3C2410_ONLY=y
CONFIG_CPU_LLSERIAL_S3C2410=y
#
# Boot options
#
# CONFIG_S3C_BOOT_ERROR_RESET is not set
#
# Power management
#
CONFIG_S3C_LOWLEVEL_UART_PORT=0
#
# S3C2400 Machines
#
CONFIG_CPU_S3C2410=y
CONFIG_S3C2410_GPIO=y
CONFIG_S3C2410_CLOCK=y
#
# S3C2410 Machines
#
# CONFIG_ARCH_SMDK2410 is not set
# CONFIG_ARCH_H1940 is not set
# CONFIG_MACH_N30 is not set
# CONFIG_ARCH_BAST is not set
# CONFIG_MACH_OTOM is not set
# CONFIG_MACH_AML_M5900 is not set
CONFIG_MACH_TCT_HAMMER=y
# CONFIG_MACH_VR1000 is not set
# CONFIG_MACH_QT2410 is not set
#
# S3C2412 Machines
#
# CONFIG_MACH_SMDK2413 is not set
# CONFIG_MACH_SMDK2412 is not set
# CONFIG_MACH_VSTMS is not set
#
# S3C2440 Machines
#
# CONFIG_MACH_ANUBIS is not set
# CONFIG_MACH_OSIRIS is not set
# CONFIG_MACH_RX3715 is not set
# CONFIG_ARCH_S3C2440 is not set
# CONFIG_MACH_NEXCODER_2440 is not set
#
# S3C2442 Machines
#
#
# S3C2443 Machines
#
# CONFIG_MACH_SMDK2443 is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_ARM920T=y
CONFIG_CPU_32v4T=y
CONFIG_CPU_ABRT_EV4T=y
CONFIG_CPU_CACHE_V4WT=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_OUTER_CACHE is not set
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
# CONFIG_TICK_ONESHOT is not set
# CONFIG_PREEMPT is not set
# CONFIG_NO_IDLE_HZ is not set
CONFIG_HZ=200
# CONFIG_AEABI is not set
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=64M root=/dev/ram0 init=/linuxrc rw"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
# CONFIG_ARTHUR is not set
#
# Power management options
#
# CONFIG_PM is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
# CONFIG_INET is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_FW_LOADER=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_OTP is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0x00000000
CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=10240
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_NETDEVICES is not set
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
# CONFIG_VT_CONSOLE is not set
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_S3C2410=y
CONFIG_SERIAL_S3C2410_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
#
# Sound
#
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
#
# Miscellaneous USB options
#
# CONFIG_USB_DEVICEFS is not set
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# may also be needed; see USB_STORAGE Help for more information
#
# CONFIG_USB_LIBUSUAL is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
CONFIG_USB_MON=y
#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_PHIDGET is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
CONFIG_USB_GADGET_S3C2410=y
CONFIG_USB_S3C2410=y
# CONFIG_USB_S3C2410_DEBUG is not set
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_GADGET_DUALSPEED is not set
# CONFIG_USB_ZERO is not set
CONFIG_USB_ETH=y
CONFIG_USB_ETH_RNDIS=y
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_SYSCTL is not set
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_DETECT_SOFTLOCKUP is not set
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SAMPLES is not set
# CONFIG_DEBUG_USER is not set
CONFIG_DEBUG_ERRORS=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_DEBUG_S3C_PORT is not set
CONFIG_DEBUG_S3C_UART=0
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_CRC_CCITT=y
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_DMA=y

1216
arch/arm/configs/yl9200_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/kernel/calls.S
View File

@ -359,9 +359,11 @@
CALL(sys_kexec_load)
CALL(sys_utimensat)
CALL(sys_signalfd)
/* 350 */ CALL(sys_ni_syscall)
/* 350 */ CALL(sys_timerfd_create)
CALL(sys_eventfd)
CALL(sys_fallocate)
CALL(sys_timerfd_settime)
CALL(sys_timerfd_gettime)
#ifndef syscalls_counted
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
#define syscalls_counted

24
arch/arm/kernel/entry-armv.S
View File

@ -209,14 +209,12 @@ __irq_svc:
irq_handler
#ifdef CONFIG_PREEMPT
str r8, [tsk, #TI_PREEMPT] @ restore preempt count
ldr r0, [tsk, #TI_FLAGS] @ get flags
teq r8, #0 @ if preempt count != 0
movne r0, #0 @ force flags to 0
tst r0, #_TIF_NEED_RESCHED
blne svc_preempt
preempt_return:
ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
str r8, [tsk, #TI_PREEMPT] @ restore preempt count
teq r0, r7
strne r0, [r0, -r0] @ bug()
#endif
ldr r0, [sp, #S_PSR] @ irqs are already disabled
msr spsr_cxsf, r0
@ -230,19 +228,11 @@ preempt_return:
#ifdef CONFIG_PREEMPT
svc_preempt:
teq r8, #0 @ was preempt count = 0
ldreq r6, .LCirq_stat
movne pc, lr @ no
ldr r0, [r6, #4] @ local_irq_count
ldr r1, [r6, #8] @ local_bh_count
adds r0, r0, r1
movne pc, lr
mov r7, #0 @ preempt_schedule_irq
str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
mov r8, lr
1: bl preempt_schedule_irq @ irq en/disable is done inside
ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
tst r0, #_TIF_NEED_RESCHED
beq preempt_return @ go again
moveq pc, r8 @ go again
b 1b
#endif
@ -333,10 +323,6 @@ __pabt_svc:
#endif
.LCfp:
.word fp_enter
#ifdef CONFIG_PREEMPT
.LCirq_stat:
.word irq_stat
#endif
/*
* User mode handlers

7
arch/arm/kernel/head-common.S
View File

@ -75,8 +75,13 @@ __error_p:
#ifdef CONFIG_DEBUG_LL
adr r0, str_p1
bl printascii
mov r0, r9
bl printhex8
adr r0, str_p2
bl printascii
b __error
str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n"
str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x"
str_p2: .asciz ").\n"
.align
#endif

33
arch/arm/mach-at91/Kconfig
View File

@ -12,18 +12,28 @@ config ARCH_AT91RM9200
config ARCH_AT91SAM9260
bool "AT91SAM9260 or AT91SAM9XE"
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
config ARCH_AT91SAM9261
bool "AT91SAM9261"
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
config ARCH_AT91SAM9263
bool "AT91SAM9263"
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
config ARCH_AT91SAM9RL
bool "AT91SAM9RL"
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
config ARCH_AT91CAP9
bool "AT91CAP9"
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
config ARCH_AT91X40
bool "AT91x40"
@ -109,6 +119,13 @@ config MACH_KAFA
help
Select this if you are using Sperry-Sun's KAFA board.
config MACH_ECBAT91
bool "emQbit ECB_AT91 SBC"
depends on ARCH_AT91RM9200
help
Select this if you are using emQbit's ECB_AT91 board.
<http://wiki.emqbit.com/free-ecb-at91>
endif
# ----------------------------------------------------------
@ -133,6 +150,20 @@ config MACH_AT91SAM9260EK
Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
config MACH_CAM60
bool "KwikByte KB9260 (CAM60) board"
depends on ARCH_AT91SAM9260
help
Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
<http://www.kwikbyte.com/KB9260.html>
config MACH_SAM9_L9260
bool "Olimex SAM9-L9260 board"
depends on ARCH_AT91SAM9260
help
Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
<http://www.olimex.com/dev/sam9-L9260.html>
endif
# ----------------------------------------------------------
@ -216,7 +247,7 @@ comment "AT91 Board Options"
config MTD_AT91_DATAFLASH_CARD
bool "Enable DataFlash Card support"
depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK)
depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK || MACH_SAM9_L9260 || MACH_ECBAT91)
help
Enable support for the DataFlash card.

3
arch/arm/mach-at91/Makefile
View File

@ -29,9 +29,12 @@ obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
obj-$(CONFIG_MACH_KAFA) += board-kafa.o
obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o
obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
# AT91SAM9260 board-specific support
obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
obj-$(CONFIG_MACH_CAM60) += board-cam60.o
obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o
# AT91SAM9261 board-specific support
obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o

9
arch/arm/mach-at91/at91cap9.c
View File

@ -13,12 +13,14 @@
*/
#include <linux/module.h>
#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
@ -288,6 +290,12 @@ static void at91cap9_reset(void)
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
static void at91cap9_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}
/* --------------------------------------------------------------------
* AT91CAP9 processor initialization
* -------------------------------------------------------------------- */
@ -298,6 +306,7 @@ void __init at91cap9_initialize(unsigned long main_clock)
iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
at91_arch_reset = at91cap9_reset;
pm_power_off = at91cap9_poweroff;
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
/* Init clock subsystem */

70
arch/arm/mach-at91/at91cap9_devices.c
View File

@ -16,15 +16,15 @@
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c-gpio.h>
#include <video/atmel_lcdc.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91cap9_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
@ -283,10 +283,15 @@ static struct at91_nand_data nand_data;
#define NAND_BASE AT91_CHIPSELECT_3
static struct resource nand_resources[] = {
{
[0] = {
.start = NAND_BASE,
.end = NAND_BASE + SZ_256M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91_BASE_SYS + AT91_ECC,
.end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}
};
@ -344,6 +349,7 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
void __init at91_add_device_nand(struct at91_nand_data *data) {}
#endif
/* --------------------------------------------------------------------
* TWI (i2c)
* -------------------------------------------------------------------- */
@ -531,14 +537,60 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
#endif
/* --------------------------------------------------------------------
* Timer/Counter block
* -------------------------------------------------------------------- */
#ifdef CONFIG_ATMEL_TCLIB
static struct resource tcb_resources[] = {
[0] = {
.start = AT91CAP9_BASE_TCB0,
.end = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91CAP9_ID_TCB,
.end = AT91CAP9_ID_TCB,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91cap9_tcb_device = {
.name = "atmel_tcb",
.id = 0,
.resource = tcb_resources,
.num_resources = ARRAY_SIZE(tcb_resources),
};
static void __init at91_add_device_tc(void)
{
/* this chip has one clock and irq for all three TC channels */
at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
platform_device_register(&at91cap9_tcb_device);
}
#else
static void __init at91_add_device_tc(void) { }
#endif
/* --------------------------------------------------------------------
* RTT
* -------------------------------------------------------------------- */
static struct resource rtt_resources[] = {
{
.start = AT91_BASE_SYS + AT91_RTT,
.end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device at91cap9_rtt_device = {
.name = "at91_rtt",
.id = -1,
.num_resources = 0,
.id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
static void __init at91_add_device_rtt(void)
@ -990,7 +1042,7 @@ static inline void configure_usart2_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
}
static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
@ -1031,8 +1083,6 @@ void __init at91_set_serial_console(unsigned portnr)
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
@ -1043,6 +1093,9 @@ void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
@ -1060,6 +1113,7 @@ static int __init at91_add_standard_devices(void)
{
at91_add_device_rtt();
at91_add_device_watchdog();
at91_add_device_tc();
return 0;
}

92
arch/arm/mach-at91/at91rm9200_devices.c
View File

@ -576,6 +576,90 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
#endif
/* --------------------------------------------------------------------
* Timer/Counter blocks
* -------------------------------------------------------------------- */
#ifdef CONFIG_ATMEL_TCLIB
static struct resource tcb0_resources[] = {
[0] = {
.start = AT91RM9200_BASE_TCB0,
.end = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91RM9200_ID_TC0,
.end = AT91RM9200_ID_TC0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AT91RM9200_ID_TC1,
.end = AT91RM9200_ID_TC1,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = AT91RM9200_ID_TC2,
.end = AT91RM9200_ID_TC2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91rm9200_tcb0_device = {
.name = "atmel_tcb",
.id = 0,
.resource = tcb0_resources,
.num_resources = ARRAY_SIZE(tcb0_resources),
};
static struct resource tcb1_resources[] = {
[0] = {
.start = AT91RM9200_BASE_TCB1,
.end = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91RM9200_ID_TC3,
.end = AT91RM9200_ID_TC3,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AT91RM9200_ID_TC4,
.end = AT91RM9200_ID_TC4,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = AT91RM9200_ID_TC5,
.end = AT91RM9200_ID_TC5,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91rm9200_tcb1_device = {
.name = "atmel_tcb",
.id = 1,
.resource = tcb1_resources,
.num_resources = ARRAY_SIZE(tcb1_resources),
};
static void __init at91_add_device_tc(void)
{
/* this chip has a separate clock and irq for each TC channel */
at91_clock_associate("tc0_clk", &at91rm9200_tcb0_device.dev, "t0_clk");
at91_clock_associate("tc1_clk", &at91rm9200_tcb0_device.dev, "t1_clk");
at91_clock_associate("tc2_clk", &at91rm9200_tcb0_device.dev, "t2_clk");
platform_device_register(&at91rm9200_tcb0_device);
at91_clock_associate("tc3_clk", &at91rm9200_tcb1_device.dev, "t0_clk");
at91_clock_associate("tc4_clk", &at91rm9200_tcb1_device.dev, "t1_clk");
at91_clock_associate("tc5_clk", &at91rm9200_tcb1_device.dev, "t2_clk");
platform_device_register(&at91rm9200_tcb1_device);
}
#else
static void __init at91_add_device_tc(void) { }
#endif
/* --------------------------------------------------------------------
* RTC
* -------------------------------------------------------------------- */
@ -1019,7 +1103,7 @@ static inline void configure_usart3_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
}
static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init __deprecated at91_init_serial(struct at91_uart_config *config)
@ -1110,8 +1194,6 @@ void __init at91_set_serial_console(unsigned portnr)
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
@ -1122,6 +1204,9 @@ void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
@ -1141,6 +1226,7 @@ static int __init at91_add_standard_devices(void)
{
at91_add_device_rtc();
at91_add_device_watchdog();
at91_add_device_tc();
return 0;
}

8
arch/arm/mach-at91/at91sam9260.c
View File

@ -11,6 +11,7 @@
*/
#include <linux/module.h>
#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -18,6 +19,7 @@
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
@ -267,6 +269,11 @@ static void at91sam9260_reset(void)
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
static void at91sam9260_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}
/* --------------------------------------------------------------------
* AT91SAM9260 processor initialization
@ -304,6 +311,7 @@ void __init at91sam9260_initialize(unsigned long main_clock)
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
at91_arch_reset = at91sam9260_reset;
pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);

159
arch/arm/mach-at91/at91sam9260_devices.c
View File

@ -19,8 +19,8 @@
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
@ -288,10 +288,15 @@ static struct at91_nand_data nand_data;
#define NAND_BASE AT91_CHIPSELECT_3
static struct resource nand_resources[] = {
{
[0] = {
.start = NAND_BASE,
.end = NAND_BASE + SZ_256M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91_BASE_SYS + AT91_ECC,
.end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}
};
@ -539,6 +544,90 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
#endif
/* --------------------------------------------------------------------
* Timer/Counter blocks
* -------------------------------------------------------------------- */
#ifdef CONFIG_ATMEL_TCLIB
static struct resource tcb0_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_TCB0,
.end = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9260_ID_TC0,
.end = AT91SAM9260_ID_TC0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AT91SAM9260_ID_TC1,
.end = AT91SAM9260_ID_TC1,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = AT91SAM9260_ID_TC2,
.end = AT91SAM9260_ID_TC2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91sam9260_tcb0_device = {
.name = "atmel_tcb",
.id = 0,
.resource = tcb0_resources,
.num_resources = ARRAY_SIZE(tcb0_resources),
};
static struct resource tcb1_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_TCB1,
.end = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9260_ID_TC3,
.end = AT91SAM9260_ID_TC3,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AT91SAM9260_ID_TC4,
.end = AT91SAM9260_ID_TC4,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = AT91SAM9260_ID_TC5,
.end = AT91SAM9260_ID_TC5,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91sam9260_tcb1_device = {
.name = "atmel_tcb",
.id = 1,
.resource = tcb1_resources,
.num_resources = ARRAY_SIZE(tcb1_resources),
};
static void __init at91_add_device_tc(void)
{
/* this chip has a separate clock and irq for each TC channel */
at91_clock_associate("tc0_clk", &at91sam9260_tcb0_device.dev, "t0_clk");
at91_clock_associate("tc1_clk", &at91sam9260_tcb0_device.dev, "t1_clk");
at91_clock_associate("tc2_clk", &at91sam9260_tcb0_device.dev, "t2_clk");
platform_device_register(&at91sam9260_tcb0_device);
at91_clock_associate("tc3_clk", &at91sam9260_tcb1_device.dev, "t0_clk");
at91_clock_associate("tc4_clk", &at91sam9260_tcb1_device.dev, "t1_clk");
at91_clock_associate("tc5_clk", &at91sam9260_tcb1_device.dev, "t2_clk");
platform_device_register(&at91sam9260_tcb1_device);
}
#else
static void __init at91_add_device_tc(void) { }
#endif
/* --------------------------------------------------------------------
* RTT
* -------------------------------------------------------------------- */
@ -553,7 +642,7 @@ static struct resource rtt_resources[] = {
static struct platform_device at91sam9260_rtt_device = {
.name = "at91_rtt",
.id = -1,
.id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
@ -962,64 +1051,9 @@ static inline void configure_usart5_pins(void)
at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
}
static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init __deprecated at91_init_serial(struct at91_uart_config *config)
{
int i;
/* Fill in list of supported UARTs */
for (i = 0; i < config->nr_tty; i++) {
switch (config->tty_map[i]) {
case 0:
configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI);
at91_uarts[i] = &at91sam9260_uart0_device;
at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
break;
case 1:
configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_uarts[i] = &at91sam9260_uart1_device;
at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
break;
case 2:
configure_usart2_pins(0);
at91_uarts[i] = &at91sam9260_uart2_device;
at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
break;
case 3:
configure_usart3_pins(0);
at91_uarts[i] = &at91sam9260_uart3_device;
at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
break;
case 4:
configure_usart4_pins();
at91_uarts[i] = &at91sam9260_uart4_device;
at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
break;
case 5:
configure_usart5_pins();
at91_uarts[i] = &at91sam9260_uart5_device;
at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
break;
case 6:
configure_dbgu_pins();
at91_uarts[i] = &at91sam9260_dbgu_device;
at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
break;
default:
continue;
}
at91_uarts[i]->id = i; /* update ID number to mapped ID */
}
/* Set serial console device */
if (config->console_tty < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[config->console_tty];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
@ -1073,8 +1107,6 @@ void __init at91_set_serial_console(unsigned portnr)
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
@ -1085,9 +1117,11 @@ void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}
@ -1103,6 +1137,7 @@ static int __init at91_add_standard_devices(void)
{
at91_add_device_rtt();
at91_add_device_watchdog();
at91_add_device_tc();
return 0;
}

8
arch/arm/mach-at91/at91sam9261.c
View File

@ -11,12 +11,14 @@
*/
#include <linux/module.h>
#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
@ -245,6 +247,11 @@ static void at91sam9261_reset(void)
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
static void at91sam9261_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}
/* --------------------------------------------------------------------
* AT91SAM9261 processor initialization
@ -256,6 +263,7 @@ void __init at91sam9261_initialize(unsigned long main_clock)
iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
at91_arch_reset = at91sam9261_reset;
pm_power_off = at91sam9261_poweroff;
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
| (1 << AT91SAM9261_ID_IRQ2);

102
arch/arm/mach-at91/at91sam9261_devices.c
View File

@ -24,7 +24,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
@ -547,6 +547,55 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
#endif
/* --------------------------------------------------------------------
* Timer/Counter block
* -------------------------------------------------------------------- */
#ifdef CONFIG_ATMEL_TCLIB
static struct resource tcb_resources[] = {
[0] = {
.start = AT91SAM9261_BASE_TCB0,
.end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9261_ID_TC0,
.end = AT91SAM9261_ID_TC0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AT91SAM9261_ID_TC1,
.end = AT91SAM9261_ID_TC1,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = AT91SAM9261_ID_TC2,
.end = AT91SAM9261_ID_TC2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91sam9261_tcb_device = {
.name = "atmel_tcb",
.id = 0,
.resource = tcb_resources,
.num_resources = ARRAY_SIZE(tcb_resources),
};
static void __init at91_add_device_tc(void)
{
/* this chip has a separate clock and irq for each TC channel */
at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk");
at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk");
at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk");
platform_device_register(&at91sam9261_tcb_device);
}
#else
static void __init at91_add_device_tc(void) { }
#endif
/* --------------------------------------------------------------------
* RTT
* -------------------------------------------------------------------- */
@ -561,7 +610,7 @@ static struct resource rtt_resources[] = {
static struct platform_device at91sam9261_rtt_device = {
.name = "at91_rtt",
.id = -1,
.id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
@ -938,49 +987,9 @@ static inline void configure_usart2_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
}
static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init __deprecated at91_init_serial(struct at91_uart_config *config)
{
int i;
/* Fill in list of supported UARTs */
for (i = 0; i < config->nr_tty; i++) {
switch (config->tty_map[i]) {
case 0:
configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_uarts[i] = &at91sam9261_uart0_device;
at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart");
break;
case 1:
configure_usart1_pins(0);
at91_uarts[i] = &at91sam9261_uart1_device;
at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart");
break;
case 2:
configure_usart2_pins(0);
at91_uarts[i] = &at91sam9261_uart2_device;
at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart");
break;
case 3:
configure_dbgu_pins();
at91_uarts[i] = &at91sam9261_dbgu_device;
at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart");
break;
default:
continue;
}
at91_uarts[i]->id = i; /* update ID number to mapped ID */
}
/* Set serial console device */
if (config->console_tty < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[config->console_tty];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
@ -1019,8 +1028,6 @@ void __init at91_set_serial_console(unsigned portnr)
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
@ -1031,9 +1038,11 @@ void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}
@ -1050,6 +1059,7 @@ static int __init at91_add_standard_devices(void)
{
at91_add_device_rtt();
at91_add_device_watchdog();
at91_add_device_tc();
return 0;
}

8
arch/arm/mach-at91/at91sam9263.c
View File

@ -11,12 +11,14 @@
*/
#include <linux/module.h>
#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
@ -271,6 +273,11 @@ static void at91sam9263_reset(void)
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
static void at91sam9263_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}
/* --------------------------------------------------------------------
* AT91SAM9263 processor initialization
@ -282,6 +289,7 @@ void __init at91sam9263_initialize(unsigned long main_clock)
iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
at91_arch_reset = at91sam9263_reset;
pm_power_off = at91sam9263_poweroff;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
/* Init clock subsystem */

98
arch/arm/mach-at91/at91sam9263_devices.c
View File

@ -22,8 +22,8 @@
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9263_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
@ -358,10 +358,15 @@ static struct at91_nand_data nand_data;
#define NAND_BASE AT91_CHIPSELECT_3
static struct resource nand_resources[] = {
{
[0] = {
.start = NAND_BASE,
.end = NAND_BASE + SZ_256M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91_BASE_SYS + AT91_ECC0,
.end = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}
};
@ -782,6 +787,43 @@ void __init at91_add_device_isi(void) {}
#endif
/* --------------------------------------------------------------------
* Timer/Counter block
* -------------------------------------------------------------------- */
#ifdef CONFIG_ATMEL_TCLIB
static struct resource tcb_resources[] = {
[0] = {
.start = AT91SAM9263_BASE_TCB0,
.end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9263_ID_TCB,
.end = AT91SAM9263_ID_TCB,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91sam9263_tcb_device = {
.name = "atmel_tcb",
.id = 0,
.resource = tcb_resources,
.num_resources = ARRAY_SIZE(tcb_resources),
};
static void __init at91_add_device_tc(void)
{
/* this chip has one clock and irq for all three TC channels */
at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk");
platform_device_register(&at91sam9263_tcb_device);
}
#else
static void __init at91_add_device_tc(void) { }
#endif
/* --------------------------------------------------------------------
* RTT
* -------------------------------------------------------------------- */
@ -933,9 +975,6 @@ static inline void configure_ssc1_pins(unsigned pins)
}
/*
* Return the device node so that board init code can use it as the
* parent for the device node reflecting how it's used on this board.
*
* SSC controllers are accessed through library code, instead of any
* kind of all-singing/all-dancing driver. For example one could be
* used by a particular I2S audio codec's driver, while another one
@ -1146,49 +1185,9 @@ static inline void configure_usart2_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
}
static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init __deprecated at91_init_serial(struct at91_uart_config *config)
{
int i;
/* Fill in list of supported UARTs */
for (i = 0; i < config->nr_tty; i++) {
switch (config->tty_map[i]) {
case 0:
configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_uarts[i] = &at91sam9263_uart0_device;
at91_clock_associate("usart0_clk", &at91sam9263_uart0_device.dev, "usart");
break;
case 1:
configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_uarts[i] = &at91sam9263_uart1_device;
at91_clock_associate("usart1_clk", &at91sam9263_uart1_device.dev, "usart");
break;
case 2:
configure_usart2_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_uarts[i] = &at91sam9263_uart2_device;
at91_clock_associate("usart2_clk", &at91sam9263_uart2_device.dev, "usart");
break;
case 3:
configure_dbgu_pins();
at91_uarts[i] = &at91sam9263_dbgu_device;
at91_clock_associate("mck", &at91sam9263_dbgu_device.dev, "usart");
break;
default:
continue;
}
at91_uarts[i]->id = i; /* update ID number to mapped ID */
}
/* Set serial console device */
if (config->console_tty < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[config->console_tty];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
@ -1227,8 +1226,6 @@ void __init at91_set_serial_console(unsigned portnr)
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
@ -1239,9 +1236,11 @@ void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}
@ -1257,6 +1256,7 @@ static int __init at91_add_standard_devices(void)
{
at91_add_device_rtt();
at91_add_device_watchdog();
at91_add_device_tc();
return 0;
}

171
arch/arm/mach-at91/at91sam926x_time.c
View File

@ -1,23 +1,20 @@
/*
* linux/arch/arm/mach-at91/at91sam926x_time.c
* at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
*
* Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
* Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
* Converted to ClockSource/ClockEvents by David Brownell.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/time.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/mach/time.h>
#include <asm/arch/at91_pit.h>
@ -26,85 +23,167 @@
#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
static u32 pit_cycle; /* write-once */
static u32 pit_cnt; /* access only w/system irq blocked */
/*
* Returns number of microseconds since last timer interrupt. Note that interrupts
* will have been disabled by do_gettimeofday()
* 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
* Clocksource: just a monotonic counter of MCK/16 cycles.
* We don't care whether or not PIT irqs are enabled.
*/
static unsigned long at91sam926x_gettimeoffset(void)
static cycle_t read_pit_clk(void)
{
unsigned long elapsed;
unsigned long t = at91_sys_read(AT91_PIT_PIIR);
unsigned long flags;
u32 elapsed;
u32 t;
elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */
raw_local_irq_save(flags);
elapsed = pit_cnt;
t = at91_sys_read(AT91_PIT_PIIR);
raw_local_irq_restore(flags);
return (unsigned long)(elapsed * jiffies_to_usecs(1)) / LATCH;
elapsed += PIT_PICNT(t) * pit_cycle;
elapsed += PIT_CPIV(t);
return elapsed;
}
static struct clocksource pit_clk = {
.name = "pit",
.rating = 175,
.read = read_pit_clk,
.shift = 20,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
/*
* Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
*/
static void
pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
unsigned long flags;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
/* update clocksource counter, then enable the IRQ */
raw_local_irq_save(flags);
pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
| AT91_PIT_PITIEN);
raw_local_irq_restore(flags);
break;
case CLOCK_EVT_MODE_ONESHOT:
BUG();
/* FALLTHROUGH */
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
/* disable irq, leaving the clocksource active */
at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
break;
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static struct clock_event_device pit_clkevt = {
.name = "pit",
.features = CLOCK_EVT_FEAT_PERIODIC,
.shift = 32,
.rating = 100,
.cpumask = CPU_MASK_CPU0,
.set_mode = pit_clkevt_mode,
};
/*
* IRQ handler for the timer.
*/
static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
{
volatile long nr_ticks;
if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */
/* Get number to ticks performed before interrupt and clear PIT interrupt */
/* The PIT interrupt may be disabled, and is shared */
if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
&& (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
unsigned nr_ticks;
/* Get number of ticks performed before irq, and ack it */
nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
do {
timer_tick();
pit_cnt += pit_cycle;
pit_clkevt.event_handler(&pit_clkevt);
nr_ticks--;
} while (nr_ticks);
return IRQ_HANDLED;
} else
return IRQ_NONE; /* not handled */
}
return IRQ_NONE;
}
static struct irqaction at91sam926x_timer_irq = {
static struct irqaction at91sam926x_pit_irq = {
.name = "at91_tick",
.flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = at91sam926x_timer_interrupt
.handler = at91sam926x_pit_interrupt
};
void at91sam926x_timer_reset(void)
static void at91sam926x_pit_reset(void)
{
/* Disable timer */
/* Disable timer and irqs */
at91_sys_write(AT91_PIT_MR, 0);
/* Clear any pending interrupts */
(void) at91_sys_read(AT91_PIT_PIVR);
/* Clear any pending interrupts, wait for PIT to stop counting */
while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
cpu_relax();
/* Set Period Interval timer and enable its interrupt */
at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
/* Start PIT but don't enable IRQ */
at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
}
/*
* Set up timer interrupt.
* Set up both clocksource and clockevent support.
*/
void __init at91sam926x_timer_init(void)
static void __init at91sam926x_pit_init(void)
{
/* Initialize and enable the timer */
at91sam926x_timer_reset();
unsigned long pit_rate;
unsigned bits;
/* Make IRQs happen for the system timer. */
setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
pit_cycle = (pit_rate + HZ/2) / HZ;
WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
/* Initialize and enable the timer */
at91sam926x_pit_reset();
/*
* Register clocksource. The high order bits of PIV are unused,
* so this isn't a 32-bit counter unless we get clockevent irqs.
*/
pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
pit_clk.mask = CLOCKSOURCE_MASK(bits);
clocksource_register(&pit_clk);
/* Set up irq handler */
setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
/* Set up and register clockevents */
pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
clockevents_register_device(&pit_clkevt);
}
#ifdef CONFIG_PM
static void at91sam926x_timer_suspend(void)
static void at91sam926x_pit_suspend(void)
{
/* Disable timer */
at91_sys_write(AT91_PIT_MR, 0);
}
#else
#define at91sam926x_timer_suspend NULL
#endif
struct sys_timer at91sam926x_timer = {
.init = at91sam926x_timer_init,
.offset = at91sam926x_gettimeoffset,
.suspend = at91sam926x_timer_suspend,
.resume = at91sam926x_timer_reset,
.init = at91sam926x_pit_init,
.suspend = at91sam926x_pit_suspend,
.resume = at91sam926x_pit_reset,
};

8
arch/arm/mach-at91/at91sam9rl.c
View File

@ -10,6 +10,7 @@
*/
#include <linux/module.h>
#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -17,6 +18,7 @@
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
@ -244,6 +246,11 @@ static void at91sam9rl_reset(void)
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
static void at91sam9rl_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}
/* --------------------------------------------------------------------
* AT91SAM9RL processor initialization
@ -274,6 +281,7 @@ void __init at91sam9rl_initialize(unsigned long main_clock)
iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
at91_arch_reset = at91sam9rl_reset;
pm_power_off = at91sam9rl_poweroff;
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
/* Init clock subsystem */

117
arch/arm/mach-at91/at91sam9rl_devices.c
View File

@ -20,7 +20,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/at91sam9rl_matrix.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
@ -105,10 +105,15 @@ static struct at91_nand_data nand_data;
#define NAND_BASE AT91_CHIPSELECT_3
static struct resource nand_resources[] = {
{
[0] = {
.start = NAND_BASE,
.end = NAND_BASE + SZ_256M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91_BASE_SYS + AT91_ECC,
.end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}
};
@ -384,6 +389,55 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
#endif
/* --------------------------------------------------------------------
* Timer/Counter block
* -------------------------------------------------------------------- */
#ifdef CONFIG_ATMEL_TCLIB
static struct resource tcb_resources[] = {
[0] = {
.start = AT91SAM9RL_BASE_TCB0,
.end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9RL_ID_TC0,
.end = AT91SAM9RL_ID_TC0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AT91SAM9RL_ID_TC1,
.end = AT91SAM9RL_ID_TC1,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = AT91SAM9RL_ID_TC2,
.end = AT91SAM9RL_ID_TC2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91sam9rl_tcb_device = {
.name = "atmel_tcb",
.id = 0,
.resource = tcb_resources,
.num_resources = ARRAY_SIZE(tcb_resources),
};
static void __init at91_add_device_tc(void)
{
/* this chip has a separate clock and irq for each TC channel */
at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
platform_device_register(&at91sam9rl_tcb_device);
}
#else
static void __init at91_add_device_tc(void) { }
#endif
/* --------------------------------------------------------------------
* RTC
* -------------------------------------------------------------------- */
@ -418,7 +472,7 @@ static struct resource rtt_resources[] = {
static struct platform_device at91sam9rl_rtt_device = {
.name = "at91_rtt",
.id = -1,
.id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
@ -539,9 +593,6 @@ static inline void configure_ssc1_pins(unsigned pins)
}
/*
* Return the device node so that board init code can use it as the
* parent for the device node reflecting how it's used on this board.
*
* SSC controllers are accessed through library code, instead of any
* kind of all-singing/all-dancing driver. For example one could be
* used by a particular I2S audio codec's driver, while another one
@ -802,54 +853,9 @@ static inline void configure_usart3_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
}
static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init __deprecated at91_init_serial(struct at91_uart_config *config)
{
int i;
/* Fill in list of supported UARTs */
for (i = 0; i < config->nr_tty; i++) {
switch (config->tty_map[i]) {
case 0:
configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_uarts[i] = &at91sam9rl_uart0_device;
at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
break;
case 1:
configure_usart1_pins(0);
at91_uarts[i] = &at91sam9rl_uart1_device;
at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
break;
case 2:
configure_usart2_pins(0);
at91_uarts[i] = &at91sam9rl_uart2_device;
at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
break;
case 3:
configure_usart3_pins(0);
at91_uarts[i] = &at91sam9rl_uart3_device;
at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
break;
case 4:
configure_dbgu_pins();
at91_uarts[i] = &at91sam9rl_dbgu_device;
at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
break;
default:
continue;
}
at91_uarts[i]->id = i; /* update ID number to mapped ID */
}
/* Set serial console device */
if (config->console_tty < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[config->console_tty];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
@ -893,8 +899,6 @@ void __init at91_set_serial_console(unsigned portnr)
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
@ -905,9 +909,11 @@ void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}
@ -925,6 +931,7 @@ static int __init at91_add_standard_devices(void)
at91_add_device_rtc();
at91_add_device_rtt();
at91_add_device_watchdog();
at91_add_device_tc();
return 0;
}

180
arch/arm/mach-at91/board-cam60.c Normal file
View File

@ -0,0 +1,180 @@
/*
* KwikByte CAM60 (KB9260)
*
* based on board-sam9260ek.c
* Copyright (C) 2005 SAN People
* Copyright (C) 2006 Atmel
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include "generic.h"
static void __init cam60_map_io(void)
{
/* Initialize processor: 10 MHz crystal */
at91sam9260_initialize(10000000);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init cam60_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host
*/
static struct at91_usbh_data __initdata cam60_usbh_data = {
.ports = 1,
};
/*
* SPI devices.
*/
#if defined(CONFIG_MTD_DATAFLASH)
static struct mtd_partition __initdata cam60_spi_partitions[] = {
{
.name = "BOOT1",
.offset = 0,
.size = 4 * 1056,
},
{
.name = "BOOT2",
.offset = MTDPART_OFS_NXTBLK,
.size = 256 * 1056,
},
{
.name = "kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = 2222 * 1056,
},
{
.name = "file system",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
},
};
static struct flash_platform_data __initdata cam60_spi_flash_platform_data = {
.name = "spi_flash",
.parts = cam60_spi_partitions,
.nr_parts = ARRAY_SIZE(cam60_spi_partitions)
};
#endif
static struct spi_board_info cam60_spi_devices[] = {
#if defined(CONFIG_MTD_DATAFLASH)
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
.platform_data = &cam60_spi_flash_platform_data
},
#endif
};
/*
* MACB Ethernet device
*/
static struct __initdata at91_eth_data cam60_macb_data = {
.phy_irq_pin = AT91_PIN_PB5,
.is_rmii = 0,
};
/*
* NAND Flash
*/
static struct mtd_partition __initdata cam60_nand_partition[] = {
{
.name = "nand_fs",
.offset = 0,
.size = MTDPART_SIZ_FULL,
},
};
static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
{
*num_partitions = ARRAY_SIZE(cam60_nand_partition);
return cam60_nand_partition;
}
static struct at91_nand_data __initdata cam60_nand_data = {
.ale = 21,
.cle = 22,
// .det_pin = ... not there
.rdy_pin = AT91_PIN_PA9,
.enable_pin = AT91_PIN_PA7,
.partition_info = nand_partitions,
};
static void __init cam60_board_init(void)
{
/* Serial */
at91_add_device_serial();
/* SPI */
at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
/* Ethernet */
at91_add_device_eth(&cam60_macb_data);
/* USB Host */
/* enable USB power supply circuit */
at91_set_gpio_output(AT91_PIN_PB18, 1);
at91_add_device_usbh(&cam60_usbh_data);
/* NAND */
at91_add_device_nand(&cam60_nand_data);
}
MACHINE_START(CAM60, "KwikByte CAM60")
/* Maintainer: KwikByte */
.phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91sam926x_timer,
.map_io = cam60_map_io,
.init_irq = cam60_init_irq,
.init_machine = cam60_board_init,
MACHINE_END

2
arch/arm/mach-at91/board-cap9adk.c
View File

@ -45,7 +45,7 @@
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91cap9_matrix.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9_smc.h>
#include "generic.h"

18
arch/arm/mach-at91/board-csb337.c
View File

@ -43,17 +43,6 @@
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 3 = USART0 .. USART3
* 4 = DBGU
*/
static struct at91_uart_config __initdata csb337_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 2,
.tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
};
static void __init csb337_map_io(void)
{
/* Initialize processor: 3.6864 MHz crystal */
@ -62,8 +51,11 @@ static void __init csb337_map_io(void)
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
/* Setup the serial ports and console */
at91_init_serial(&csb337_uart_config);
/* DBGU on ttyS0 */
at91_register_uart(0, 0, 0);
/* make console=ttyS0 the default */
at91_set_serial_console(0);
}
static void __init csb337_init_irq(void)

30
arch/arm/mach-at91/board-csb637.c
View File

@ -40,27 +40,16 @@
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 3 = USART0 .. USART3
* 4 = DBGU
*/
static struct at91_uart_config __initdata csb637_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 2,
.tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
};
static void __init csb637_map_io(void)
{
/* Initialize processor: 3.6864 MHz crystal */
at91rm9200_initialize(3686400, AT91RM9200_BGA);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
/* DBGU on ttyS0 */
at91_register_uart(0, 0, 0);
/* Setup the serial ports and console */
at91_init_serial(&csb637_uart_config);
/* make console=ttyS0 the default */
at91_set_serial_console(0);
}
static void __init csb637_init_irq(void)
@ -118,8 +107,19 @@ static struct platform_device csb_flash = {
.num_resources = ARRAY_SIZE(csb_flash_resources),
};
static struct gpio_led csb_leds[] = {
{ /* "d1", red */
.name = "d1",
.gpio = AT91_PIN_PB2,
.active_low = 1,
.default_trigger = "heartbeat",
},
};
static void __init csb637_board_init(void)
{
/* LED(s) */
at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
/* Serial */
at91_add_device_serial();
/* Ethernet */

178
arch/arm/mach-at91/board-ecbat91.c Normal file
View File

@ -0,0 +1,178 @@
/*
* linux/arch/arm/mach-at91rm9200/board-ecbat91.c
* Copyright (C) 2007 emQbit.com.
*
* We started from board-dk.c, which is Copyright (C) 2005 SAN People.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include "generic.h"
static void __init ecb_at91map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000, AT91RM9200_PQFP);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx & Tx only) */
at91_register_uart(AT91RM9200_ID_US0, 1, 0);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init ecb_at91init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata ecb_at91eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 0,
};
static struct at91_usbh_data __initdata ecb_at91usbh_data = {
.ports = 1,
};
static struct at91_mmc_data __initdata ecb_at91mmc_data = {
.slot_b = 0,
.wire4 = 1,
};
#if defined(CONFIG_MTD_DATAFLASH)
static struct mtd_partition __initdata my_flash0_partitions[] =
{
{ /* 0x8400 */
.name = "Darrell-loader",
.offset = 0,
.size = 12* 1056,
},
{
.name = "U-boot",
.offset = MTDPART_OFS_NXTBLK,
.size = 110 * 1056,
},
{ /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
.name = "UBoot-env",
.offset = MTDPART_OFS_NXTBLK,
.size = 8 * 1056,
},
{ /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
.name = "Kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = 1534 * 1056,
},
{ /* 190200 - jffs2 root filesystem */
.name = "Filesystem",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL, /* 26 sectors */
}
};
static struct flash_platform_data __initdata my_flash0_platform = {
.name = "Removable flash card",
.parts = my_flash0_partitions,
.nr_parts = ARRAY_SIZE(my_flash0_partitions)
};
#endif
static struct spi_board_info __initdata ecb_at91spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 10 * 1000 * 1000,
.bus_num = 0,
#if defined(CONFIG_MTD_DATAFLASH)
.platform_data = &my_flash0_platform,
#endif
},
{ /* User accessable spi - cs1 (250KHz) */
.modalias = "spi-cs1",
.chip_select = 1,
.max_speed_hz = 250 * 1000,
},
{ /* User accessable spi - cs2 (1MHz) */
.modalias = "spi-cs2",
.chip_select = 2,
.max_speed_hz = 1 * 1000 * 1000,
},
{ /* User accessable spi - cs3 (10MHz) */
.modalias = "spi-cs3",
.chip_select = 3,
.max_speed_hz = 10 * 1000 * 1000,
},
};
static void __init ecb_at91board_init(void)
{
/* Serial */
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&ecb_at91eth_data);
/* USB Host */
at91_add_device_usbh(&ecb_at91usbh_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* MMC */
at91_add_device_mmc(0, &ecb_at91mmc_data);
/* SPI */
at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
}
MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
/* Maintainer: emQbit.com */
.phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91rm9200_timer,
.map_io = ecb_at91map_io,
.init_irq = ecb_at91init_irq,
.init_machine = ecb_at91board_init,
MACHINE_END

199
arch/arm/mach-at91/board-sam9-l9260.c Normal file
View File

@ -0,0 +1,199 @@
/*
* linux/arch/arm/mach-at91/board-sam9-l9260.c
*
* Copyright (C) 2005 SAN People
* Copyright (C) 2006 Atmel
* Copyright (C) 2007 Olimex Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include "generic.h"
static void __init ek_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
};
/*
* USB Device port
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PC5,
.pullup_pin = 0, /* pull-up driven by UDC */
};
/*
* SPI devices.
*/
static struct spi_board_info ek_spi_devices[] = {
#if !defined(CONFIG_MMC_AT91)
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 1,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
{ /* DataFlash card */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
#endif
#endif
};
/*
* MACB Ethernet device
*/
static struct at91_eth_data __initdata ek_macb_data = {
.phy_irq_pin = AT91_PIN_PA7,
.is_rmii = 0,
};
/*
* NAND flash
*/
static struct mtd_partition __initdata ek_nand_partition[] = {
{
.name = "Bootloader Area",
.offset = 0,
.size = 10 * 1024 * 1024,
},
{
.name = "User Area",
.offset = 10 * 1024 * 1024,
.size = MTDPART_SIZ_FULL,
},
};
static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
{
*num_partitions = ARRAY_SIZE(ek_nand_partition);
return ek_nand_partition;
}
static struct at91_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
// .det_pin = ... not connected
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
.bus_width_16 = 1,
#else
.bus_width_16 = 0,
#endif
};
/*
* MCI (SD/MMC)
*/
static struct at91_mmc_data __initdata ek_mmc_data = {
.slot_b = 1,
.wire4 = 1,
.det_pin = AT91_PIN_PC8,
.wp_pin = AT91_PIN_PC4,
// .vcc_pin = ... not connected
};
static void __init ek_board_init(void)
{
/* Serial */
at91_add_device_serial();
/* USB Host */
at91_add_device_usbh(&ek_usbh_data);
/* USB Device */
at91_add_device_udc(&ek_udc_data);
/* SPI */
at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
/* NAND */
at91_add_device_nand(&ek_nand_data);
/* Ethernet */
at91_add_device_eth(&ek_macb_data);
/* MMC */
at91_add_device_mmc(0, &ek_mmc_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
}
MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
/* Maintainer: Olimex */
.phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91sam926x_timer,
.map_io = ek_map_io,
.init_irq = ek_init_irq,
.init_machine = ek_board_init,
MACHINE_END

83
arch/arm/mach-at91/board-sam9260ek.c
View File

@ -25,6 +25,8 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/at73c213.h>
#include <linux/clk.h>
#include <asm/hardware.h>
#include <asm/setup.h>
@ -37,29 +39,28 @@
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam926x_mc.h>
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 5 = USART0 .. USART5
* 6 = DBGU
*/
static struct at91_uart_config __initdata ek_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 3,
.tty_map = { 6, 0, 1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */
};
static void __init ek_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
/* Setup the serial ports and console */
at91_init_serial(&ek_uart_config);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
@ -84,6 +85,35 @@ static struct at91_udc_data __initdata ek_udc_data = {
};
/*
* Audio
*/
static struct at73c213_board_info at73c213_data = {
.ssc_id = 0,
.shortname = "AT91SAM9260-EK external DAC",
};
#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
static void __init at73c213_set_clk(struct at73c213_board_info *info)
{
struct clk *pck0;
struct clk *plla;
pck0 = clk_get(NULL, "pck0");
plla = clk_get(NULL, "plla");
/* AT73C213 MCK Clock */
at91_set_B_periph(AT91_PIN_PC1, 0); /* PCK0 */
clk_set_parent(pck0, plla);
clk_put(plla);
info->dac_clk = pck0;
}
#else
static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
#endif
/*
* SPI devices.
*/
@ -110,6 +140,8 @@ static struct spi_board_info ek_spi_devices[] = {
.chip_select = 0,
.max_speed_hz = 10 * 1000 * 1000,
.bus_num = 1,
.mode = SPI_MODE_1,
.platform_data = &at73c213_data,
},
#endif
};
@ -172,6 +204,24 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
// .vcc_pin = ... not connected
};
/*
* LEDs
*/
static struct gpio_led ek_leds[] = {
{ /* "bottom" led, green, userled1 to be defined */
.name = "ds5",
.gpio = AT91_PIN_PA6,
.active_low = 1,
.default_trigger = "none",
},
{ /* "power" led, yellow */
.name = "ds1",
.gpio = AT91_PIN_PA9,
.default_trigger = "heartbeat",
}
};
static void __init ek_board_init(void)
{
/* Serial */
@ -190,6 +240,11 @@ static void __init ek_board_init(void)
at91_add_device_mmc(0, &ek_mmc_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* SSC (to AT73C213) */
at73c213_set_clk(&at73c213_data);
at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
/* LEDs */
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
}
MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")

83
arch/arm/mach-at91/board-sam9261ek.c
View File

@ -26,6 +26,8 @@
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/spi/at73c213.h>
#include <linux/clk.h>
#include <linux/dm9000.h>
#include <linux/fb.h>
#include <linux/gpio_keys.h>
@ -44,22 +46,11 @@
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 2 = USART0 .. USART2
* 3 = DBGU
*/
static struct at91_uart_config __initdata ek_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 1,
.tty_map = { 3, -1, -1, -1 } /* ttyS0, ..., ttyS3 */
};
static void __init ek_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
@ -68,8 +59,11 @@ static void __init ek_map_io(void)
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
/* Setup the serial ports and console */
at91_init_serial(&ek_uart_config);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
@ -238,6 +232,35 @@ static void __init ek_add_device_ts(void)
static void __init ek_add_device_ts(void) {}
#endif
/*
* Audio
*/
static struct at73c213_board_info at73c213_data = {
.ssc_id = 1,
.shortname = "AT91SAM9261-EK external DAC",
};
#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
static void __init at73c213_set_clk(struct at73c213_board_info *info)
{
struct clk *pck2;
struct clk *plla;
pck2 = clk_get(NULL, "pck2");
plla = clk_get(NULL, "plla");
/* AT73C213 MCK Clock */
at91_set_B_periph(AT91_PIN_PB31, 0); /* PCK2 */
clk_set_parent(pck2, plla);
clk_put(plla);
info->dac_clk = pck2;
}
#else
static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
#endif
/*
* SPI devices
*/
@ -256,6 +279,7 @@ static struct spi_board_info ek_spi_devices[] = {
.bus_num = 0,
.platform_data = &ads_info,
.irq = AT91SAM9261_ID_IRQ0,
.controller_data = (void *) AT91_PIN_PA28, /* CS pin */
},
#endif
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
@ -271,6 +295,9 @@ static struct spi_board_info ek_spi_devices[] = {
.chip_select = 3,
.max_speed_hz = 10 * 1000 * 1000,
.bus_num = 0,
.mode = SPI_MODE_1,
.platform_data = &at73c213_data,
.controller_data = (void*) AT91_PIN_PA29, /* default for CS3 is PA6, but it must be PA29 */
},
#endif
};
@ -460,6 +487,29 @@ static void __init ek_add_device_buttons(void)
static void __init ek_add_device_buttons(void) {}
#endif
/*
* LEDs
*/
static struct gpio_led ek_leds[] = {
{ /* "bottom" led, green, userled1 to be defined */
.name = "ds7",
.gpio = AT91_PIN_PA14,
.active_low = 1,
.default_trigger = "none",
},
{ /* "top" led, green, userled2 to be defined */
.name = "ds8",
.gpio = AT91_PIN_PA13,
.active_low = 1,
.default_trigger = "none",
},
{ /* "power" led, yellow */
.name = "ds1",
.gpio = AT91_PIN_PA23,
.default_trigger = "heartbeat",
}
};
static void __init ek_board_init(void)
{
/* Serial */
@ -481,6 +531,9 @@ static void __init ek_board_init(void)
at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
/* Touchscreen */
ek_add_device_ts();
/* SSC (to AT73C213) */
at73c213_set_clk(&at73c213_data);
at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
#else
/* MMC */
at91_add_device_mmc(0, &ek_mmc_data);
@ -489,6 +542,8 @@ static void __init ek_board_init(void)
at91_add_device_lcdc(&ek_lcdc_data);
/* Push Buttons */
ek_add_device_buttons();
/* LEDs */
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
}
MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")

25
arch/arm/mach-at91/board-sam9263ek.c
View File

@ -43,29 +43,24 @@
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 2 = USART0 .. USART2
* 3 = DBGU
*/
static struct at91_uart_config __initdata ek_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 2,
.tty_map = { 3, 0, -1, -1, } /* ttyS0, ..., ttyS3 */
};
static void __init ek_map_io(void)
{
/* Initialize processor: 16.367 MHz crystal */
at91sam9263_initialize(16367660);
/* Setup the serial ports and console */
at91_init_serial(&ek_uart_config);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
@ -341,7 +336,7 @@ static struct gpio_led ek_leds[] = {
.name = "ds3",
.gpio = AT91_PIN_PB7,
.default_trigger = "heartbeat",
},
}
};

23
arch/arm/mach-at91/board-sam9rlek.c
View File

@ -29,29 +29,24 @@
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 3 = USART0 .. USART3
* 4 = DBGU
*/
static struct at91_uart_config __initdata ek_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 2,
.tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
};
static void __init ek_map_io(void)
{
/* Initialize processor: 12.000 MHz crystal */
at91sam9rl_initialize(12000000);
/* Setup the serial ports and console */
at91_init_serial(&ek_uart_config);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)

683
arch/arm/mach-at91/board-yl-9200.c Executable file
View File

@ -0,0 +1,683 @@
/*
* linux/arch/arm/mach-at91/board-yl-9200.c
*
* Adapted from:
*various board files in
* /arch/arm/mach-at91
* modifications to convert to YL-9200 platform
* Copyright (C) 2007 S.Birtles
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
/*#include <linux/can_bus/candata.h>*/
#include <linux/spi/ads7846.h>
#include <linux/mtd/physmap.h>
/*#include <sound/gpio_sounder.h>*/
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91rm9200_mc.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include "generic.h"
#include <asm/arch/at91_pio.h>
#define YL_9200_FLASH_BASE AT91_CHIPSELECT_0
#define YL_9200_FLASH_SIZE 0x800000
/*
* Serial port configuration.
* 0 .. 3 = USART0 .. USART3
* 4 = DBGU
*atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL
*atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL
*atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL
*atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL
*atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL
* on the YL-9200 we are sitting at the following
*ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
*ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL
*/
/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/
static struct at91_uart_config __initdata yl_9200_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 3,
.tty_map = { 4, 1, 0, -1, -1 } /* ttyS0, ..., ttyS4 */
};
static void __init yl_9200_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
/*Also initialises register clocks & gpio*/
at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/
/* Setup the serial ports and console */
at91_init_serial(&yl_9200_uart_config);
/* Setup the LEDs D2=PB17,D3=PB16 */
at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/
}
static void __init yl_9200_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata yl_9200_eth_data = {
.phy_irq_pin = AT91_PIN_PB28,
.is_rmii = 1,
};
static struct at91_usbh_data __initdata yl_9200_usbh_data = {
.ports = 1, /* this should be 1 not 2 for the Yl9200*/
};
static struct at91_udc_data __initdata yl_9200_udc_data = {
/*on sheet 7 Schemitic rev 1.0*/
.pullup_pin = AT91_PIN_PC4,
.vbus_pin= AT91_PIN_PC5,
.pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/
};
/*
static struct at91_cf_data __initdata yl_9200_cf_data = {
TODO S.BIRTLES
.det_pin = AT91_PIN_xxx,
.rst_pin = AT91_PIN_xxx,
.irq_pin = ... not connected
.vcc_pin = ... always powered
};
*/
static struct at91_mmc_data __initdata yl_9200_mmc_data = {
.det_pin = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/
/* .wp_pin = ... not connected SHEET7*/
.slot_b = 0,
.wire4 = 1,
};
/* --------------------------------------------------------------------
* Touch screen
* -------------------------------------------------------------------- */
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
static int ads7843_pendown_state(void)
{
return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
}
static void __init at91_init_device_ts(void)
{
/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C
THAT IS TO SAY THAT MISO,MOSI,SPCK AND CS are already configured
we only need to enable the other datapins which are:
PB10/RK1 BUSY
*/
/* Touchscreen BUSY signal , pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/
at91_set_gpio_input(AT91_PIN_PB10, 1);
}
#else
static void __init at91_init_device_ts(void) {}
#endif
static struct ads7846_platform_data ads_info = {
.model = 7843,
.x_min = 150,
.x_max = 3830,
.y_min = 190,
.y_max = 3830,
.vref_delay_usecs = 100,
/* for a 8" touch screen*/
//.x_plate_ohms = 603, //= 450, S.Birtles TODO
//.y_plate_ohms = 332, //= 250, S.Birtles TODO
/*for a 10.4" touch screen*/
//.x_plate_ohms =611,
//.y_plate_ohms =325,
.x_plate_ohms = 576,
.y_plate_ohms = 366,
//
.pressure_max = 15000, /*generally nonsense on the 7843*/
/*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/
.debounce_max = 1,
.debounce_rep = 0,
.debounce_tol = (~0),
.get_pendown_state = ads7843_pendown_state,
};
/*static struct canbus_platform_data can_info = {
.model = 2510,
};
*/
static struct spi_board_info yl_9200_spi_devices[] = {
/*this sticks it at:
/sys/devices/platform/atmel_spi.0/spi0.0
/sys/bus/platform/devices/
Documentation/spi IIRC*/
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
/*(this IS correct 04-NOV-2007)*/
{
.modalias = "ads7846", /* because the driver is called ads7846*/
.chip_select = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */
/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/
/*.controller_data =AT91_PIN_PA3 ,*/
.max_speed_hz = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */
.bus_num = 0,
.platform_data = &ads_info,
.irq = AT91_PIN_PB11,
},
#endif
/*we need to put our CAN driver data here!!*/
/*THIS IS ALL DUMMY DATA*/
/* {
.modalias = "mcp2510", //DUMMY for MCP2510 chip
.chip_select = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */
/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */
/* .controller_data =AT91_PIN_PA4 ,
.max_speed_hz = 25000 * 26,
.bus_num = 0,
.platform_data = &can_info,
.irq = AT91_PIN_PC0,
},
*/
//max SPI chip needs to go here
};
static struct mtd_partition __initdata yl_9200_nand_partition[] = {
{
.name = "AT91 NAND partition 1, boot",
.offset = 0,
.size = 1 * SZ_256K
},
{
.name = "AT91 NAND partition 2, kernel",
.offset = 1 * SZ_256K,
.size = 2 * SZ_1M - 1 * SZ_256K
},
{
.name = "AT91 NAND partition 3, filesystem",
.offset = 2 * SZ_1M,
.size = 14 * SZ_1M
},
{
.name = "AT91 NAND partition 4, storage",
.offset = 16 * SZ_1M,
.size = 16 * SZ_1M
},
{
.name = "AT91 NAND partition 5, ext-fs",
.offset = 32 * SZ_1M,
.size = 32 * SZ_1M
},
};
static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
{
*num_partitions = ARRAY_SIZE(yl_9200_nand_partition);
return yl_9200_nand_partition;
}
static struct at91_nand_data __initdata yl_9200_nand_data = {
.ale= 6,
.cle= 7,
/*.det_pin = AT91_PIN_PCxx,*/ /*we don't have a det pin because NandFlash is fixed to board*/
.rdy_pin = AT91_PIN_PC14, /*R/!B Sheet10*/
.enable_pin = AT91_PIN_PC15, /*!CE Sheet10 */
.partition_info = nand_partitions,
};
/*
TODO S.Birtles
potentially a problem with the size above
physmap platform flash device: 00800000 at 10000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
NOR chip too large to fit in mapping. Attempting to cope...
Intel/Sharp Extended Query Table at 0x0031
Using buffer write method
cfi_cmdset_0001: Erase suspend on write enabled
Reducing visibility of 16384KiB chip to 8192KiB
*/
static struct mtd_partition yl_9200_flash_partitions[] = {
{
.name = "Bootloader",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_WRITEABLE /* force read-only */
},{
.name = "Kernel",
.size = 0x001C0000,
.offset = 0x00040000,
},{
.name = "Filesystem",
.size = MTDPART_SIZ_FULL,
.offset = 0x00200000
}
};
static struct physmap_flash_data yl_9200_flash_data = {
.width = 2,
.parts = yl_9200_flash_partitions,
.nr_parts = ARRAY_SIZE(yl_9200_flash_partitions),
};
static struct resource yl_9200_flash_resources[] = {
{
.start = YL_9200_FLASH_BASE,
.end = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device yl_9200_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &yl_9200_flash_data,
},
.resource = yl_9200_flash_resources,
.num_resources = ARRAY_SIZE(yl_9200_flash_resources),
};
static struct gpio_led yl_9200_leds[] = {
/*D2 &D3 are passed directly in via at91_init_leds*/
{
.name = "led4", /*D4*/
.gpio = AT91_PIN_PB15,
.active_low = 1,
.default_trigger = "heartbeat",
/*.default_trigger = "timer",*/
},
{
.name = "led5", /*D5*/
.gpio = AT91_PIN_PB8,
.active_low = 1,
.default_trigger = "heartbeat",
}
};
//static struct gpio_sounder yl_9200_sounder[] = {*/
/*This is a simple speaker attached to a gpo line*/
// {
// .name = "Speaker", /*LS1*/
// .gpio = AT91_PIN_PA22,
// .active_low = 0,
// .default_trigger = "heartbeat",
/*.default_trigger = "timer",*/
// },
//};
static struct i2c_board_info __initdata yl_9200_i2c_devices[] = {
{
/*TODO*/
I2C_BOARD_INFO("CS4334", 0x00),
}
};
/*
* GPIO Buttons
*/
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
static struct gpio_keys_button yl_9200_buttons[] = {
{
.gpio = AT91_PIN_PA24,
.code = BTN_2,
.desc = "SW2",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB1,
.code = BTN_3,
.desc = "SW3",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB2,
.code = BTN_4,
.desc = "SW4",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB6,
.code = BTN_5,
.desc = "SW5",
.active_low = 1,
.wakeup = 1,
},
};
static struct gpio_keys_platform_data yl_9200_button_data = {
.buttons = yl_9200_buttons,
.nbuttons = ARRAY_SIZE(yl_9200_buttons),
};
static struct platform_device yl_9200_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &yl_9200_button_data,
}
};
static void __init yl_9200_add_device_buttons(void)
{
//SW2
at91_set_gpio_input(AT91_PIN_PA24, 0);
at91_set_deglitch(AT91_PIN_PA24, 1);
//SW3
at91_set_gpio_input(AT91_PIN_PB1, 0);
at91_set_deglitch(AT91_PIN_PB1, 1);
//SW4
at91_set_gpio_input(AT91_PIN_PB2, 0);
at91_set_deglitch(AT91_PIN_PB2, 1);
//SW5
at91_set_gpio_input(AT91_PIN_PB6, 0);
at91_set_deglitch(AT91_PIN_PB6, 1);
at91_set_gpio_output(AT91_PIN_PB7, 1); /* #TURN BUTTONS ON, SHEET 5 of schematics */
platform_device_register(&yl_9200_button_device);
}
#else
static void __init yl_9200_add_device_buttons(void) {}
#endif
#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
#include <video/s1d13xxxfb.h>
/* EPSON S1D13806 FB (discontinued chip)*/
/* EPSON S1D13506 FB */
#define AT91_FB_REG_BASE 0x80000000L
#define AT91_FB_REG_SIZE 0x200
#define AT91_FB_VMEM_BASE 0x80200000L
#define AT91_FB_VMEM_SIZE 0x200000L
/*#define S1D_DISPLAY_WIDTH 640*/
/*#define S1D_DISPLAY_HEIGHT 480*/
static void __init yl_9200_init_video(void)
{
at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
at91_sys_write(AT91_PIOC + PIO_BSR,0);
at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
at91_sys_write( AT91_SMC_CSR(2),
AT91_SMC_NWS_(0x4) |
AT91_SMC_WSEN |
AT91_SMC_TDF_(0x100) |
AT91_SMC_DBW
);
}
static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] =
{
{S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
{S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
{S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
{S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
{S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
{S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
{S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
{S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
{S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
{S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
{S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
{S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
{S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
{S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
{S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
{S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
{S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
{S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
{S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
{S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
{S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
{S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
{S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
{S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
{S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
{S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
{S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
{S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
{S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
{S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
{S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
{S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
{S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
{S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
{S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
{S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
{S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
{S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
{S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
{S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
{S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
{S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
{S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
{S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
{S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
{S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
{S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
{S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
{S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
{S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
{S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
{S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
{S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
{S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
{S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
{S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
{S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
{S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
{S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
{S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
{S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
{S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
{S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
{S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
{S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
{S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
{S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
{S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
{S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
{S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
{S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
{S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
{S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
{S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
{S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
{S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
{S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
{S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
{S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
{S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
{S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
{S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
{S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
{S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
{S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
{S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
{S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
{S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
{S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
{S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
{S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
{S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
{S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
{S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
{S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
{S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
{S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
{S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
{S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
{S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
{S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
{S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
{S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
{S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
{S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
};
static u64 s1dfb_dmamask = 0xffffffffUL;
static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = {
.initregs = yl_9200_s1dfb_initregs,
.initregssize = ARRAY_SIZE(yl_9200_s1dfb_initregs),
.platform_init_video = yl_9200_init_video,
};
static struct resource yl_9200_s1dfb_resource[] = {
[0] = { /* video mem */
.name = "s1d13xxxfb memory",
/* .name = "s1d13806 memory",*/
.start = AT91_FB_VMEM_BASE,
.end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
.flags = IORESOURCE_MEM,
},
[1] = { /* video registers */
.name = "s1d13xxxfb registers",
/* .name = "s1d13806 registers",*/
.start = AT91_FB_REG_BASE,
.end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device yl_9200_s1dfb_device = {
/*TODO S.Birtles , really we need the chip revision in here as well*/
.name = "s1d13806fb",
/* .name = "s1d13506fb",*/
.id = -1,
.dev = {
/*TODO theres a waring here!!*/
/*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/
.dma_mask = &s1dfb_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &yl_9200_s1dfb_pdata,
},
.resource = yl_9200_s1dfb_resource,
.num_resources = ARRAY_SIZE(yl_9200_s1dfb_resource),
};
void __init yl_9200_add_device_video(void)
{
platform_device_register(&yl_9200_s1dfb_device);
}
#else
void __init yl_9200_add_device_video(void) {}
#endif
/*this is not called first , yl_9200_map_io is called first*/
static void __init yl_9200_board_init(void)
{
/* Serial */
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&yl_9200_eth_data);
/* USB Host */
at91_add_device_usbh(&yl_9200_usbh_data);
/* USB Device */
at91_add_device_udc(&yl_9200_udc_data);
/* pullup_pin it is actually active low, but this is not needed, driver sets it up */
/*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/
/* Compact Flash */
/*at91_add_device_cf(&yl_9200_cf_data);*/
/* I2C */
at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices));
/* SPI */
/*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/
/* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the max 485 NOT SPI*/
/*touch screen and CAN*/
at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices));
/*Basically the TS uses PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/
/* we need this incase the board is running without a touch screen*/
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
at91_init_device_ts(); /*init the touch screen device*/
#endif
/* DataFlash card */
at91_add_device_mmc(0, &yl_9200_mmc_data);
/* NAND */
at91_add_device_nand(&yl_9200_nand_data);
/* NOR Flash */
platform_device_register(&yl_9200_flash);
/* LEDs. Note!! this does not include the led's we passed for the processor status */
at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds));
/* VGA */
/*this is self registered by including the s1d13xxx chip in the kernel build*/
yl_9200_add_device_video();
/* Push Buttons */
yl_9200_add_device_buttons();
/*TODO fixup the Sounder */
// yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder));
}
MACHINE_START(YL9200, "uCdragon YL-9200")
/* Maintainer: S.Birtles*/
.phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91rm9200_timer,
.map_io = yl_9200_map_io,
.init_irq = yl_9200_init_irq,
.init_machine = yl_9200_board_init,
MACHINE_END

165
arch/arm/mach-at91/pm.c
View File

@ -26,12 +26,135 @@
#include <asm/mach-types.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91rm9200_mc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/cpu.h>
#include "generic.h"
#ifdef CONFIG_ARCH_AT91RM9200
#include <asm/arch/at91rm9200_mc.h>
/*
* The AT91RM9200 goes into self-refresh mode with this command, and will
* terminate self-refresh automatically on the next SDRAM access.
*/
#define sdram_selfrefresh_enable() at91_sys_write(AT91_SDRAMC_SRR, 1)
#define sdram_selfrefresh_disable() do {} while (0)
#elif defined(CONFIG_ARCH_AT91CAP9)
#include <asm/arch/at91cap9_ddrsdr.h>
static u32 saved_lpr;
static inline void sdram_selfrefresh_enable(void)
{
u32 lpr;
saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
}
#define sdram_selfrefresh_disable() at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
#else
#include <asm/arch/at91sam9_sdramc.h>
static u32 saved_lpr;
static inline void sdram_selfrefresh_enable(void)
{
u32 lpr;
saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
}
#define sdram_selfrefresh_disable() at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
/*
* FIXME: The AT91SAM9263 has a second EBI controller which may have
* additional SDRAM. pm_slowclock.S will require a similar fix.
*/
#endif
/*
* Show the reason for the previous system reset.
*/
#if defined(AT91_SHDWC)
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_shdwc.h>
static void __init show_reset_status(void)
{
static char reset[] __initdata = "reset";
static char general[] __initdata = "general";
static char wakeup[] __initdata = "wakeup";
static char watchdog[] __initdata = "watchdog";
static char software[] __initdata = "software";
static char user[] __initdata = "user";
static char unknown[] __initdata = "unknown";
static char signal[] __initdata = "signal";
static char rtc[] __initdata = "rtc";
static char rtt[] __initdata = "rtt";
static char restore[] __initdata = "power-restored";
char *reason, *r2 = reset;
u32 reset_type, wake_type;
reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
wake_type = at91_sys_read(AT91_SHDW_SR);
switch (reset_type) {
case AT91_RSTC_RSTTYP_GENERAL:
reason = general;
break;
case AT91_RSTC_RSTTYP_WAKEUP:
/* board-specific code enabled the wakeup sources */
reason = wakeup;
/* "wakeup signal" */
if (wake_type & AT91_SHDW_WAKEUP0)
r2 = signal;
else {
r2 = reason;
if (wake_type & AT91_SHDW_RTTWK) /* rtt wakeup */
reason = rtt;
else if (wake_type & AT91_SHDW_RTCWK) /* rtc wakeup */
reason = rtc;
else if (wake_type == 0) /* power-restored wakeup */
reason = restore;
else /* unknown wakeup */
reason = unknown;
}
break;
case AT91_RSTC_RSTTYP_WATCHDOG:
reason = watchdog;
break;
case AT91_RSTC_RSTTYP_SOFTWARE:
reason = software;
break;
case AT91_RSTC_RSTTYP_USER:
reason = user;
break;
default:
reason = unknown;
break;
}
pr_info("AT91: Starting after %s %s\n", reason, r2);
}
#else
static void __init show_reset_status(void) {}
#endif
static int at91_pm_valid_state(suspend_state_t state)
{
@ -125,6 +248,11 @@ EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
static void (*slow_clock)(void);
#ifdef CONFIG_AT91_SLOW_CLOCK
extern void at91_slow_clock(void);
extern u32 at91_slow_clock_sz;
#endif
static int at91_pm_enter(suspend_state_t state)
{
@ -158,11 +286,14 @@ static int at91_pm_enter(suspend_state_t state)
* turning off the main oscillator; reverse on wakeup.
*/
if (slow_clock) {
#ifdef CONFIG_AT91_SLOW_CLOCK
/* copy slow_clock handler to SRAM, and call it */
memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
#endif
slow_clock();
break;
} else {
/* DEVELOPMENT ONLY */
pr_info("AT91: PM - no slow clock mode yet ...\n");
pr_info("AT91: PM - no slow clock mode enabled ...\n");
/* FALLTHROUGH leaving master clock alone */
}
@ -175,13 +306,15 @@ static int at91_pm_enter(suspend_state_t state)
case PM_SUSPEND_STANDBY:
/*
* NOTE: the Wait-for-Interrupt instruction needs to be
* in icache so the SDRAM stays in self-refresh mode until
* the wakeup IRQ occurs.
* in icache so no SDRAM accesses are needed until the
* wakeup IRQ occurs and self-refresh is terminated.
*/
asm("b 1f; .align 5; 1:");
asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
at91_sys_write(AT91_SDRAMC_SRR, 1); /* self-refresh mode */
/* fall though to next state */
sdram_selfrefresh_enable();
asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
sdram_selfrefresh_disable();
break;
case PM_SUSPEND_ON:
asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
@ -196,6 +329,7 @@ static int at91_pm_enter(suspend_state_t state)
at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
error:
sdram_selfrefresh_disable();
target_state = PM_SUSPEND_ON;
at91_irq_resume();
at91_gpio_resume();
@ -220,21 +354,20 @@ static struct platform_suspend_ops at91_pm_ops ={
static int __init at91_pm_init(void)
{
printk("AT91: Power Management\n");
#ifdef CONFIG_AT91_PM_SLOW_CLOCK
/* REVISIT allocations of SRAM should be dynamically managed.
* FIQ handlers and other components will want SRAM/TCM too...
*/
slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K));
memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz);
#ifdef CONFIG_AT91_SLOW_CLOCK
slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
#endif
/* Disable SDRAM low-power mode. Cannot be used with self-refresh. */
pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
#ifdef CONFIG_ARCH_AT91RM9200
/* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
at91_sys_write(AT91_SDRAMC_LPR, 0);
#endif
suspend_set_ops(&at91_pm_ops);
show_reset_status();
return 0;
}
arch_initcall(at91_pm_init);

2
arch/arm/mach-clps711x/Kconfig
View File

@ -31,6 +31,8 @@ config ARCH_EDB7211
bool "EDB7211"
select ISA
select ARCH_DISCONTIGMEM_ENABLE
select ARCH_SPARSEMEM_ENABLE
select ARCH_SELECT_MEMORY_MODEL
help
Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
evaluation board.

2
arch/arm/mach-ep93xx/Makefile
View File

@ -1,7 +1,7 @@
#
# Makefile for the linux kernel.
#
obj-y := core.o clock.o
obj-y := core.o clock.o gpio.o
obj-m :=
obj-n :=
obj- :=

109
arch/arm/mach-ep93xx/core.c
View File

@ -159,7 +159,7 @@ static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c };
static void update_gpio_int_params(unsigned port)
void ep93xx_gpio_update_int_params(unsigned port)
{
BUG_ON(port > 2);
@ -175,99 +175,11 @@ static void update_gpio_int_params(unsigned port)
EP93XX_GPIO_REG(int_en_register_offset[port]));
}
/* Port ordering is: A B F D E C G H */
static const u8 data_register_offset[8] = {
0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40,
};
static const u8 data_direction_register_offset[8] = {
0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44,
};
#define GPIO_IN 0
#define GPIO_OUT 1
static void ep93xx_gpio_set_direction(unsigned line, int direction)
void ep93xx_gpio_int_mask(unsigned line)
{
unsigned int data_direction_register;
unsigned long flags;
unsigned char v;
data_direction_register =
EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
local_irq_save(flags);
if (direction == GPIO_OUT) {
if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) {
/* Port A/B/F */
gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
update_gpio_int_params(line >> 3);
}
v = __raw_readb(data_direction_register);
v |= 1 << (line & 7);
__raw_writeb(v, data_direction_register);
} else if (direction == GPIO_IN) {
v = __raw_readb(data_direction_register);
v &= ~(1 << (line & 7));
__raw_writeb(v, data_direction_register);
}
local_irq_restore(flags);
gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
}
int gpio_direction_input(unsigned gpio)
{
if (gpio > EP93XX_GPIO_LINE_MAX)
return -EINVAL;
ep93xx_gpio_set_direction(gpio, GPIO_IN);
return 0;
}
EXPORT_SYMBOL(gpio_direction_input);
int gpio_direction_output(unsigned gpio, int value)
{
if (gpio > EP93XX_GPIO_LINE_MAX)
return -EINVAL;
gpio_set_value(gpio, value);
ep93xx_gpio_set_direction(gpio, GPIO_OUT);
return 0;
}
EXPORT_SYMBOL(gpio_direction_output);
int gpio_get_value(unsigned gpio)
{
unsigned int data_register;
data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
return !!(__raw_readb(data_register) & (1 << (gpio & 7)));
}
EXPORT_SYMBOL(gpio_get_value);
void gpio_set_value(unsigned gpio, int value)
{
unsigned int data_register;
unsigned long flags;
unsigned char v;
data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
local_irq_save(flags);
v = __raw_readb(data_register);
if (value)
v |= 1 << (gpio & 7);
else
v &= ~(1 << (gpio & 7));
__raw_writeb(v, data_register);
local_irq_restore(flags);
}
EXPORT_SYMBOL(gpio_set_value);
/*************************************************************************
* EP93xx IRQ handling
*************************************************************************/
@ -316,7 +228,7 @@ static void ep93xx_gpio_irq_ack(unsigned int irq)
if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
update_gpio_int_params(port);
ep93xx_gpio_update_int_params(port);
}
__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
@ -332,7 +244,7 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
gpio_int_unmasked[port] &= ~port_mask;
update_gpio_int_params(port);
ep93xx_gpio_update_int_params(port);
__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}
@ -343,7 +255,7 @@ static void ep93xx_gpio_irq_mask(unsigned int irq)
int port = line >> 3;
gpio_int_unmasked[port] &= ~(1 << (line & 7));
update_gpio_int_params(port);
ep93xx_gpio_update_int_params(port);
}
static void ep93xx_gpio_irq_unmask(unsigned int irq)
@ -352,7 +264,7 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq)
int port = line >> 3;
gpio_int_unmasked[port] |= 1 << (line & 7);
update_gpio_int_params(port);
ep93xx_gpio_update_int_params(port);
}
@ -368,7 +280,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
const int port = gpio >> 3;
const int port_mask = 1 << (gpio & 7);
ep93xx_gpio_set_direction(gpio, GPIO_IN);
gpio_direction_output(gpio, gpio_get_value(gpio));
switch (type) {
case IRQT_RISING:
@ -411,7 +323,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
desc->status &= ~IRQ_TYPE_SENSE_MASK;
desc->status |= type & IRQ_TYPE_SENSE_MASK;
update_gpio_int_params(port);
ep93xx_gpio_update_int_params(port);
return 0;
}
@ -549,6 +461,7 @@ static struct platform_device ep93xx_ohci_device = {
.resource = ep93xx_ohci_resources,
};
extern void ep93xx_gpio_init(void);
void __init ep93xx_init_devices(void)
{
@ -562,6 +475,8 @@ void __init ep93xx_init_devices(void)
__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
__raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
ep93xx_gpio_init();
amba_device_register(&uart1_device, &iomem_resource);
amba_device_register(&uart2_device, &iomem_resource);
amba_device_register(&uart3_device, &iomem_resource);

158
arch/arm/mach-ep93xx/gpio.c Normal file
View File

@ -0,0 +1,158 @@
/*
* linux/arch/arm/mach-ep93xx/gpio.c
*
* Generic EP93xx GPIO handling
*
* Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
*
* Based on code originally from:
* linux/arch/arm/mach-ep93xx/core.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <asm/arch/ep93xx-regs.h>
#include <asm/io.h>
#include <asm/gpio.h>
struct ep93xx_gpio_chip {
struct gpio_chip chip;
unsigned int data_reg;
unsigned int data_dir_reg;
};
#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
/* From core.c */
extern void ep93xx_gpio_int_mask(unsigned line);
extern void ep93xx_gpio_update_int_params(unsigned port);
static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
unsigned long flags;
u8 v;
local_irq_save(flags);
v = __raw_readb(ep93xx_chip->data_dir_reg);
v &= ~(1 << offset);
__raw_writeb(v, ep93xx_chip->data_dir_reg);
local_irq_restore(flags);
return 0;
}
static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int val)
{
struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
unsigned long flags;
int line;
u8 v;
local_irq_save(flags);
/* Set the value */
v = __raw_readb(ep93xx_chip->data_reg);
if (val)
v |= (1 << offset);
else
v &= ~(1 << offset);
__raw_writeb(v, ep93xx_chip->data_reg);
/* Drive as an output */
line = chip->base + offset;
if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
/* Ports A/B/F */
ep93xx_gpio_int_mask(line);
ep93xx_gpio_update_int_params(line >> 3);
}
v = __raw_readb(ep93xx_chip->data_dir_reg);
v |= (1 << offset);
__raw_writeb(v, ep93xx_chip->data_dir_reg);
local_irq_restore(flags);
return 0;
}
static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
}
static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
unsigned long flags;
u8 v;
local_irq_save(flags);
v = __raw_readb(ep93xx_chip->data_reg);
if (val)
v |= (1 << offset);
else
v &= ~(1 << offset);
__raw_writeb(v, ep93xx_chip->data_reg);
local_irq_restore(flags);
}
static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
u8 data_reg, data_dir_reg;
int i;
data_reg = __raw_readb(ep93xx_chip->data_reg);
data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
for (i = 0; i < chip->ngpio; i++)
seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i,
(data_reg & (1 << i)) ? "set" : "clear",
(data_dir_reg & (1 << i)) ? "out" : "in");
}
#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
{ \
.chip = { \
.label = name, \
.direction_input = ep93xx_gpio_direction_input, \
.direction_output = ep93xx_gpio_direction_output, \
.get = ep93xx_gpio_get, \
.set = ep93xx_gpio_set, \
.dbg_show = ep93xx_gpio_dbg_show, \
.base = base_gpio, \
.ngpio = 8, \
}, \
.data_reg = EP93XX_GPIO_REG(dr), \
.data_dir_reg = EP93XX_GPIO_REG(ddr), \
}
static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
EP93XX_GPIO_BANK("C", 0x30, 0x34, 40),
EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
EP93XX_GPIO_BANK("F", 0x08, 0x18, 16),
EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
};
void __init ep93xx_gpio_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++)
gpiochip_add(&ep93xx_gpio_banks[i].chip);
}

8
arch/arm/mach-iop32x/Kconfig
View File

@ -34,14 +34,6 @@ config MACH_N2100
Say Y here if you want to run your kernel on the Thecus n2100
NAS appliance.
config IOP3XX_ATU
bool "Enable the PCI Controller"
default y
help
Say Y here if you want the IOP to initialize its PCI Controller.
Say N if the IOP is an add in card, the host system owns the PCI
bus in this case.
config MACH_EM7210
bool "Enable support for the Lanner EM7210"
help

11
arch/arm/mach-iop32x/iq31244.c
View File

@ -178,10 +178,9 @@ static struct hw_pci iq31244_pci __initdata = {
static int __init iq31244_pci_init(void)
{
if (is_ep80219()) {
if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
pci_common_init(&ep80219_pci);
} else if (machine_is_iq31244()) {
if (is_ep80219())
pci_common_init(&ep80219_pci);
else if (machine_is_iq31244()) {
if (is_80219()) {
printk("note: iq31244 board type has been selected\n");
printk("note: to select ep80219 operation:\n");
@ -190,9 +189,7 @@ static int __init iq31244_pci_init(void)
printk("\t2/ update boot loader to pass"
" the ep80219 id: %d\n", MACH_TYPE_EP80219);
}
if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
pci_common_init(&iq31244_pci);
pci_common_init(&iq31244_pci);
}
return 0;

2
arch/arm/mach-iop32x/iq80321.c
View File

@ -106,7 +106,7 @@ static struct hw_pci iq80321_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.preinit = iop3xx_pci_preinit_cond,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80321_pci_map_irq,
};

8
arch/arm/mach-iop33x/Kconfig
View File

@ -16,14 +16,6 @@ config MACH_IQ80332
Say Y here if you want to run your kernel on the Intel IQ80332
evaluation kit for the IOP332 chipset.
config IOP3XX_ATU
bool "Enable the PCI Controller"
default y
help
Say Y here if you want the IOP to initialize its PCI Controller.
Say N if the IOP is an add in card, the host system owns the PCI
bus in this case.
endmenu
endif

2
arch/arm/mach-iop33x/iq80331.c
View File

@ -89,7 +89,7 @@ static struct hw_pci iq80331_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.preinit = iop3xx_pci_preinit_cond,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80331_pci_map_irq,
};

2
arch/arm/mach-iop33x/iq80332.c
View File

@ -89,7 +89,7 @@ static struct hw_pci iq80332_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.preinit = iop3xx_pci_preinit_cond,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80332_pci_map_irq,
};

3
arch/arm/mach-ks8695/Makefile
View File

@ -11,5 +11,8 @@ obj- :=
# PCI support is optional
obj-$(CONFIG_PCI) += pci.o
# LEDs
obj-$(CONFIG_LEDS) += leds.o
# Board-specific support
obj-$(CONFIG_MACH_KS8695) += board-micrel.o

21
arch/arm/mach-ks8695/devices.c
View File

@ -176,6 +176,27 @@ static void __init ks8695_add_device_watchdog(void) {}
#endif
/* --------------------------------------------------------------------
* LEDs
* -------------------------------------------------------------------- */
#if defined(CONFIG_LEDS)
short ks8695_leds_cpu = -1;
short ks8695_leds_timer = -1;
void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
{
/* Enable GPIO to access the LEDs */
gpio_direction_output(cpu_led, 1);
gpio_direction_output(timer_led, 1);
ks8695_leds_cpu = cpu_led;
ks8695_leds_timer = timer_led;
}
#else
void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
#endif
/* -------------------------------------------------------------------- */
/*

94
arch/arm/mach-ks8695/leds.c Normal file
View File

@ -0,0 +1,94 @@
/*
* LED driver for KS8695-based boards.
*
* Copyright (C) Andrew Victor
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <asm/mach-types.h>
#include <asm/leds.h>
#include <asm/arch/devices.h>
#include <asm/arch/gpio.h>
static inline void ks8695_led_on(unsigned int led)
{
gpio_set_value(led, 0);
}
static inline void ks8695_led_off(unsigned int led)
{
gpio_set_value(led, 1);
}
static inline void ks8695_led_toggle(unsigned int led)
{
unsigned long is_off = gpio_get_value(led);
if (is_off)
ks8695_led_on(led);
else
ks8695_led_off(led);
}
/*
* Handle LED events.
*/
static void ks8695_leds_event(led_event_t evt)
{
unsigned long flags;
local_irq_save(flags);
switch(evt) {
case led_start: /* System startup */
ks8695_led_on(ks8695_leds_cpu);
break;
case led_stop: /* System stop / suspend */
ks8695_led_off(ks8695_leds_cpu);
break;
#ifdef CONFIG_LEDS_TIMER
case led_timer: /* Every 50 timer ticks */
ks8695_led_toggle(ks8695_leds_timer);
break;
#endif
#ifdef CONFIG_LEDS_CPU
case led_idle_start: /* Entering idle state */
ks8695_led_off(ks8695_leds_cpu);
break;
case led_idle_end: /* Exit idle state */
ks8695_led_on(ks8695_leds_cpu);
break;
#endif
default:
break;
}
local_irq_restore(flags);
}
static int __init leds_init(void)
{
if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
return -ENODEV;
leds_event = ks8695_leds_event;
leds_event(led_start);
return 0;
}
__initcall(leds_init);

30
arch/arm/mach-ns9xxx/Kconfig
View File

@ -2,9 +2,26 @@ if ARCH_NS9XXX
menu "NS9xxx Implementations"
config NS9XXX_HAVE_SERIAL8250
bool
config PROCESSOR_NS9360
bool
config MODULE_CC9P9360
bool
select PROCESSOR_NS9360
config BOARD_A9M9750DEV
select NS9XXX_HAVE_SERIAL8250
bool
config BOARD_JSCC9P9360
bool
config MACH_CC9P9360DEV
bool "ConnectCore 9P 9360 on an A9M9750 Devboard"
select PROCESSOR_NS9360
select MODULE_CC9P9360
select BOARD_A9M9750DEV
help
Say Y here if you are using the Digi ConnectCore 9P 9360
@ -12,21 +29,12 @@ config MACH_CC9P9360DEV
config MACH_CC9P9360JS
bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard"
select PROCESSOR_NS9360
select MODULE_CC9P9360
select BOARD_JSCC9P9360
help
Say Y here if you are using the Digi ConnectCore 9P 9360
on an JSCC9P9360 Development Board.
config PROCESSOR_NS9360
bool
config BOARD_A9M9750DEV
bool
config BOARD_JSCC9P9360
bool
endmenu
endif

7
arch/arm/mach-ns9xxx/Makefile
View File

@ -1,7 +1,12 @@
obj-y := irq.o time.o generic.o gpio.o
obj-y := clock.o generic.o gpio.o irq.o
obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o
obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o
obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o
# platform devices
obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o

2
arch/arm/mach-ns9xxx/Makefile.boot
View File

@ -1,2 +1,2 @@
zreladdr-y := 0x108000
zreladdr-y := 0x8000
params_phys-y := 0x100

69
arch/arm/mach-ns9xxx/board-a9m9750dev.c
View File

@ -8,15 +8,14 @@
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/irq.h>
#include <asm/mach/map.h>
#include <asm/gpio.h>
#include <asm/arch-ns9xxx/board.h>
#include <asm/arch-ns9xxx/regs-sys.h>
#include <asm/arch-ns9xxx/processor-ns9360.h>
#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
#include <asm/arch-ns9xxx/regs-mem.h>
#include <asm/arch-ns9xxx/regs-bbu.h>
#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
@ -105,9 +104,9 @@ void __init board_a9m9750dev_init_irq(void)
int i;
if (gpio_request(11, "board a9m9750dev extirq2") == 0)
ns9xxx_gpio_configure(11, 0, 1);
ns9360_gpio_configure(11, 0, 1);
else
printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n",
printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n",
__func__);
for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
@ -116,69 +115,16 @@ void __init board_a9m9750dev_init_irq(void)
set_irq_flags(i, IRQF_VALID);
}
/* IRQ_EXT2: level sensitive + active low */
/* IRQ_NS9XXX_EXT2: level sensitive + active low */
eic = __raw_readl(SYS_EIC(2));
REGSET(eic, SYS_EIC, PLTY, AL);
REGSET(eic, SYS_EIC, LVEDG, LEVEL);
__raw_writel(eic, SYS_EIC(2));
set_irq_chained_handler(IRQ_EXT2,
set_irq_chained_handler(IRQ_NS9XXX_EXT2,
a9m9750dev_fpga_demux_handler);
}
static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = {
{
.iobase = FPGA_UARTA_BASE,
.membase = (unsigned char*)FPGA_UARTA_BASE,
.mapbase = FPGA_UARTA_BASE,
.irq = IRQ_FPGA_UARTA,
.iotype = UPIO_MEM,
.uartclk = 18432000,
.regshift = 0,
.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
}, {
.iobase = FPGA_UARTB_BASE,
.membase = (unsigned char*)FPGA_UARTB_BASE,
.mapbase = FPGA_UARTB_BASE,
.irq = IRQ_FPGA_UARTB,
.iotype = UPIO_MEM,
.uartclk = 18432000,
.regshift = 0,
.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
}, {
.iobase = FPGA_UARTC_BASE,
.membase = (unsigned char*)FPGA_UARTC_BASE,
.mapbase = FPGA_UARTC_BASE,
.irq = IRQ_FPGA_UARTC,
.iotype = UPIO_MEM,
.uartclk = 18432000,
.regshift = 0,
.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
}, {
.iobase = FPGA_UARTD_BASE,
.membase = (unsigned char*)FPGA_UARTD_BASE,
.mapbase = FPGA_UARTD_BASE,
.irq = IRQ_FPGA_UARTD,
.iotype = UPIO_MEM,
.uartclk = 18432000,
.regshift = 0,
.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
}, {
/* end marker */
},
};
static struct platform_device board_a9m9750dev_serial_device = {
.name = "serial8250",
.dev = {
.platform_data = board_a9m9750dev_serial8250_port,
},
};
static struct platform_device *board_a9m9750dev_devices[] __initdata = {
&board_a9m9750dev_serial_device,
};
void __init board_a9m9750dev_init_machine(void)
{
u32 reg;
@ -210,7 +156,4 @@ void __init board_a9m9750dev_init_machine(void)
__raw_writel(0x2, MEM_SMOED(0));
__raw_writel(0x6, MEM_SMRD(0));
__raw_writel(0x6, MEM_SMWD(0));
platform_add_devices(board_a9m9750dev_devices,
ARRAY_SIZE(board_a9m9750dev_devices));
}

215
arch/arm/mach-ns9xxx/clock.c Normal file
View File

@ -0,0 +1,215 @@
/*
* arch/arm/mach-ns9xxx/clock.c
*
* Copyright (C) 2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <asm/semaphore.h>
#include "clock.h"
static LIST_HEAD(clocks);
static DEFINE_SPINLOCK(clk_lock);
struct clk *clk_get(struct device *dev, const char *id)
{
struct clk *p, *ret = NULL, *retgen = NULL;
unsigned long flags;
int idno;
if (dev == NULL || dev->bus != &platform_bus_type)
idno = -1;
else
idno = to_platform_device(dev)->id;
spin_lock_irqsave(&clk_lock, flags);
list_for_each_entry(p, &clocks, node) {
if (strcmp(id, p->name) == 0) {
if (p->id == idno) {
if (!try_module_get(p->owner))
continue;
ret = p;
break;
} else if (p->id == -1)
/* remember match with id == -1 in case there is
* no clock for idno */
retgen = p;
}
}
if (!ret && retgen && try_module_get(retgen->owner))
ret = retgen;
if (ret)
++ret->refcount;
spin_unlock_irqrestore(&clk_lock, flags);
return ret ? ret : ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
module_put(clk->owner);
--clk->refcount;
}
EXPORT_SYMBOL(clk_put);
static int clk_enable_unlocked(struct clk *clk)
{
int ret = 0;
if (clk->parent) {
ret = clk_enable_unlocked(clk->parent);
if (ret)
return ret;
}
if (clk->usage++ == 0 && clk->endisable)
ret = clk->endisable(clk, 1);
return ret;
}
int clk_enable(struct clk *clk)
{
int ret;
unsigned long flags;
spin_lock_irqsave(&clk_lock, flags);
ret = clk_enable_unlocked(clk);
spin_unlock_irqrestore(&clk_lock, flags);
return ret;
}
EXPORT_SYMBOL(clk_enable);
static void clk_disable_unlocked(struct clk *clk)
{
if (--clk->usage == 0 && clk->endisable)
clk->endisable(clk, 0);
if (clk->parent)
clk_disable_unlocked(clk->parent);
}
void clk_disable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clk_lock, flags);
clk_disable_unlocked(clk);
spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (clk->get_rate)
return clk->get_rate(clk);
if (clk->rate)
return clk->rate;
if (clk->parent)
return clk_get_rate(clk->parent);
return 0;
}
EXPORT_SYMBOL(clk_get_rate);
int clk_register(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clk_lock, flags);
list_add(&clk->node, &clocks);
if (clk->parent)
++clk->parent->refcount;
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
int clk_unregister(struct clk *clk)
{
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&clk_lock, flags);
if (clk->usage || clk->refcount)
ret = -EBUSY;
else
list_del(&clk->node);
if (clk->parent)
--clk->parent->refcount;
spin_unlock_irqrestore(&clk_lock, flags);
return ret;
}
#if defined CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
static int clk_debugfs_show(struct seq_file *s, void *null)
{
unsigned long flags;
struct clk *p;
spin_lock_irqsave(&clk_lock, flags);
list_for_each_entry(p, &clocks, node)
seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n",
p->name, p->id, p->usage, p->refcount,
p->usage ? clk_get_rate(p) : 0);
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
static int clk_debugfs_open(struct inode *inode, struct file *file)
{
return single_open(file, clk_debugfs_show, NULL);
}
static struct file_operations clk_debugfs_operations = {
.open = clk_debugfs_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int __init clk_debugfs_init(void)
{
struct dentry *dentry;
dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL,
&clk_debugfs_operations);
return IS_ERR(dentry) ? PTR_ERR(dentry) : 0;
}
subsys_initcall(clk_debugfs_init);
#endif /* if defined CONFIG_DEBUG_FS */

35
arch/arm/mach-ns9xxx/clock.h Normal file
View File

@ -0,0 +1,35 @@
/*
* arch/arm/mach-ns9xxx/clock.h
*
* Copyright (C) 2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#ifndef __NS9XXX_CLOCK_H
#define __NS9XXX_CLOCK_H
#include <linux/list.h>
struct clk {
struct module *owner;
const char *name;
int id;
struct clk *parent;
unsigned long rate;
int (*endisable)(struct clk *, int enable);
unsigned long (*get_rate)(struct clk *);
struct list_head node;
unsigned long refcount;
unsigned long usage;
};
int clk_register(struct clk *clk);
int clk_unregister(struct clk *clk);
#endif /* ifndef __NS9XXX_CLOCK_H */

27
arch/arm/mach-ns9xxx/generic.c
View File

@ -1,7 +1,7 @@
/*
* arch/arm/mach-ns9xxx/generic.c
*
* Copyright (C) 2006 by Digi International Inc.
* Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
@ -11,34 +11,9 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/memory.h>
#include <asm/page.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/arch-ns9xxx/regs-sys.h>
#include <asm/arch-ns9xxx/regs-mem.h>
#include <asm/arch-ns9xxx/board.h>
#include "generic.h"
static struct map_desc standard_io_desc[] __initdata = {
{ /* BBus */
.virtual = io_p2v(0x90000000),
.pfn = __phys_to_pfn(0x90000000),
.length = 0x00700000,
.type = MT_DEVICE,
}, { /* AHB */
.virtual = io_p2v(0xa0100000),
.pfn = __phys_to_pfn(0xa0100000),
.length = 0x00900000,
.type = MT_DEVICE,
},
};
void __init ns9xxx_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
}
void __init ns9xxx_init_machine(void)
{
}

5
arch/arm/mach-ns9xxx/generic.h
View File

@ -1,7 +1,7 @@
/*
* arch/arm/mach-ns9xxx/generic.h
*
* Copyright (C) 2006 by Digi International Inc.
* Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
@ -13,7 +13,4 @@
#include <linux/init.h>
void __init ns9xxx_init_irq(void);
void __init ns9xxx_map_io(void);
void __init ns9xxx_init_machine(void);
extern struct sys_timer ns9xxx_timer;

118
arch/arm/mach-ns9xxx/gpio-ns9360.c Normal file
View File

@ -0,0 +1,118 @@
/*
* arch/arm/mach-ns9xxx/gpio-ns9360.c
*
* Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#include <linux/bug.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/arch-ns9xxx/regs-bbu.h>
#include <asm/arch-ns9xxx/processor-ns9360.h>
#include "gpio-ns9360.h"
static inline int ns9360_valid_gpio(unsigned gpio)
{
return gpio <= 72;
}
static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio)
{
if (gpio < 56)
return BBU_GCONFb1(gpio / 8);
else
/*
* this could be optimised away on
* ns9750 only builds, but it isn't ...
*/
return BBU_GCONFb2((gpio - 56) / 8);
}
static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio)
{
if (gpio < 32)
return BBU_GCTRL1;
else if (gpio < 64)
return BBU_GCTRL2;
else
/* this could be optimised away on ns9750 only builds */
return BBU_GCTRL3;
}
static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio)
{
if (gpio < 32)
return BBU_GSTAT1;
else if (gpio < 64)
return BBU_GSTAT2;
else
/* this could be optimised away on ns9750 only builds */
return BBU_GSTAT3;
}
/*
* each gpio can serve for 4 different purposes [0..3]. These are called
* "functions" and passed in the parameter func. Functions 0-2 are always some
* special things, function 3 is GPIO. If func == 3 dir specifies input or
* output, and with inv you can enable an inverter (independent of func).
*/
int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func)
{
void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio);
u32 confval;
confval = __raw_readl(conf);
REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
__raw_writel(confval, conf);
return 0;
}
int ns9360_gpio_configure(unsigned gpio, int inv, int func)
{
if (likely(ns9360_valid_gpio(gpio))) {
if (func == 3) {
printk(KERN_WARNING "use gpio_direction_input "
"or gpio_direction_output\n");
return -EINVAL;
} else
return __ns9360_gpio_configure(gpio, 0, inv, func);
} else
return -EINVAL;
}
EXPORT_SYMBOL(ns9360_gpio_configure);
int ns9360_gpio_get_value(unsigned gpio)
{
void __iomem *stat = ns9360_gpio_get_gstataddr(gpio);
int ret;
ret = 1 & (__raw_readl(stat) >> (gpio & 31));
return ret;
}
void ns9360_gpio_set_value(unsigned gpio, int value)
{
void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio);
u32 ctrlval;
ctrlval = __raw_readl(ctrl);
if (value)
ctrlval |= 1 << (gpio & 31);
else
ctrlval &= ~(1 << (gpio & 31));
__raw_writel(ctrlval, ctrl);
}

13
arch/arm/mach-ns9xxx/gpio-ns9360.h Normal file
View File

@ -0,0 +1,13 @@
/*
* arch/arm/mach-ns9xxx/gpio-ns9360.h
*
* Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func);
int ns9360_gpio_get_value(unsigned gpio);
void ns9360_gpio_set_value(unsigned gpio, int value);

145
arch/arm/mach-ns9xxx/gpio.c
View File

@ -1,7 +1,7 @@
/*
* arch/arm/mach-ns9xxx/gpio.c
*
* Copyright (C) 2006 by Digi International Inc.
* Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
@ -15,12 +15,13 @@
#include <asm/arch-ns9xxx/gpio.h>
#include <asm/arch-ns9xxx/processor.h>
#include <asm/arch-ns9xxx/regs-bbu.h>
#include <asm/io.h>
#include <asm/arch-ns9xxx/processor-ns9360.h>
#include <asm/bug.h>
#include <asm/types.h>
#include <asm/bitops.h>
#include "gpio-ns9360.h"
#if defined(CONFIG_PROCESSOR_NS9360)
#define GPIO_MAX 72
#elif defined(CONFIG_PROCESSOR_NS9750)
@ -45,41 +46,10 @@ static inline int ns9xxx_valid_gpio(unsigned gpio)
return gpio <= 49;
else
#endif
{
BUG();
}
static inline void __iomem *ns9xxx_gpio_get_gconfaddr(unsigned gpio)
{
if (gpio < 56)
return BBU_GCONFb1(gpio / 8);
else
/*
* this could be optimised away on
* ns9750 only builds, but it isn't ...
*/
return BBU_GCONFb2((gpio - 56) / 8);
}
static inline void __iomem *ns9xxx_gpio_get_gctrladdr(unsigned gpio)
{
if (gpio < 32)
return BBU_GCTRL1;
else if (gpio < 64)
return BBU_GCTRL2;
else
/* this could be optimised away on ns9750 only builds */
return BBU_GCTRL3;
}
static inline void __iomem *ns9xxx_gpio_get_gstataddr(unsigned gpio)
{
if (gpio < 32)
return BBU_GSTAT1;
else if (gpio < 64)
return BBU_GSTAT2;
else
/* this could be optimised away on ns9750 only builds */
return BBU_GSTAT3;
return 0;
}
}
int gpio_request(unsigned gpio, const char *label)
@ -98,49 +68,24 @@ void gpio_free(unsigned gpio)
}
EXPORT_SYMBOL(gpio_free);
/*
* each gpio can serve for 4 different purposes [0..3]. These are called
* "functions" and passed in the parameter func. Functions 0-2 are always some
* special things, function 3 is GPIO. If func == 3 dir specifies input or
* output, and with inv you can enable an inverter (independent of func).
*/
static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func)
{
void __iomem *conf = ns9xxx_gpio_get_gconfaddr(gpio);
u32 confval;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
confval = __raw_readl(conf);
REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
__raw_writel(confval, conf);
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
}
int ns9xxx_gpio_configure(unsigned gpio, int inv, int func)
{
if (likely(ns9xxx_valid_gpio(gpio))) {
if (func == 3) {
printk(KERN_WARNING "use gpio_direction_input "
"or gpio_direction_output\n");
return -EINVAL;
} else
return __ns9xxx_gpio_configure(gpio, 0, inv, func);
} else
return -EINVAL;
}
EXPORT_SYMBOL(ns9xxx_gpio_configure);
int gpio_direction_input(unsigned gpio)
{
if (likely(ns9xxx_valid_gpio(gpio))) {
return __ns9xxx_gpio_configure(gpio, 0, 0, 3);
int ret = -EINVAL;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
#if defined(CONFIG_PROCESSOR_NS9360)
if (processor_is_ns9360())
ret = __ns9360_gpio_configure(gpio, 0, 0, 3);
else
#endif
BUG();
spin_unlock_irqrestore(&gpio_lock, flags);
return ret;
} else
return -EINVAL;
}
@ -149,9 +94,22 @@ EXPORT_SYMBOL(gpio_direction_input);
int gpio_direction_output(unsigned gpio, int value)
{
if (likely(ns9xxx_valid_gpio(gpio))) {
int ret = -EINVAL;
unsigned long flags;
gpio_set_value(gpio, value);
return __ns9xxx_gpio_configure(gpio, 1, 0, 3);
spin_lock_irqsave(&gpio_lock, flags);
#if defined(CONFIG_PROCESSOR_NS9360)
if (processor_is_ns9360())
ret = __ns9360_gpio_configure(gpio, 1, 0, 3);
else
#endif
BUG();
spin_unlock_irqrestore(&gpio_lock, flags);
return ret;
} else
return -EINVAL;
}
@ -159,31 +117,28 @@ EXPORT_SYMBOL(gpio_direction_output);
int gpio_get_value(unsigned gpio)
{
void __iomem *stat = ns9xxx_gpio_get_gstataddr(gpio);
int ret;
ret = 1 & (__raw_readl(stat) >> (gpio & 31));
return ret;
#if defined(CONFIG_PROCESSOR_NS9360)
if (processor_is_ns9360())
return ns9360_gpio_get_value(gpio);
else
#endif
{
BUG();
return -EINVAL;
}
}
EXPORT_SYMBOL(gpio_get_value);
void gpio_set_value(unsigned gpio, int value)
{
void __iomem *ctrl = ns9xxx_gpio_get_gctrladdr(gpio);
u32 ctrlval;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
ctrlval = __raw_readl(ctrl);
if (value)
ctrlval |= 1 << (gpio & 31);
#if defined(CONFIG_PROCESSOR_NS9360)
if (processor_is_ns9360())
ns9360_gpio_set_value(gpio, value);
else
ctrlval &= ~(1 << (gpio & 31));
__raw_writel(ctrlval, ctrl);
#endif
BUG();
spin_unlock_irqrestore(&gpio_lock, flags);
}

74
arch/arm/mach-ns9xxx/irq.c
View File

@ -9,21 +9,27 @@
* the Free Software Foundation.
*/
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <asm/arch-ns9xxx/regs-sys.h>
#include <asm/arch-ns9xxx/regs-sys-common.h>
#include <asm/arch-ns9xxx/irqs.h>
#include <asm/arch-ns9xxx/board.h>
#include "generic.h"
/* simple interrupt prio table: prio(x) < prio(y) <=> x < y */
#define irq2prio(i) (i)
#define prio2irq(p) (p)
static void ns9xxx_mask_irq(unsigned int irq)
{
/* XXX: better use cpp symbols */
u32 ic = __raw_readl(SYS_IC(irq / 4));
ic &= ~(1 << (7 + 8 * (3 - (irq & 3))));
__raw_writel(ic, SYS_IC(irq / 4));
int prio = irq2prio(irq);
u32 ic = __raw_readl(SYS_IC(prio / 4));
ic &= ~(1 << (7 + 8 * (3 - (prio & 3))));
__raw_writel(ic, SYS_IC(prio / 4));
}
static void ns9xxx_ack_irq(unsigned int irq)
@ -40,9 +46,10 @@ static void ns9xxx_maskack_irq(unsigned int irq)
static void ns9xxx_unmask_irq(unsigned int irq)
{
/* XXX: better use cpp symbols */
u32 ic = __raw_readl(SYS_IC(irq / 4));
ic |= 1 << (7 + 8 * (3 - (irq & 3)));
__raw_writel(ic, SYS_IC(irq / 4));
int prio = irq2prio(irq);
u32 ic = __raw_readl(SYS_IC(prio / 4));
ic |= 1 << (7 + 8 * (3 - (prio & 3)));
__raw_writel(ic, SYS_IC(prio / 4));
}
static struct irq_chip ns9xxx_chip = {
@ -52,24 +59,61 @@ static struct irq_chip ns9xxx_chip = {
.unmask = ns9xxx_unmask_irq,
};
#if 0
#define handle_irq handle_level_irq
#else
void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
{
unsigned int cpu = smp_processor_id();
struct irqaction *action;
irqreturn_t action_ret;
spin_lock(&desc->lock);
if (unlikely(desc->status & IRQ_INPROGRESS))
goto out_unlock;
desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
kstat_cpu(cpu).irqs[irq]++;
action = desc->action;
if (unlikely(!action || (desc->status & IRQ_DISABLED)))
goto out_unlock;
desc->status |= IRQ_INPROGRESS;
spin_unlock(&desc->lock);
action_ret = handle_IRQ_event(irq, action);
spin_lock(&desc->lock);
desc->status &= ~IRQ_INPROGRESS;
if (!(desc->status & IRQ_DISABLED) && desc->chip->ack)
desc->chip->ack(irq);
out_unlock:
spin_unlock(&desc->lock);
}
#define handle_irq handle_prio_irq
#endif
void __init ns9xxx_init_irq(void)
{
int i;
/* disable all IRQs */
for (i = 0; i < 8; ++i)
__raw_writel((4 * i) << 24 | (4 * i + 1) << 16 |
(4 * i + 2) << 8 | (4 * i + 3), SYS_IC(i));
__raw_writel(prio2irq(4 * i) << 24 |
prio2irq(4 * i + 1) << 16 |
prio2irq(4 * i + 2) << 8 |
prio2irq(4 * i + 3),
SYS_IC(i));
/* simple interrupt prio table:
* prio(x) < prio(y) <=> x < y
*/
for (i = 0; i < 32; ++i)
__raw_writel(i, SYS_IVA(i));
__raw_writel(prio2irq(i), SYS_IVA(i));
for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) {
for (i = 0; i <= 31; ++i) {
set_irq_chip(i, &ns9xxx_chip);
set_irq_handler(i, handle_level_irq);
set_irq_handler(i, handle_irq);
set_irq_flags(i, IRQF_VALID);
}
}

8
arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
View File

@ -1,7 +1,7 @@
/*
* arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
*
* Copyright (C) 2006 by Digi International Inc.
* Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
@ -11,12 +11,14 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/arch-ns9xxx/processor-ns9360.h>
#include "board-a9m9750dev.h"
#include "generic.h"
static void __init mach_cc9p9360dev_map_io(void)
{
ns9xxx_map_io();
ns9360_map_io();
board_a9m9750dev_map_io();
}
@ -36,6 +38,6 @@ MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard")
.map_io = mach_cc9p9360dev_map_io,
.init_irq = mach_cc9p9360dev_init_irq,
.init_machine = mach_cc9p9360dev_init_machine,
.timer = &ns9xxx_timer,
.timer = &ns9360_timer,
.boot_params = 0x100,
MACHINE_END

8
arch/arm/mach-ns9xxx/mach-cc9p9360js.c
View File

@ -1,7 +1,7 @@
/*
* arch/arm/mach-ns9xxx/mach-cc9p9360js.c
*
* Copyright (C) 2006 by Digi International Inc.
* Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
@ -11,6 +11,8 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/arch-ns9xxx/processor-ns9360.h>
#include "board-jscc9p9360.h"
#include "generic.h"
@ -21,9 +23,9 @@ static void __init mach_cc9p9360js_init_machine(void)
}
MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
.map_io = ns9xxx_map_io,
.map_io = ns9360_map_io,
.init_irq = ns9xxx_init_irq,
.init_machine = mach_cc9p9360js_init_machine,
.timer = &ns9xxx_timer,
.timer = &ns9360_timer,
.boot_params = 0x100,
MACHINE_END

69
arch/arm/mach-ns9xxx/plat-serial8250.c Normal file
View File

@ -0,0 +1,69 @@
/*
* arch/arm/mach-ns9xxx/plat-serial8250.c
*
* Copyright (C) 2008 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
#include <asm/arch-ns9xxx/board.h>
#define DRIVER_NAME "serial8250"
static int __init ns9xxx_plat_serial8250_init(void)
{
struct plat_serial8250_port *pdata;
struct platform_device *pdev;
int ret = -ENOMEM;
int i;
if (!board_is_a9m9750dev())
return -ENODEV;
pdev = platform_device_alloc(DRIVER_NAME, 0);
if (!pdev)
goto err;
pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL);
if (!pdata)
goto err;
pdev->dev.platform_data = pdata;
pdata[0].iobase = FPGA_UARTA_BASE;
pdata[1].iobase = FPGA_UARTB_BASE;
pdata[2].iobase = FPGA_UARTC_BASE;
pdata[3].iobase = FPGA_UARTD_BASE;
for (i = 0; i < 4; ++i) {
pdata[i].membase = (void __iomem *)pdata[i].iobase;
pdata[i].mapbase = pdata[i].iobase;
pdata[i].iotype = UPIO_MEM;
pdata[i].uartclk = 18432000;
pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
}
pdata[0].irq = IRQ_FPGA_UARTA;
pdata[1].irq = IRQ_FPGA_UARTB;
pdata[2].irq = IRQ_FPGA_UARTC;
pdata[3].irq = IRQ_FPGA_UARTD;
ret = platform_device_add(pdev);
if (ret) {
err:
platform_device_put(pdev);
printk(KERN_WARNING "Could not add %s (errno=%d)\n",
DRIVER_NAME, ret);
}
return 0;
}
arch_initcall(ns9xxx_plat_serial8250_init);

54
arch/arm/mach-ns9xxx/processor-ns9360.c Normal file
View File

@ -0,0 +1,54 @@
/*
* arch/arm/mach-ns9xxx/processor-ns9360.c
*
* Copyright (C) 2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/arch-ns9xxx/processor-ns9360.h>
#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
void ns9360_reset(char mode)
{
u32 reg;
reg = __raw_readl(SYS_PLL) >> 16;
REGSET(reg, SYS_PLL, SWC, YES);
__raw_writel(reg, SYS_PLL);
}
#define CRYSTAL 29491200 /* Hz */
unsigned long ns9360_systemclock(void)
{
u32 pll = __raw_readl(SYS_PLL);
return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
>> REGGETIM(pll, SYS_PLL, FS);
}
static struct map_desc ns9360_io_desc[] __initdata = {
{ /* BBus */
.virtual = io_p2v(0x90000000),
.pfn = __phys_to_pfn(0x90000000),
.length = 0x00700000,
.type = MT_DEVICE,
}, { /* AHB */
.virtual = io_p2v(0xa0100000),
.pfn = __phys_to_pfn(0xa0100000),
.length = 0x00900000,
.type = MT_DEVICE,
},
};
void __init ns9360_map_io(void)
{
iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc));
}

75
arch/arm/mach-ns9xxx/time.c → arch/arm/mach-ns9xxx/time-ns9360.c
View File

@ -1,7 +1,7 @@
/*
* arch/arm/mach-ns9xxx/time.c
* arch/arm/mach-ns9xxx/time-ns9360.c
*
* Copyright (C) 2006 by Digi International Inc.
* Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
@ -15,8 +15,8 @@
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <asm/arch-ns9xxx/regs-sys.h>
#include <asm/arch-ns9xxx/clock.h>
#include <asm/arch-ns9xxx/processor-ns9360.h>
#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
#include <asm/arch-ns9xxx/irqs.h>
#include <asm/arch/system.h>
#include "generic.h"
@ -25,26 +25,26 @@
#define TIMER_CLOCKEVENT 1
static u32 latch;
static cycle_t ns9xxx_clocksource_read(void)
static cycle_t ns9360_clocksource_read(void)
{
return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE));
}
static struct clocksource ns9xxx_clocksource = {
.name = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE),
static struct clocksource ns9360_clocksource = {
.name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE),
.rating = 300,
.read = ns9xxx_clocksource_read,
.read = ns9360_clocksource_read,
.mask = CLOCKSOURCE_MASK(32),
.shift = 20,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
static void ns9360_clockevent_setmode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
switch(mode) {
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
__raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT));
REGSET(tc, SYS_TCx, REN, EN);
@ -69,7 +69,7 @@ static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
}
static int ns9xxx_clockevent_setnextevent(unsigned long evt,
static int ns9360_clockevent_setnextevent(unsigned long evt,
struct clock_event_device *clk)
{
u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
@ -88,20 +88,20 @@ static int ns9xxx_clockevent_setnextevent(unsigned long evt,
return 0;
}
static struct clock_event_device ns9xxx_clockevent_device = {
.name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
static struct clock_event_device ns9360_clockevent_device = {
.name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
.shift = 20,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = ns9xxx_clockevent_setmode,
.set_next_event = ns9xxx_clockevent_setnextevent,
.set_mode = ns9360_clockevent_setmode,
.set_next_event = ns9360_clockevent_setnextevent,
};
static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id)
static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id)
{
int timerno = irq - IRQ_TIMER0;
int timerno = irq - IRQ_NS9360_TIMER0;
u32 tc;
struct clock_event_device *evt = &ns9xxx_clockevent_device;
struct clock_event_device *evt = &ns9360_clockevent_device;
/* clear irq */
tc = __raw_readl(SYS_TC(timerno));
@ -119,13 +119,13 @@ static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id)
return IRQ_HANDLED;
}
static struct irqaction ns9xxx_clockevent_action = {
.name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
static struct irqaction ns9360_clockevent_action = {
.name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = ns9xxx_clockevent_handler,
.handler = ns9360_clockevent_handler,
};
static void __init ns9xxx_timer_init(void)
static void __init ns9360_timer_init(void)
{
int tc;
@ -148,12 +148,12 @@ static void __init ns9xxx_timer_init(void)
__raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(),
ns9xxx_clocksource.shift);
ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(),
ns9360_clocksource.shift);
clocksource_register(&ns9xxx_clocksource);
clocksource_register(&ns9360_clocksource);
latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0);
latch = SH_DIV(ns9360_cpuclock(), HZ, 0);
tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
REGSET(tc, SYS_TCx, TEN, DIS);
@ -166,19 +166,20 @@ static void __init ns9xxx_timer_init(void)
REGSET(tc, SYS_TCx, REN, EN);
__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(),
NSEC_PER_SEC, ns9xxx_clockevent_device.shift);
ns9xxx_clockevent_device.max_delta_ns =
clockevent_delta2ns(-1, &ns9xxx_clockevent_device);
ns9xxx_clockevent_device.min_delta_ns =
clockevent_delta2ns(1, &ns9xxx_clockevent_device);
ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(),
NSEC_PER_SEC, ns9360_clockevent_device.shift);
ns9360_clockevent_device.max_delta_ns =
clockevent_delta2ns(-1, &ns9360_clockevent_device);
ns9360_clockevent_device.min_delta_ns =
clockevent_delta2ns(1, &ns9360_clockevent_device);
ns9xxx_clockevent_device.cpumask = cpumask_of_cpu(0);
clockevents_register_device(&ns9xxx_clockevent_device);
ns9360_clockevent_device.cpumask = cpumask_of_cpu(0);
clockevents_register_device(&ns9360_clockevent_device);
setup_irq(IRQ_TIMER0 + TIMER_CLOCKEVENT, &ns9xxx_clockevent_action);
setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT,
&ns9360_clockevent_action);
}
struct sys_timer ns9xxx_timer = {
.init = ns9xxx_timer_init,
struct sys_timer ns9360_timer = {
.init = ns9360_timer_init,
};

490
arch/arm/mach-orion/addr-map.c
View File

@ -1,490 +0,0 @@
/*
* arch/arm/mach-orion/addr-map.c
*
* Address map functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include "common.h"
/*
* The Orion has fully programable address map. There's a separate address
* map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
* Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
* address decode windows that allow it to access any of the Orion resources.
*
* CPU address decoding --
* Linux assumes that it is the boot loader that already setup the access to
* DDR and internal registers.
* Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
* Setup access to various devices located on the device bus interface (e.g.
* flashes, RTC, etc) should be issued by machine-setup.c according to
* specific board population (by using orion_setup_cpu_win()).
*
* Non-CPU Masters address decoding --
* Unlike the CPU, we setup the access from Orion's master interfaces to DDR
* banks only (the typical use case).
* Setup access for each master to DDR is issued by common.c.
*
* Note: although orion_setbits() and orion_clrbits() are not atomic
* no locking is necessary here since code in this file is only called
* at boot time when there is no concurrency issues.
*/
/*
* Generic Address Decode Windows bit settings
*/
#define TARGET_DDR 0
#define TARGET_PCI 3
#define TARGET_PCIE 4
#define TARGET_DEV_BUS 1
#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
((n) == 1) ? 0xd : \
((n) == 2) ? 0xb : \
((n) == 3) ? 0x7 : 0xf)
#define ATTR_PCIE_MEM 0x59
#define ATTR_PCIE_IO 0x51
#define ATTR_PCI_MEM 0x59
#define ATTR_PCI_IO 0x51
#define ATTR_DEV_CS0 0x1e
#define ATTR_DEV_CS1 0x1d
#define ATTR_DEV_CS2 0x1b
#define ATTR_DEV_BOOT 0xf
#define WIN_EN 1
/*
* Helpers to get DDR banks info
*/
#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8))
#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8))
#define DDR_MAX_CS 4
#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
#define DDR_BANK_EN 1
/*
* CPU Address Decode Windows registers
*/
#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4))
#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4))
#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4))
#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4))
#define CPU_MAX_WIN 8
/*
* Use this CPU address decode windows allocation
*/
#define CPU_WIN_PCIE_IO 0
#define CPU_WIN_PCI_IO 1
#define CPU_WIN_PCIE_MEM 2
#define CPU_WIN_PCI_MEM 3
#define CPU_WIN_DEV_BOOT 4
#define CPU_WIN_DEV_CS0 5
#define CPU_WIN_DEV_CS1 6
#define CPU_WIN_DEV_CS2 7
/*
* PCIE Address Decode Windows registers
*/
#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8))
#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8))
#define PCIE_WIN_CTRL(n) (((n) < 5) ? \
ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
ORION_PCIE_REG(0x1880))
#define PCIE_WIN_BASE(n) (((n) < 5) ? \
ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
ORION_PCIE_REG(0x1884))
#define PCIE_WIN_REMAP(n) (((n) < 5) ? \
ORION_PCIE_REG(0x182c + ((n) << 4)) : \
ORION_PCIE_REG(0x188c))
#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0)
#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0)
#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4)
#define PCIE_MAX_BARS 3
#define PCIE_MAX_WINS 6
/*
* Use PCIE BAR '1' for all DDR banks
*/
#define PCIE_DRAM_BAR 1
/*
* PCI Address Decode Windows registers
*/
#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \
((n) == 1) ? ORION_PCI_REG(0xd08) : \
((n) == 2) ? ORION_PCI_REG(0xc0c) : \
((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
((n) == 1) ? ORION_PCI_REG(0xd48) : \
((n) == 2) ? ORION_PCI_REG(0xc4c) : \
((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c)
#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4))
#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4))
#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4))
#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c)
/*
* PCI configuration heleprs for BAR settings
*/
#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
/*
* Gigabit Ethernet Address Decode Windows registers
*/
#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8))
#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8))
#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4))
#define ETH_WIN_EN ORION_ETH_REG(0x290)
#define ETH_WIN_PROT ORION_ETH_REG(0x294)
#define ETH_MAX_WIN 6
#define ETH_MAX_REMAP_WIN 4
/*
* USB Address Decode Windows registers
*/
#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
: ORION_USB1_REG(0x320 + ((w) << 4)))
#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
: ORION_USB1_REG(0x324 + ((w) << 4)))
#define USB_MAX_WIN 4
/*
* SATA Address Decode Windows registers
*/
#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10))
#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10))
#define SATA_MAX_WIN 4
static int __init orion_cpu_win_can_remap(u32 win)
{
u32 dev, rev;
orion_pcie_id(&dev, &rev);
if ((dev == MV88F5281_DEV_ID && win < 4)
|| (dev == MV88F5182_DEV_ID && win < 2)
|| (dev == MV88F5181_DEV_ID && win < 2))
return 1;
return 0;
}
void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
{
u32 win, attr, ctrl;
switch (target) {
case ORION_PCIE_IO:
target = TARGET_PCIE;
attr = ATTR_PCIE_IO;
win = CPU_WIN_PCIE_IO;
break;
case ORION_PCI_IO:
target = TARGET_PCI;
attr = ATTR_PCI_IO;
win = CPU_WIN_PCI_IO;
break;
case ORION_PCIE_MEM:
target = TARGET_PCIE;
attr = ATTR_PCIE_MEM;
win = CPU_WIN_PCIE_MEM;
break;
case ORION_PCI_MEM:
target = TARGET_PCI;
attr = ATTR_PCI_MEM;
win = CPU_WIN_PCI_MEM;
break;
case ORION_DEV_BOOT:
target = TARGET_DEV_BUS;
attr = ATTR_DEV_BOOT;
win = CPU_WIN_DEV_BOOT;
break;
case ORION_DEV0:
target = TARGET_DEV_BUS;
attr = ATTR_DEV_CS0;
win = CPU_WIN_DEV_CS0;
break;
case ORION_DEV1:
target = TARGET_DEV_BUS;
attr = ATTR_DEV_CS1;
win = CPU_WIN_DEV_CS1;
break;
case ORION_DEV2:
target = TARGET_DEV_BUS;
attr = ATTR_DEV_CS2;
win = CPU_WIN_DEV_CS2;
break;
case ORION_DDR:
case ORION_REGS:
/*
* Must be mapped by bootloader.
*/
default:
target = attr = win = -1;
BUG();
}
base &= 0xffff0000;
ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
(target << 4) | WIN_EN);
orion_write(CPU_WIN_BASE(win), base);
orion_write(CPU_WIN_CTRL(win), ctrl);
if (orion_cpu_win_can_remap(win)) {
if (remap >= 0) {
orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
orion_write(CPU_WIN_REMAP_HI(win), 0);
} else {
orion_write(CPU_WIN_REMAP_LO(win), base);
orion_write(CPU_WIN_REMAP_HI(win), 0);
}
}
}
void __init orion_setup_cpu_wins(void)
{
int i;
/*
* First, disable and clear windows
*/
for (i = 0; i < CPU_MAX_WIN; i++) {
orion_write(CPU_WIN_BASE(i), 0);
orion_write(CPU_WIN_CTRL(i), 0);
if (orion_cpu_win_can_remap(i)) {
orion_write(CPU_WIN_REMAP_LO(i), 0);
orion_write(CPU_WIN_REMAP_HI(i), 0);
}
}
/*
* Setup windows for PCI+PCIe IO+MEM space.
*/
orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
ORION_PCIE_MEM_SIZE, -1);
orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
ORION_PCI_MEM_SIZE, -1);
}
/*
* Setup PCIE BARs and Address Decode Wins:
* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
* WIN[0-3] -> DRAM bank[0-3]
*/
void __init orion_setup_pcie_wins(void)
{
u32 base, size, i;
/*
* First, disable and clear BARs and windows
*/
for (i = 1; i < PCIE_MAX_BARS; i++) {
orion_write(PCIE_BAR_CTRL(i), 0);
orion_write(PCIE_BAR_LO(i), 0);
orion_write(PCIE_BAR_HI(i), 0);
}
for (i = 0; i < PCIE_MAX_WINS; i++) {
orion_write(PCIE_WIN_CTRL(i), 0);
orion_write(PCIE_WIN_BASE(i), 0);
orion_write(PCIE_WIN_REMAP(i), 0);
}
/*
* Setup windows for DDR banks. Count total DDR size on the fly.
*/
base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
size = 0;
for (i = 0; i < DDR_MAX_CS; i++) {
u32 bank_base, bank_size;
bank_size = orion_read(DDR_SIZE_CS(i));
bank_base = orion_read(DDR_BASE_CS(i));
if (bank_size & DDR_BANK_EN) {
bank_size = DDR_REG_TO_SIZE(bank_size);
bank_base = DDR_REG_TO_BASE(bank_base);
orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
orion_write(PCIE_WIN_REMAP(i), 0);
orion_write(PCIE_WIN_CTRL(i),
((bank_size-1) & 0xffff0000) |
(ATTR_DDR_CS(i) << 8) |
(TARGET_DDR << 4) |
(PCIE_DRAM_BAR << 1) | WIN_EN);
size += bank_size;
}
}
/*
* Setup BAR[1] to all DRAM banks
*/
orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
((size - 1) & 0xffff0000) | WIN_EN);
}
void __init orion_setup_pci_wins(void)
{
u32 base, size, i;
/*
* First, disable windows
*/
orion_write(PCI_BAR_ENABLE, 0xffffffff);
/*
* Setup windows for DDR banks.
*/
for (i = 0; i < DDR_MAX_CS; i++) {
base = orion_read(DDR_BASE_CS(i));
size = orion_read(DDR_SIZE_CS(i));
if (size & DDR_BANK_EN) {
u32 bus, dev, func, reg, val;
size = DDR_REG_TO_SIZE(size);
base = DDR_REG_TO_BASE(base);
bus = orion_pci_local_bus_nr();
dev = orion_pci_local_dev_nr();
func = PCI_CONF_FUNC_BAR_CS(i);
reg = PCI_CONF_REG_BAR_LO_CS(i);
orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
(base & 0xfffff000) | (val & 0xfff));
reg = PCI_CONF_REG_BAR_HI_CS(i);
orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
orion_write(PCI_BAR_SIZE_DDR_CS(i),
(size - 1) & 0xfffff000);
orion_write(PCI_BAR_REMAP_DDR_CS(i),
base & 0xfffff000);
orion_clrbits(PCI_BAR_ENABLE, (1 << i));
}
}
/*
* Disable automatic update of address remaping when writing to BARs
*/
orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
}
void __init orion_setup_usb_wins(void)
{
int i;
u32 usb_if, dev, rev;
u32 max_usb_if = 1;
orion_pcie_id(&dev, &rev);
if (dev == MV88F5182_DEV_ID)
max_usb_if = 2;
for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
/*
* First, disable and clear windows
*/
for (i = 0; i < USB_MAX_WIN; i++) {
orion_write(USB_WIN_BASE(usb_if, i), 0);
orion_write(USB_WIN_CTRL(usb_if, i), 0);
}
/*
* Setup windows for DDR banks.
*/
for (i = 0; i < DDR_MAX_CS; i++) {
u32 base, size;
size = orion_read(DDR_SIZE_CS(i));
base = orion_read(DDR_BASE_CS(i));
if (size & DDR_BANK_EN) {
base = DDR_REG_TO_BASE(base);
size = DDR_REG_TO_SIZE(size);
orion_write(USB_WIN_CTRL(usb_if, i),
((size-1) & 0xffff0000) |
(ATTR_DDR_CS(i) << 8) |
(TARGET_DDR << 4) | WIN_EN);
orion_write(USB_WIN_BASE(usb_if, i),
base & 0xffff0000);
}
}
}
}
void __init orion_setup_eth_wins(void)
{
int i;
/*
* First, disable and clear windows
*/
for (i = 0; i < ETH_MAX_WIN; i++) {
orion_write(ETH_WIN_BASE(i), 0);
orion_write(ETH_WIN_SIZE(i), 0);
orion_setbits(ETH_WIN_EN, 1 << i);
orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
if (i < ETH_MAX_REMAP_WIN)
orion_write(ETH_WIN_REMAP(i), 0);
}
/*
* Setup windows for DDR banks.
*/
for (i = 0; i < DDR_MAX_CS; i++) {
u32 base, size;
size = orion_read(DDR_SIZE_CS(i));
base = orion_read(DDR_BASE_CS(i));
if (size & DDR_BANK_EN) {
base = DDR_REG_TO_BASE(base);
size = DDR_REG_TO_SIZE(size);
orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
(ATTR_DDR_CS(i) << 8) |
TARGET_DDR);
orion_clrbits(ETH_WIN_EN, 1 << i);
orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
}
}
}
void __init orion_setup_sata_wins(void)
{
int i;
/*
* First, disable and clear windows
*/
for (i = 0; i < SATA_MAX_WIN; i++) {
orion_write(SATA_WIN_BASE(i), 0);
orion_write(SATA_WIN_CTRL(i), 0);
}
/*
* Setup windows for DDR banks.
*/
for (i = 0; i < DDR_MAX_CS; i++) {
u32 base, size;
size = orion_read(DDR_SIZE_CS(i));
base = orion_read(DDR_BASE_CS(i));
if (size & DDR_BANK_EN) {
base = DDR_REG_TO_BASE(base);
size = DDR_REG_TO_SIZE(size);
orion_write(SATA_WIN_CTRL(i),
((size-1) & 0xffff0000) |
(ATTR_DDR_CS(i) << 8) |
(TARGET_DDR << 4) | WIN_EN);
orion_write(SATA_WIN_BASE(i),
base & 0xffff0000);
}
}
}

92
arch/arm/mach-orion/common.h
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@ -1,92 +0,0 @@
#ifndef __ARCH_ORION_COMMON_H__
#define __ARCH_ORION_COMMON_H__
/*
* Basic Orion init functions used early by machine-setup.
*/
void __init orion_map_io(void);
void __init orion_init_irq(void);
void __init orion_init(void);
/*
* Enumerations and functions for Orion windows mapping. Used by Orion core
* functions to map its interfaces and by the machine-setup to map its on-
* board devices. Details in /mach-orion/addr-map.c
*/
enum orion_target {
ORION_DEV_BOOT = 0,
ORION_DEV0,
ORION_DEV1,
ORION_DEV2,
ORION_PCIE_MEM,
ORION_PCIE_IO,
ORION_PCI_MEM,
ORION_PCI_IO,
ORION_DDR,
ORION_REGS,
ORION_MAX_TARGETS
};
void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
void orion_setup_cpu_wins(void);
void orion_setup_eth_wins(void);
void orion_setup_usb_wins(void);
void orion_setup_pci_wins(void);
void orion_setup_pcie_wins(void);
void orion_setup_sata_wins(void);
/*
* Shared code used internally by other Orion core functions.
* (/mach-orion/pci.c)
*/
struct pci_sys_data;
struct pci_bus;
void orion_pcie_id(u32 *dev, u32 *rev);
u32 orion_pcie_local_bus_nr(void);
u32 orion_pci_local_bus_nr(void);
u32 orion_pci_local_dev_nr(void);
int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
/*
* Valid GPIO pins according to MPP setup, used by machine-setup.
* (/mach-orion/gpio.c).
*/
void __init orion_gpio_set_valid_pins(u32 pins);
void gpio_display(void); /* debug */
/*
* Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
*/
extern struct sys_timer orion_timer;
/*
* Pull in Orion Ethernet platform_data, used by machine-setup
*/
struct mv643xx_eth_platform_data;
void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
/*
* Orion Sata platform_data, used by machine-setup
*/
struct mv_sata_platform_data;
void __init orion_sata_init(struct mv_sata_platform_data *sata_data);
struct machine_desc;
struct meminfo;
struct tag;
extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
char **, struct meminfo *);
#endif /* __ARCH_ORION_COMMON_H__ */

557
arch/arm/mach-orion/pci.c
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@ -1,557 +0,0 @@
/*
* arch/arm/mach-orion/pci.c
*
* PCI and PCIE functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <asm/mach/pci.h>
#include "common.h"
/*****************************************************************************
* Orion has one PCIE controller and one PCI controller.
*
* Note1: The local PCIE bus number is '0'. The local PCI bus number
* follows the scanned PCIE bridged busses, if any.
*
* Note2: It is possible for PCI/PCIE agents to access many subsystem's
* space, by configuring BARs and Address Decode Windows, e.g. flashes on
* device bus, Orion registers, etc. However this code only enable the
* access to DDR banks.
****************************************************************************/
/*****************************************************************************
* PCIE controller
****************************************************************************/
#define PCIE_CTRL ORION_PCIE_REG(0x1a00)
#define PCIE_STAT ORION_PCIE_REG(0x1a04)
#define PCIE_DEV_ID ORION_PCIE_REG(0x0000)
#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004)
#define PCIE_DEV_REV ORION_PCIE_REG(0x0008)
#define PCIE_MASK ORION_PCIE_REG(0x1910)
#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8)
#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc)
/*
* PCIE_STAT bits
*/
#define PCIE_STAT_LINK_DOWN 1
#define PCIE_STAT_BUS_OFFS 8
#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS)
#define PCIE_STAT_DEV_OFFS 20
#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS)
/*
* PCIE_CONF_ADDR bits
*/
#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc))
#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
#define PCIE_CONF_ADDR_EN (1 << 31)
/*
* PCIE config cycles are done by programming the PCIE_CONF_ADDR register
* and then reading the PCIE_CONF_DATA register. Need to make sure these
* transactions are atomic.
*/
static DEFINE_SPINLOCK(orion_pcie_lock);
void orion_pcie_id(u32 *dev, u32 *rev)
{
*dev = orion_read(PCIE_DEV_ID) >> 16;
*rev = orion_read(PCIE_DEV_REV) & 0xff;
}
u32 orion_pcie_local_bus_nr(void)
{
u32 stat = orion_read(PCIE_STAT);
return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
}
static u32 orion_pcie_local_dev_nr(void)
{
u32 stat = orion_read(PCIE_STAT);
return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
}
static u32 orion_pcie_no_link(void)
{
u32 stat = orion_read(PCIE_STAT);
return(stat & PCIE_STAT_LINK_DOWN);
}
static void orion_pcie_set_bus_nr(int nr)
{
orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
}
static void orion_pcie_master_slave_enable(void)
{
orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
PCI_COMMAND_IO |
PCI_COMMAND_MEMORY);
}
static void orion_pcie_enable_interrupts(void)
{
/*
* Enable interrupts lines
* INTA[24] INTB[25] INTC[26] INTD[27]
*/
orion_setbits(PCIE_MASK, 0xf<<24);
}
static int orion_pcie_valid_config(u32 bus, u32 dev)
{
/*
* Don't go out when trying to access --
* 1. our own device
* 2. where there's no device connected (no link)
* 3. nonexisting devices on local bus
*/
if ((orion_pcie_local_bus_nr() == bus) &&
(orion_pcie_local_dev_nr() == dev))
return 0;
if (orion_pcie_no_link())
return 0;
if (bus == orion_pcie_local_bus_nr())
if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) ||
((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
return 0;
return 1;
}
static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
unsigned long flags;
unsigned int dev, rev, pcie_addr;
if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
spin_lock_irqsave(&orion_pcie_lock, flags);
orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
orion_pcie_id(&dev, &rev);
if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
/* extended register space */
pcie_addr = ORION_PCIE_WA_VIRT_BASE;
pcie_addr |= PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
PCIE_CONF_REG(where);
*val = orion_read(pcie_addr);
} else
*val = orion_read(PCIE_CONF_DATA);
if (size == 1)
*val = (*val >> (8*(where & 0x3))) & 0xff;
else if (size == 2)
*val = (*val >> (8*(where & 0x3))) & 0xffff;
spin_unlock_irqrestore(&orion_pcie_lock, flags);
return PCIBIOS_SUCCESSFUL;
}
static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 val)
{
unsigned long flags;
int ret;
if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
spin_lock_irqsave(&orion_pcie_lock, flags);
ret = PCIBIOS_SUCCESSFUL;
orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
if (size == 4) {
__raw_writel(val, PCIE_CONF_DATA);
} else if (size == 2) {
__raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
} else if (size == 1) {
__raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
} else {
ret = PCIBIOS_BAD_REGISTER_NUMBER;
}
spin_unlock_irqrestore(&orion_pcie_lock, flags);
return ret;
}
struct pci_ops orion_pcie_ops = {
.read = orion_pcie_rd_conf,
.write = orion_pcie_wr_conf,
};
static int orion_pcie_setup(struct pci_sys_data *sys)
{
struct resource *res;
/*
* Master + Slave enable
*/
orion_pcie_master_slave_enable();
/*
* Enable interrupts lines A-D
*/
orion_pcie_enable_interrupts();
/*
* Request resource
*/
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
if (!res)
panic("orion_pci_setup unable to alloc resources");
/*
* IORESOURCE_IO
*/
res[0].name = "PCI-EX I/O Space";
res[0].flags = IORESOURCE_IO;
res[0].start = ORION_PCIE_IO_BUS_BASE;
res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCIE IO resource failed\n");
sys->resource[0] = &res[0];
/*
* IORESOURCE_MEM
*/
res[1].name = "PCI-EX Memory Space";
res[1].flags = IORESOURCE_MEM;
res[1].start = ORION_PCIE_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCIE Memory resource failed\n");
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
sys->io_offset = 0;
return 1;
}
/*****************************************************************************
* PCI controller
****************************************************************************/
#define PCI_MODE ORION_PCI_REG(0xd00)
#define PCI_CMD ORION_PCI_REG(0xc00)
#define PCI_P2P_CONF ORION_PCI_REG(0x1d14)
#define PCI_CONF_ADDR ORION_PCI_REG(0xc78)
#define PCI_CONF_DATA ORION_PCI_REG(0xc7c)
/*
* PCI_MODE bits
*/
#define PCI_MODE_64BIT (1 << 2)
#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
/*
* PCI_CMD bits
*/
#define PCI_CMD_HOST_REORDER (1 << 29)
/*
* PCI_P2P_CONF bits
*/
#define PCI_P2P_BUS_OFFS 16
#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS 24
#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
/*
* PCI_CONF_ADDR bits
*/
#define PCI_CONF_REG(reg) ((reg) & 0xfc)
#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN (1 << 31)
/*
* Internal configuration space
*/
#define PCI_CONF_FUNC_STAT_CMD 0
#define PCI_CONF_REG_STAT_CMD 4
#define PCIX_STAT 0x64
#define PCIX_STAT_BUS_OFFS 8
#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
/*
* PCI config cycles are done by programming the PCI_CONF_ADDR register
* and then reading the PCI_CONF_DATA register. Need to make sure these
* transactions are atomic.
*/
static DEFINE_SPINLOCK(orion_pci_lock);
u32 orion_pci_local_bus_nr(void)
{
u32 conf = orion_read(PCI_P2P_CONF);
return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}
u32 orion_pci_local_dev_nr(void)
{
u32 conf = orion_read(PCI_P2P_CONF);
return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
}
int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
u32 where, u32 size, u32 *val)
{
unsigned long flags;
spin_lock_irqsave(&orion_pci_lock, flags);
orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
*val = orion_read(PCI_CONF_DATA);
if (size == 1)
*val = (*val >> (8*(where & 0x3))) & 0xff;
else if (size == 2)
*val = (*val >> (8*(where & 0x3))) & 0xffff;
spin_unlock_irqrestore(&orion_pci_lock, flags);
return PCIBIOS_SUCCESSFUL;
}
int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
u32 where, u32 size, u32 val)
{
unsigned long flags;
int ret = PCIBIOS_SUCCESSFUL;
spin_lock_irqsave(&orion_pci_lock, flags);
orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
if (size == 4) {
__raw_writel(val, PCI_CONF_DATA);
} else if (size == 2) {
__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
} else if (size == 1) {
__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
} else {
ret = PCIBIOS_BAD_REGISTER_NUMBER;
}
spin_unlock_irqrestore(&orion_pci_lock, flags);
return ret;
}
static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 *val)
{
/*
* Don't go out for local device
*/
if ((orion_pci_local_bus_nr() == bus->number) &&
(orion_pci_local_dev_nr() == PCI_SLOT(devfn))) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
PCI_FUNC(devfn), where, size, val);
}
static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
/*
* Don't go out for local device
*/
if ((orion_pci_local_bus_nr() == bus->number) &&
(orion_pci_local_dev_nr() == PCI_SLOT(devfn)))
return PCIBIOS_DEVICE_NOT_FOUND;
return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
PCI_FUNC(devfn), where, size, val);
}
struct pci_ops orion_pci_ops = {
.read = orion_pci_rd_conf,
.write = orion_pci_wr_conf,
};
static void orion_pci_set_bus_nr(int nr)
{
u32 p2p = orion_read(PCI_P2P_CONF);
if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
/*
* PCI-X mode
*/
u32 pcix_status, bus, dev;
bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
pcix_status &= ~PCIX_STAT_BUS_MASK;
pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
} else {
/*
* PCI Conventional mode
*/
p2p &= ~PCI_P2P_BUS_MASK;
p2p |= (nr << PCI_P2P_BUS_OFFS);
orion_write(PCI_P2P_CONF, p2p);
}
}
static void orion_pci_master_slave_enable(void)
{
u32 bus_nr, dev_nr, func, reg, val;
bus_nr = orion_pci_local_bus_nr();
dev_nr = orion_pci_local_dev_nr();
func = PCI_CONF_FUNC_STAT_CMD;
reg = PCI_CONF_REG_STAT_CMD;
orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val);
val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
}
static int orion_pci_setup(struct pci_sys_data *sys)
{
struct resource *res;
/*
* Master + Slave enable
*/
orion_pci_master_slave_enable();
/*
* Force ordering
*/
orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
/*
* Request resources
*/
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
if (!res)
panic("orion_pci_setup unable to alloc resources");
/*
* IORESOURCE_IO
*/
res[0].name = "PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[0].start = ORION_PCI_IO_BUS_BASE;
res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCI IO resource failed\n");
sys->resource[0] = &res[0];
/*
* IORESOURCE_MEM
*/
res[1].name = "PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
res[1].start = ORION_PCI_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCI Memory resource failed\n");
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
sys->io_offset = 0;
return 1;
}
/*****************************************************************************
* General PCIE + PCI
****************************************************************************/
int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
if (nr == 0) {
/*
* PCIE setup
*/
orion_pcie_set_bus_nr(0);
ret = orion_pcie_setup(sys);
} else if (nr == 1) {
/*
* PCI setup
*/
ret = orion_pci_setup(sys);
}
return ret;
}
struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
{
struct pci_ops *ops;
struct pci_bus *bus;
if (nr == 0) {
u32 pci_bus;
/*
* PCIE scan
*/
ops = &orion_pcie_ops;
bus = pci_scan_bus(sys->busnr, ops, sys);
/*
* Set local PCI bus number to follow PCIE bridges (if any)
*/
pci_bus = bus->number + bus->subordinate - bus->secondary + 1;
orion_pci_set_bus_nr(pci_bus);
} else if (nr == 1) {
/*
* PCI scan
*/
ops = &orion_pci_ops;
bus = pci_scan_bus(sys->busnr, ops, sys);
} else {
BUG();
bus = NULL;
}
return bus;
}

181
arch/arm/mach-orion/time.c
View File

@ -1,181 +0,0 @@
/*
* arch/arm/mach-orion/time.c
*
* Core time functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/mach/time.h>
#include <asm/arch/orion.h>
#include "common.h"
/*
* Timer0: clock_event_device, Tick.
* Timer1: clocksource, Free running.
* WatchDog: Not used.
*
* Timers are counting down.
*/
#define CLOCKEVENT 0
#define CLOCKSOURCE 1
/*
* Timers bits
*/
#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1))
#define TIMER_EN(x) (1 << ((x) * 2))
#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1))
#define BRIDGE_INT_TIMER_WD (1 << 3)
#define TIMER_WD_EN (1 << 4)
#define TIMER_WD_RELOAD_EN (1 << 5)
static cycle_t orion_clksrc_read(void)
{
return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE)));
}
static struct clocksource orion_clksrc = {
.name = "orion_clocksource",
.shift = 20,
.rating = 300,
.read = orion_clksrc_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static int
orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
{
unsigned long flags;
if (delta == 0)
return -ETIME;
local_irq_save(flags);
/*
* Clear and enable timer interrupt bit
*/
orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
/*
* Setup new timer value
*/
orion_write(TIMER_VAL(CLOCKEVENT), delta);
/*
* Disable auto reload and kickoff the timer
*/
orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT));
orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT));
local_irq_restore(flags);
return 0;
}
static void
orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
unsigned long flags;
local_irq_save(flags);
if (mode == CLOCK_EVT_MODE_PERIODIC) {
/*
* Setup latch cycles in timer and enable reload interrupt.
*/
orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH);
orion_write(TIMER_VAL(CLOCKEVENT), LATCH);
orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
TIMER_EN(CLOCKEVENT));
} else {
/*
* Disable timer and interrupt
*/
orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
TIMER_EN(CLOCKEVENT));
}
local_irq_restore(flags);
}
static struct clock_event_device orion_clkevt = {
.name = "orion_tick",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.rating = 300,
.cpumask = CPU_MASK_CPU0,
.set_next_event = orion_clkevt_next_event,
.set_mode = orion_clkevt_mode,
};
static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
{
/*
* Clear cause bit and do event
*/
orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
orion_clkevt.event_handler(&orion_clkevt);
return IRQ_HANDLED;
}
static struct irqaction orion_timer_irq = {
.name = "orion_tick",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = orion_timer_interrupt
};
static void orion_timer_init(void)
{
/*
* Setup clocksource free running timer (no interrupt on reload)
*/
orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff);
orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff);
orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE));
orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) |
TIMER_EN(CLOCKSOURCE));
/*
* Register clocksource
*/
orion_clksrc.mult =
clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift);
clocksource_register(&orion_clksrc);
/*
* Connect and enable tick handler
*/
setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq);
/*
* Register clockevent
*/
orion_clkevt.mult =
div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift);
orion_clkevt.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &orion_clkevt);
orion_clkevt.min_delta_ns =
clockevent_delta2ns(1, &orion_clkevt);
clockevents_register_device(&orion_clkevt);
}
struct sys_timer orion_timer = {
.init = orion_timer_init,
};

10
arch/arm/mach-orion/Kconfig → arch/arm/mach-orion5x/Kconfig
View File

@ -1,4 +1,4 @@
if ARCH_ORION
if ARCH_ORION5X
menu "Orion Implementations"
@ -36,6 +36,14 @@ config MACH_TS209
Say 'Y' here if you want your kernel to support the
QNAP TS-109/TS-209 platform.
config MACH_LINKSTATION_PRO
bool "Buffalo Linkstation Pro/Live"
select I2C_BOARDINFO
help
Say 'Y' here if you want your kernel to support the
Buffalo Linkstation Pro/Live platform. Both v1 and
v2 devices are supported.
endmenu
endif

3
arch/arm/mach-orion/Makefile → arch/arm/mach-orion5x/Makefile
View File

@ -1,6 +1,7 @@
obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o
obj-y += common.o addr-map.o pci.o gpio.o irq.o
obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
obj-$(CONFIG_MACH_DNS323) += dns323-setup.o
obj-$(CONFIG_MACH_TS209) += ts209-setup.o

0
arch/arm/mach-orion/Makefile.boot → arch/arm/mach-orion5x/Makefile.boot
View File

240
arch/arm/mach-orion5x/addr-map.c Normal file
View File

@ -0,0 +1,240 @@
/*
* arch/arm/mach-orion5x/addr-map.c
*
* Address map functions for Marvell Orion 5x SoCs
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include "common.h"
/*
* The Orion has fully programable address map. There's a separate address
* map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
* Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
* address decode windows that allow it to access any of the Orion resources.
*
* CPU address decoding --
* Linux assumes that it is the boot loader that already setup the access to
* DDR and internal registers.
* Setup access to PCI and PCI-E IO/MEM space is issued by this file.
* Setup access to various devices located on the device bus interface (e.g.
* flashes, RTC, etc) should be issued by machine-setup.c according to
* specific board population (by using orion5x_setup_*_win()).
*
* Non-CPU Masters address decoding --
* Unlike the CPU, we setup the access from Orion's master interfaces to DDR
* banks only (the typical use case).
* Setup access for each master to DDR is issued by common.c.
*
* Note: although orion_setbits() and orion_clrbits() are not atomic
* no locking is necessary here since code in this file is only called
* at boot time when there is no concurrency issues.
*/
/*
* Generic Address Decode Windows bit settings
*/
#define TARGET_DDR 0
#define TARGET_DEV_BUS 1
#define TARGET_PCI 3
#define TARGET_PCIE 4
#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
((n) == 1) ? 0xd : \
((n) == 2) ? 0xb : \
((n) == 3) ? 0x7 : 0xf)
#define ATTR_PCIE_MEM 0x59
#define ATTR_PCIE_IO 0x51
#define ATTR_PCIE_WA 0x79
#define ATTR_PCI_MEM 0x59
#define ATTR_PCI_IO 0x51
#define ATTR_DEV_CS0 0x1e
#define ATTR_DEV_CS1 0x1d
#define ATTR_DEV_CS2 0x1b
#define ATTR_DEV_BOOT 0xf
#define WIN_EN 1
/*
* Helpers to get DDR bank info
*/
#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8))
#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8))
#define DDR_MAX_CS 4
#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
#define DDR_BANK_EN 1
/*
* CPU Address Decode Windows registers
*/
#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
/*
* Gigabit Ethernet Address Decode Windows registers
*/
#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8))
#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8))
#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4))
#define ETH_WIN_EN ORION5X_ETH_REG(0x290)
#define ETH_WIN_PROT ORION5X_ETH_REG(0x294)
#define ETH_MAX_WIN 6
#define ETH_MAX_REMAP_WIN 4
struct mbus_dram_target_info orion5x_mbus_dram_info;
static int __init orion5x_cpu_win_can_remap(int win)
{
u32 dev, rev;
orion5x_pcie_id(&dev, &rev);
if ((dev == MV88F5281_DEV_ID && win < 4)
|| (dev == MV88F5182_DEV_ID && win < 2)
|| (dev == MV88F5181_DEV_ID && win < 2))
return 1;
return 0;
}
static void __init setup_cpu_win(int win, u32 base, u32 size,
u8 target, u8 attr, int remap)
{
orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
orion5x_write(CPU_WIN_CTRL(win),
((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
if (orion5x_cpu_win_can_remap(win)) {
if (remap < 0)
remap = base;
orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
orion5x_write(CPU_WIN_REMAP_HI(win), 0);
}
}
void __init orion5x_setup_cpu_mbus_bridge(void)
{
int i;
int cs;
/*
* First, disable and clear windows.
*/
for (i = 0; i < 8; i++) {
orion5x_write(CPU_WIN_BASE(i), 0);
orion5x_write(CPU_WIN_CTRL(i), 0);
if (orion5x_cpu_win_can_remap(i)) {
orion5x_write(CPU_WIN_REMAP_LO(i), 0);
orion5x_write(CPU_WIN_REMAP_HI(i), 0);
}
}
/*
* Setup windows for PCI+PCIe IO+MEM space.
*/
setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
TARGET_PCIE, ATTR_PCIE_MEM, -1);
setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
TARGET_PCI, ATTR_PCI_MEM, -1);
/*
* Setup MBUS dram target info.
*/
orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
for (i = 0, cs = 0; i < 4; i++) {
u32 base = readl(DDR_BASE_CS(i));
u32 size = readl(DDR_SIZE_CS(i));
/*
* Chip select enabled?
*/
if (size & 1) {
struct mbus_dram_window *w;
w = &orion5x_mbus_dram_info.cs[cs++];
w->cs_index = i;
w->mbus_attr = 0xf & ~(1 << i);
w->base = base & 0xff000000;
w->size = (size | 0x00ffffff) + 1;
}
}
orion5x_mbus_dram_info.num_cs = cs;
}
void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
{
setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
}
void __init orion5x_setup_dev0_win(u32 base, u32 size)
{
setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
}
void __init orion5x_setup_dev1_win(u32 base, u32 size)
{
setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
}
void __init orion5x_setup_dev2_win(u32 base, u32 size)
{
setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
}
void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
{
setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
}
void __init orion5x_setup_eth_wins(void)
{
int i;
/*
* First, disable and clear windows
*/
for (i = 0; i < ETH_MAX_WIN; i++) {
orion5x_write(ETH_WIN_BASE(i), 0);
orion5x_write(ETH_WIN_SIZE(i), 0);
orion5x_setbits(ETH_WIN_EN, 1 << i);
orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
if (i < ETH_MAX_REMAP_WIN)
orion5x_write(ETH_WIN_REMAP(i), 0);
}
/*
* Setup windows for DDR banks.
*/
for (i = 0; i < DDR_MAX_CS; i++) {
u32 base, size;
size = orion5x_read(DDR_SIZE_CS(i));
base = orion5x_read(DDR_BASE_CS(i));
if (size & DDR_BANK_EN) {
base = DDR_REG_TO_BASE(base);
size = DDR_REG_TO_SIZE(size);
orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
(ATTR_DDR_CS(i) << 8) |
TARGET_DDR);
orion5x_clrbits(ETH_WIN_EN, 1 << i);
orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
}
}
}

220
arch/arm/mach-orion/common.c → arch/arm/mach-orion5x/common.c
View File

@ -1,12 +1,12 @@
/*
* arch/arm/mach-orion/common.c
* arch/arm/mach-orion5x/common.c
*
* Core functions for Marvell Orion System On Chip
* Core functions for Marvell Orion 5x SoCs
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
@ -14,64 +14,71 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/arch/hardware.h>
#include <asm/arch/orion5x.h>
#include <asm/plat-orion/ehci-orion.h>
#include <asm/plat-orion/orion_nand.h>
#include <asm/plat-orion/time.h>
#include "common.h"
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
static struct map_desc orion_io_desc[] __initdata = {
static struct map_desc orion5x_io_desc[] __initdata = {
{
.virtual = ORION_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE),
.length = ORION_REGS_SIZE,
.virtual = ORION5X_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
.length = ORION5X_REGS_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCIE_IO_VIRT_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
.length = ORION_PCIE_IO_SIZE,
.virtual = ORION5X_PCIE_IO_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
.length = ORION5X_PCIE_IO_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCI_IO_VIRT_BASE,
.pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
.length = ORION_PCI_IO_SIZE,
.virtual = ORION5X_PCI_IO_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
.length = ORION5X_PCI_IO_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCIE_WA_VIRT_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
.length = ORION_PCIE_WA_SIZE,
.virtual = ORION5X_PCIE_WA_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
.length = ORION5X_PCIE_WA_SIZE,
.type = MT_DEVICE
},
};
void __init orion_map_io(void)
void __init orion5x_map_io(void)
{
iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
}
/*****************************************************************************
* UART
****************************************************************************/
static struct resource orion_uart_resources[] = {
static struct resource orion5x_uart_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_ORION_UART0,
.end = IRQ_ORION_UART0,
.start = IRQ_ORION5X_UART0,
.end = IRQ_ORION5X_UART0,
.flags = IORESOURCE_IRQ,
},
{
@ -80,96 +87,102 @@ static struct resource orion_uart_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_ORION_UART1,
.end = IRQ_ORION_UART1,
.start = IRQ_ORION5X_UART1,
.end = IRQ_ORION5X_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct plat_serial8250_port orion_uart_data[] = {
static struct plat_serial8250_port orion5x_uart_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_ORION_UART0,
.irq = IRQ_ORION5X_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = ORION_TCLK,
.uartclk = ORION5X_TCLK,
},
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_ORION_UART1,
.irq = IRQ_ORION5X_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = ORION_TCLK,
.uartclk = ORION5X_TCLK,
},
{ },
};
static struct platform_device orion_uart = {
static struct platform_device orion5x_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = orion_uart_data,
.platform_data = orion5x_uart_data,
},
.resource = orion_uart_resources,
.num_resources = ARRAY_SIZE(orion_uart_resources),
.resource = orion5x_uart_resources,
.num_resources = ARRAY_SIZE(orion5x_uart_resources),
};
/*******************************************************************************
* USB Controller - 2 interfaces
******************************************************************************/
static struct resource orion_ehci0_resources[] = {
static struct resource orion5x_ehci0_resources[] = {
{
.start = ORION_USB0_PHYS_BASE,
.end = ORION_USB0_PHYS_BASE + SZ_4K,
.start = ORION5X_USB0_PHYS_BASE,
.end = ORION5X_USB0_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_ORION_USB0_CTRL,
.end = IRQ_ORION_USB0_CTRL,
.start = IRQ_ORION5X_USB0_CTRL,
.end = IRQ_ORION5X_USB0_CTRL,
.flags = IORESOURCE_IRQ,
},
};
static struct resource orion_ehci1_resources[] = {
static struct resource orion5x_ehci1_resources[] = {
{
.start = ORION_USB1_PHYS_BASE,
.end = ORION_USB1_PHYS_BASE + SZ_4K,
.start = ORION5X_USB1_PHYS_BASE,
.end = ORION5X_USB1_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_ORION_USB1_CTRL,
.end = IRQ_ORION_USB1_CTRL,
.start = IRQ_ORION5X_USB1_CTRL,
.end = IRQ_ORION5X_USB1_CTRL,
.flags = IORESOURCE_IRQ,
},
};
static struct orion_ehci_data orion5x_ehci_data = {
.dram = &orion5x_mbus_dram_info,
};
static u64 ehci_dmamask = 0xffffffffUL;
static struct platform_device orion_ehci0 = {
static struct platform_device orion5x_ehci0 = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &orion5x_ehci_data,
},
.resource = orion_ehci0_resources,
.num_resources = ARRAY_SIZE(orion_ehci0_resources),
.resource = orion5x_ehci0_resources,
.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
};
static struct platform_device orion_ehci1 = {
static struct platform_device orion5x_ehci1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &orion5x_ehci_data,
},
.resource = orion_ehci1_resources,
.num_resources = ARRAY_SIZE(orion_ehci1_resources),
.resource = orion5x_ehci1_resources,
.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
};
/*****************************************************************************
@ -177,42 +190,42 @@ static struct platform_device orion_ehci1 = {
* (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
****************************************************************************/
static struct resource orion_eth_shared_resources[] = {
static struct resource orion5x_eth_shared_resources[] = {
{
.start = ORION_ETH_PHYS_BASE + 0x2000,
.end = ORION_ETH_PHYS_BASE + 0x3fff,
.start = ORION5X_ETH_PHYS_BASE + 0x2000,
.end = ORION5X_ETH_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device orion_eth_shared = {
static struct platform_device orion5x_eth_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = 1,
.resource = orion_eth_shared_resources,
.resource = orion5x_eth_shared_resources,
};
static struct resource orion_eth_resources[] = {
static struct resource orion5x_eth_resources[] = {
{
.name = "eth irq",
.start = IRQ_ORION_ETH_SUM,
.end = IRQ_ORION_ETH_SUM,
.start = IRQ_ORION5X_ETH_SUM,
.end = IRQ_ORION5X_ETH_SUM,
.flags = IORESOURCE_IRQ,
}
};
static struct platform_device orion_eth = {
static struct platform_device orion5x_eth = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = orion_eth_resources,
.resource = orion5x_eth_resources,
};
void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
orion_eth.dev.platform_data = eth_data;
platform_device_register(&orion_eth_shared);
platform_device_register(&orion_eth);
orion5x_eth.dev.platform_data = eth_data;
platform_device_register(&orion5x_eth_shared);
platform_device_register(&orion5x_eth);
}
/*****************************************************************************
@ -220,13 +233,13 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
* (The Orion and Discovery (MV643xx) families share the same I2C controller)
****************************************************************************/
static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource orion_i2c_resources[] = {
static struct resource orion5x_i2c_resources[] = {
{
.name = "i2c base",
.start = I2C_PHYS_BASE,
@ -235,56 +248,70 @@ static struct resource orion_i2c_resources[] = {
},
{
.name = "i2c irq",
.start = IRQ_ORION_I2C,
.end = IRQ_ORION_I2C,
.start = IRQ_ORION5X_I2C,
.end = IRQ_ORION5X_I2C,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_i2c = {
static struct platform_device orion5x_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(orion_i2c_resources),
.resource = orion_i2c_resources,
.num_resources = ARRAY_SIZE(orion5x_i2c_resources),
.resource = orion5x_i2c_resources,
.dev = {
.platform_data = &orion_i2c_pdata,
.platform_data = &orion5x_i2c_pdata,
},
};
/*****************************************************************************
* Sata port
****************************************************************************/
static struct resource orion_sata_resources[] = {
static struct resource orion5x_sata_resources[] = {
{
.name = "sata base",
.start = ORION_SATA_PHYS_BASE,
.end = ORION_SATA_PHYS_BASE + 0x5000 - 1,
.start = ORION5X_SATA_PHYS_BASE,
.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "sata irq",
.start = IRQ_ORION_SATA,
.end = IRQ_ORION_SATA,
.start = IRQ_ORION5X_SATA,
.end = IRQ_ORION5X_SATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_sata = {
static struct platform_device orion5x_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(orion_sata_resources),
.resource = orion_sata_resources,
.num_resources = ARRAY_SIZE(orion5x_sata_resources),
.resource = orion5x_sata_resources,
};
void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
orion_sata.dev.platform_data = sata_data;
platform_device_register(&orion_sata);
sata_data->dram = &orion5x_mbus_dram_info;
orion5x_sata.dev.platform_data = sata_data;
platform_device_register(&orion5x_sata);
}
/*****************************************************************************
* Time handling
****************************************************************************/
static void orion5x_timer_init(void)
{
orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
}
struct sys_timer orion5x_timer = {
.init = orion5x_timer_init,
};
/*****************************************************************************
* General
****************************************************************************/
@ -292,9 +319,9 @@ void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
/*
* Identify device ID and rev from PCIE configuration header space '0'.
*/
static void orion_id(u32 *dev, u32 *rev, char **dev_name)
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
{
orion_pcie_id(dev, rev);
orion5x_pcie_id(dev, rev);
if (*dev == MV88F5281_DEV_ID) {
if (*rev == MV88F5281_REV_D2) {
@ -321,33 +348,28 @@ static void orion_id(u32 *dev, u32 *rev, char **dev_name)
}
}
void __init orion_init(void)
void __init orion5x_init(void)
{
char *dev_name;
u32 dev, rev;
orion_id(&dev, &rev, &dev_name);
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK);
orion5x_id(&dev, &rev, &dev_name);
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK);
/*
* Setup Orion address map
*/
orion_setup_cpu_wins();
orion_setup_usb_wins();
orion_setup_eth_wins();
orion_setup_pci_wins();
orion_setup_pcie_wins();
if (dev == MV88F5182_DEV_ID)
orion_setup_sata_wins();
orion5x_setup_cpu_mbus_bridge();
orion5x_setup_eth_wins();
/*
* REgister devices
* Register devices.
*/
platform_device_register(&orion_uart);
platform_device_register(&orion_ehci0);
platform_device_register(&orion5x_uart);
platform_device_register(&orion5x_ehci0);
if (dev == MV88F5182_DEV_ID)
platform_device_register(&orion_ehci1);
platform_device_register(&orion_i2c);
platform_device_register(&orion5x_ehci1);
platform_device_register(&orion5x_i2c);
}
/*

72
arch/arm/mach-orion5x/common.h Normal file
View File

@ -0,0 +1,72 @@
#ifndef __ARCH_ORION5X_COMMON_H
#define __ARCH_ORION5X_COMMON_H
/*
* Basic Orion init functions used early by machine-setup.
*/
void orion5x_map_io(void);
void orion5x_init_irq(void);
void orion5x_init(void);
extern struct sys_timer orion5x_timer;
/*
* Enumerations and functions for Orion windows mapping. Used by Orion core
* functions to map its interfaces and by the machine-setup to map its on-
* board devices. Details in /mach-orion/addr-map.c
*/
extern struct mbus_dram_target_info orion5x_mbus_dram_info;
void orion5x_setup_cpu_mbus_bridge(void);
void orion5x_setup_dev_boot_win(u32 base, u32 size);
void orion5x_setup_dev0_win(u32 base, u32 size);
void orion5x_setup_dev1_win(u32 base, u32 size);
void orion5x_setup_dev2_win(u32 base, u32 size);
void orion5x_setup_pcie_wa_win(u32 base, u32 size);
void orion5x_setup_eth_wins(void);
/*
* Shared code used internally by other Orion core functions.
* (/mach-orion/pci.c)
*/
struct pci_sys_data;
struct pci_bus;
void orion5x_pcie_id(u32 *dev, u32 *rev);
int orion5x_pcie_local_bus_nr(void);
int orion5x_pci_local_bus_nr(void);
int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
/*
* Valid GPIO pins according to MPP setup, used by machine-setup.
* (/mach-orion/gpio.c).
*/
void orion5x_gpio_set_valid_pins(u32 pins);
void gpio_display(void); /* debug */
/*
* Pull in Orion Ethernet platform_data, used by machine-setup
*/
struct mv643xx_eth_platform_data;
void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
/*
* Orion Sata platform_data, used by machine-setup
*/
struct mv_sata_platform_data;
void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
struct machine_desc;
struct meminfo;
struct tag;
extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
char **, struct meminfo *);
#endif

55
arch/arm/mach-orion/db88f5281-setup.c → arch/arm/mach-orion5x/db88f5281-setup.c
View File

@ -1,12 +1,12 @@
/*
* arch/arm/mach-orion/db88f5281-setup.c
* arch/arm/mach-orion5x/db88f5281-setup.c
*
* Marvell Orion-2 Development Board Setup
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
@ -24,8 +24,8 @@
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/arch/orion.h>
#include <asm/arch/platform.h>
#include <asm/arch/orion5x.h>
#include <asm/plat-orion/orion_nand.h>
#include "common.h"
/*****************************************************************************
@ -244,8 +244,8 @@ static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
/*
* PCIE IRQ is connected internally (not GPIO)
*/
if (dev->bus->number == orion_pcie_local_bus_nr())
return IRQ_ORION_PCIE0_INT;
if (dev->bus->number == orion5x_pcie_local_bus_nr())
return IRQ_ORION5X_PCIE0_INT;
/*
* PCI IRQs are connected via GPIOs
@ -265,8 +265,8 @@ static struct hw_pci db88f5281_pci __initdata = {
.nr_controllers = 2,
.preinit = db88f5281_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = orion_pci_sys_setup,
.scan = orion_pci_sys_scan_bus,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = db88f5281_pci_map_irq,
};
@ -312,19 +312,16 @@ static void __init db88f5281_init(void)
/*
* Basic Orion setup. Need to be called early.
*/
orion_init();
orion5x_init();
/*
* Setup the CPU address decode windows for our on-board devices
*/
orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
DB88F5281_NOR_BOOT_SIZE, -1);
orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE,
DB88F5281_7SEG_SIZE, -1);
orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
DB88F5281_NOR_SIZE, -1);
orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE,
DB88F5281_NAND_SIZE, -1);
orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
DB88F5281_NOR_BOOT_SIZE);
orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
/*
* Setup Multiplexing Pins:
@ -340,25 +337,25 @@ static void __init db88f5281_init(void)
* MPP18: UART1_CTS MPP19: UART1_RTS
* MPP-DEV: DEV_D[16:31]
*/
orion_write(MPP_0_7_CTRL, 0x00222203);
orion_write(MPP_8_15_CTRL, 0x44000000);
orion_write(MPP_16_19_CTRL, 0);
orion_write(MPP_DEV_CTRL, 0);
orion5x_write(MPP_0_7_CTRL, 0x00222203);
orion5x_write(MPP_8_15_CTRL, 0x44000000);
orion5x_write(MPP_16_19_CTRL, 0);
orion5x_write(MPP_DEV_CTRL, 0);
orion_gpio_set_valid_pins(0x00003fc3);
orion5x_gpio_set_valid_pins(0x00003fc3);
platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
orion_eth_init(&db88f5281_eth_data);
orion5x_eth_init(&db88f5281_eth_data);
}
MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
.phys_io = ORION_REGS_PHYS_BASE,
.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
.phys_io = ORION5X_REGS_PHYS_BASE,
.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = db88f5281_init,
.map_io = orion_map_io,
.init_irq = orion_init_irq,
.timer = &orion_timer,
.map_io = orion5x_map_io,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
MACHINE_END

45
arch/arm/mach-orion/dns323-setup.c → arch/arm/mach-orion5x/dns323-setup.c
View File

@ -1,5 +1,5 @@
/*
* arch/arm/mach-orion/dns323-setup.c
* arch/arm/mach-orion5x/dns323-setup.c
*
* Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
*
@ -25,8 +25,7 @@
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/arch/orion.h>
#include <asm/arch/platform.h>
#include <asm/arch/orion5x.h>
#include "common.h"
#define DNS323_GPIO_LED_RIGHT_AMBER 1
@ -45,8 +44,8 @@
static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
/* PCI-E */
if (dev->bus->number == orion_pcie_local_bus_nr())
return IRQ_ORION_PCIE0_INT;
if (dev->bus->number == orion5x_pcie_local_bus_nr())
return IRQ_ORION5X_PCIE0_INT;
pr_err("%s: requested mapping for unknown bus\n", __func__);
@ -56,8 +55,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static struct hw_pci dns323_pci __initdata = {
.nr_controllers = 1,
.swizzle = pci_std_swizzle,
.setup = orion_pci_sys_setup,
.scan = orion_pci_sys_scan_bus,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = dns323_pci_map_irq,
};
@ -247,27 +246,25 @@ static void dns323_power_off(void)
static void __init dns323_init(void)
{
/* Setup basic Orion functions. Need to be called early. */
orion_init();
orion5x_init();
/* setup flash mapping
* CS3 holds a 8 MB Spansion S29GL064M90TFIR4
*/
orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE,
DNS323_NOR_BOOT_SIZE, -1);
orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
/* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE
*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
orion_write(ORION_REGS_VIRT_BASE | 0x20070,
(0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
ORION5X_PCIE_WA_SIZE);
/* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
orion_write(MPP_0_7_CTRL, 0);
orion_write(MPP_8_15_CTRL, 0);
orion_write(MPP_16_19_CTRL, 0);
orion_write(MPP_DEV_CTRL, 0);
orion5x_write(MPP_0_7_CTRL, 0);
orion5x_write(MPP_8_15_CTRL, 0);
orion5x_write(MPP_16_19_CTRL, 0);
orion5x_write(MPP_DEV_CTRL, 0);
/* Define used GPIO pins
@ -290,7 +287,7 @@ static void __init dns323_init(void)
| 14 | Out | //unknown//
| 15 | Out | //unknown//
*/
orion_gpio_set_valid_pins(0x07f6);
orion5x_gpio_set_valid_pins(0x07f6);
/* register dns323 specific power-off method */
if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
@ -306,18 +303,18 @@ static void __init dns323_init(void)
i2c_register_board_info(0, dns323_i2c_devices,
ARRAY_SIZE(dns323_i2c_devices));
orion_eth_init(&dns323_eth_data);
orion5x_eth_init(&dns323_eth_data);
}
/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
MACHINE_START(DNS323, "D-Link DNS-323")
/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
.phys_io = ORION_REGS_PHYS_BASE,
.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.phys_io = ORION5X_REGS_PHYS_BASE,
.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = dns323_init,
.map_io = orion_map_io,
.init_irq = orion_init_irq,
.timer = &orion_timer,
.map_io = orion5x_map_io,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
MACHINE_END

77
arch/arm/mach-orion/gpio.c → arch/arm/mach-orion5x/gpio.c
View File

@ -1,12 +1,12 @@
/*
* arch/arm/mach-orion/gpio.c
* arch/arm/mach-orion5x/gpio.c
*
* GPIO functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
@ -16,14 +16,15 @@
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <asm/gpio.h>
#include <asm/arch/orion.h>
#include <asm/io.h>
#include <asm/arch/orion5x.h>
#include "common.h"
static DEFINE_SPINLOCK(gpio_lock);
static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */
void __init orion_gpio_set_valid_pins(u32 pins)
void __init orion5x_gpio_set_valid_pins(u32 pins)
{
gpio_valid[0] = pins;
}
@ -49,7 +50,7 @@ int gpio_direction_input(unsigned pin)
if (!gpio_label[pin])
gpio_label[pin] = "?";
orion_setbits(GPIO_IO_CONF, 1 << pin);
orion5x_setbits(GPIO_IO_CONF, 1 << pin);
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
@ -76,12 +77,12 @@ int gpio_direction_output(unsigned pin, int value)
gpio_label[pin] = "?";
mask = 1 << pin;
orion_clrbits(GPIO_BLINK_EN, mask);
orion5x_clrbits(GPIO_BLINK_EN, mask);
if (value)
orion_setbits(GPIO_OUT, mask);
orion5x_setbits(GPIO_OUT, mask);
else
orion_clrbits(GPIO_OUT, mask);
orion_clrbits(GPIO_IO_CONF, mask);
orion5x_clrbits(GPIO_OUT, mask);
orion5x_clrbits(GPIO_IO_CONF, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
@ -92,10 +93,10 @@ int gpio_get_value(unsigned pin)
{
int val, mask = 1 << pin;
if (orion_read(GPIO_IO_CONF) & mask)
val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL);
if (orion5x_read(GPIO_IO_CONF) & mask)
val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL);
else
val = orion_read(GPIO_OUT);
val = orion5x_read(GPIO_OUT);
return val & mask;
}
@ -108,32 +109,32 @@ void gpio_set_value(unsigned pin, int value)
spin_lock_irqsave(&gpio_lock, flags);
orion_clrbits(GPIO_BLINK_EN, mask);
orion5x_clrbits(GPIO_BLINK_EN, mask);
if (value)
orion_setbits(GPIO_OUT, mask);
orion5x_setbits(GPIO_OUT, mask);
else
orion_clrbits(GPIO_OUT, mask);
orion5x_clrbits(GPIO_OUT, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
}
EXPORT_SYMBOL(gpio_set_value);
void orion_gpio_set_blink(unsigned pin, int blink)
void orion5x_gpio_set_blink(unsigned pin, int blink)
{
unsigned long flags;
int mask = 1 << pin;
spin_lock_irqsave(&gpio_lock, flags);
orion_clrbits(GPIO_OUT, mask);
orion5x_clrbits(GPIO_OUT, mask);
if (blink)
orion_setbits(GPIO_BLINK_EN, mask);
orion5x_setbits(GPIO_BLINK_EN, mask);
else
orion_clrbits(GPIO_BLINK_EN, mask);
orion5x_clrbits(GPIO_BLINK_EN, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
}
EXPORT_SYMBOL(orion_gpio_set_blink);
EXPORT_SYMBOL(orion5x_gpio_set_blink);
int gpio_request(unsigned pin, const char *label)
{
@ -187,39 +188,39 @@ void gpio_display(void)
printk("GPIO, free\n");
} else {
printk("GPIO, used by %s, ", gpio_label[i]);
if (orion_read(GPIO_IO_CONF) & (1 << i)) {
if (orion5x_read(GPIO_IO_CONF) & (1 << i)) {
printk("input, active %s, level %s, edge %s\n",
((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
} else {
printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1);
printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1);
}
}
}
printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL));
MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL));
printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL));
MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL));
printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL));
MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL));
printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL));
MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL));
printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
GPIO_OUT, orion_read(GPIO_OUT));
GPIO_OUT, orion5x_read(GPIO_OUT));
printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
GPIO_IO_CONF, orion_read(GPIO_IO_CONF));
GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF));
printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN));
GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN));
printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
GPIO_IN_POL, orion_read(GPIO_IN_POL));
GPIO_IN_POL, orion5x_read(GPIO_IN_POL));
printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
GPIO_DATA_IN, orion_read(GPIO_DATA_IN));
GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN));
printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK));
GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK));
printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE));
GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE));
printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK));
GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK));
}

132
arch/arm/mach-orion/irq.c → arch/arm/mach-orion5x/irq.c
View File

@ -1,12 +1,12 @@
/*
* arch/arm/mach-orion/irq.c
* arch/arm/mach-orion5x/irq.c
*
* Core IRQ functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
@ -14,7 +14,9 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/gpio.h>
#include <asm/arch/orion.h>
#include <asm/io.h>
#include <asm/arch/orion5x.h>
#include <asm/plat-orion/irq.h>
#include "common.h"
/*****************************************************************************
@ -42,46 +44,46 @@
* polarity LEVEL mask
*
****************************************************************************/
static void orion_gpio_irq_ack(u32 irq)
static void orion5x_gpio_irq_ack(u32 irq)
{
int pin = irq_to_gpio(irq);
if (irq_desc[irq].status & IRQ_LEVEL)
/*
* Mask bit for level interrupt
*/
orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
else
/*
* Clear casue bit for egde interrupt
*/
orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
}
static void orion_gpio_irq_mask(u32 irq)
static void orion5x_gpio_irq_mask(u32 irq)
{
int pin = irq_to_gpio(irq);
if (irq_desc[irq].status & IRQ_LEVEL)
orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
else
orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
}
static void orion_gpio_irq_unmask(u32 irq)
static void orion5x_gpio_irq_unmask(u32 irq)
{
int pin = irq_to_gpio(irq);
if (irq_desc[irq].status & IRQ_LEVEL)
orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
else
orion_setbits(GPIO_EDGE_MASK, 1 << pin);
orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
}
static int orion_gpio_set_irq_type(u32 irq, u32 type)
static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
{
int pin = irq_to_gpio(irq);
struct irq_desc *desc;
if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
printk(KERN_ERR "orion_gpio_set_irq_type failed "
if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
"(irq %d, pin %d).\n", irq, pin);
return -EINVAL;
}
@ -92,22 +94,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type)
case IRQT_HIGH:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
orion_clrbits(GPIO_IN_POL, (1 << pin));
orion5x_clrbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_LOW:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
orion_setbits(GPIO_IN_POL, (1 << pin));
orion5x_setbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_RISING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
orion_clrbits(GPIO_IN_POL, (1 << pin));
orion5x_clrbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_FALLING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
orion_setbits(GPIO_IN_POL, (1 << pin));
orion5x_setbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_BOTHEDGE:
desc->handle_irq = handle_edge_irq;
@ -115,11 +117,11 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type)
/*
* set initial polarity based on current input level
*/
if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN))
& (1 << pin))
orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
else
orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
break;
default:
@ -133,22 +135,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type)
return 0;
}
static struct irq_chip orion_gpio_irq_chip = {
static struct irq_chip orion5x_gpio_irq_chip = {
.name = "Orion-IRQ-GPIO",
.ack = orion_gpio_irq_ack,
.mask = orion_gpio_irq_mask,
.unmask = orion_gpio_irq_unmask,
.set_type = orion_gpio_set_irq_type,
.ack = orion5x_gpio_irq_ack,
.mask = orion5x_gpio_irq_mask,
.unmask = orion5x_gpio_irq_unmask,
.set_type = orion5x_gpio_set_irq_type,
};
static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
u32 cause, offs, pin;
BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
(orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) |
(orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK));
for (pin = offs; pin < offs + 8; pin++) {
if (cause & (1 << pin)) {
@ -156,16 +158,16 @@ static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
desc = irq_desc + irq;
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
/* Swap polarity (race with GPIO line) */
u32 polarity = orion_read(GPIO_IN_POL);
u32 polarity = orion5x_read(GPIO_IN_POL);
polarity ^= 1 << pin;
orion_write(GPIO_IN_POL, polarity);
orion5x_write(GPIO_IN_POL, polarity);
}
desc_handle_irq(irq, desc);
}
}
}
static void __init orion_init_gpio_irq(void)
static void __init orion5x_init_gpio_irq(void)
{
int i;
struct irq_desc *desc;
@ -173,69 +175,37 @@ static void __init orion_init_gpio_irq(void)
/*
* Mask and clear GPIO IRQ interrupts
*/
orion_write(GPIO_LEVEL_MASK, 0x0);
orion_write(GPIO_EDGE_MASK, 0x0);
orion_write(GPIO_EDGE_CAUSE, 0x0);
orion5x_write(GPIO_LEVEL_MASK, 0x0);
orion5x_write(GPIO_EDGE_MASK, 0x0);
orion5x_write(GPIO_EDGE_CAUSE, 0x0);
/*
* Register chained level handlers for GPIO IRQs by default.
* User can use set_type() if he wants to use edge types handlers.
*/
for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion5x_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
desc = irq_desc + i;
desc->status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler);
}
/*****************************************************************************
* Orion Main IRQ
****************************************************************************/
static void orion_main_irq_mask(u32 irq)
static void __init orion5x_init_main_irq(void)
{
orion_clrbits(MAIN_IRQ_MASK, 1 << irq);
orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
}
static void orion_main_irq_unmask(u32 irq)
void __init orion5x_init_irq(void)
{
orion_setbits(MAIN_IRQ_MASK, 1 << irq);
}
static struct irq_chip orion_main_irq_chip = {
.name = "Orion-IRQ-Main",
.ack = orion_main_irq_mask,
.mask = orion_main_irq_mask,
.unmask = orion_main_irq_unmask,
};
static void __init orion_init_main_irq(void)
{
int i;
/*
* Mask and clear Main IRQ interrupts
*/
orion_write(MAIN_IRQ_MASK, 0x0);
orion_write(MAIN_IRQ_CAUSE, 0x0);
/*
* Register level handler for Main IRQs
*/
for (i = 0; i < IRQ_ORION_GPIO_START; i++) {
set_irq_chip(i, &orion_main_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
void __init orion_init_irq(void)
{
orion_init_main_irq();
orion_init_gpio_irq();
orion5x_init_main_irq();
orion5x_init_gpio_irq();
}

80
arch/arm/mach-orion/kurobox_pro-setup.c → arch/arm/mach-orion5x/kurobox_pro-setup.c
View File

@ -1,10 +1,10 @@
/*
* arch/arm/mach-orion/kurobox_pro-setup.c
* arch/arm/mach-orion5x/kurobox_pro-setup.c
*
* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
@ -22,8 +22,8 @@
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/arch/orion.h>
#include <asm/arch/platform.h>
#include <asm/arch/orion5x.h>
#include <asm/plat-orion/orion_nand.h>
#include "common.h"
/*****************************************************************************
@ -123,8 +123,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
/*
* PCI isn't used on the Kuro
*/
if (dev->bus->number == orion_pcie_local_bus_nr())
return IRQ_ORION_PCIE0_INT;
if (dev->bus->number == orion5x_pcie_local_bus_nr())
return IRQ_ORION5X_PCIE0_INT;
else
printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
@ -134,8 +134,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static struct hw_pci kurobox_pro_pci __initdata = {
.nr_controllers = 1,
.swizzle = pci_std_swizzle,
.setup = orion_pci_sys_setup,
.scan = orion_pci_sys_scan_bus,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = kurobox_pro_pci_map_irq,
};
@ -178,31 +178,25 @@ static struct mv_sata_platform_data kurobox_pro_sata_data = {
* General Setup
****************************************************************************/
static struct platform_device *kurobox_pro_devices[] __initdata = {
&kurobox_pro_nor_flash,
&kurobox_pro_nand_flash,
};
static void __init kurobox_pro_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion_init();
orion5x_init();
/*
* Setup the CPU address decode windows for our devices
*/
orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE,
KUROBOX_PRO_NOR_BOOT_SIZE, -1);
orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE,
KUROBOX_PRO_NAND_SIZE, -1);
orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
KUROBOX_PRO_NOR_BOOT_SIZE);
orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE);
/*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
ORION5X_PCIE_WA_SIZE);
/*
* Setup Multiplexing Pins --
@ -219,26 +213,44 @@ static void __init kurobox_pro_init(void)
* MPP[15] SATA 1 active indication
* MPP[16-19] Not used
*/
orion_write(MPP_0_7_CTRL, 0x44220003);
orion_write(MPP_8_15_CTRL, 0x55550000);
orion_write(MPP_16_19_CTRL, 0x0);
orion5x_write(MPP_0_7_CTRL, 0x44220003);
orion5x_write(MPP_8_15_CTRL, 0x55550000);
orion5x_write(MPP_16_19_CTRL, 0x0);
orion_gpio_set_valid_pins(0x0000000c);
orion5x_gpio_set_valid_pins(0x0000000c);
platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
platform_device_register(&kurobox_pro_nor_flash);
if (machine_is_kurobox_pro())
platform_device_register(&kurobox_pro_nand_flash);
i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
orion_eth_init(&kurobox_pro_eth_data);
orion_sata_init(&kurobox_pro_sata_data);
orion5x_eth_init(&kurobox_pro_eth_data);
orion5x_sata_init(&kurobox_pro_sata_data);
}
#ifdef CONFIG_MACH_KUROBOX_PRO
MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
.phys_io = ORION_REGS_PHYS_BASE,
.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.phys_io = ORION5X_REGS_PHYS_BASE,
.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion_map_io,
.init_irq = orion_init_irq,
.timer = &orion_timer,
.map_io = orion5x_map_io,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
MACHINE_END
#endif
#ifdef CONFIG_MACH_LINKSTATION_PRO
MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
/* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
.phys_io = ORION5X_REGS_PHYS_BASE,
.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion5x_map_io,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
MACHINE_END
#endif

559
arch/arm/mach-orion5x/pci.c Normal file
View File

@ -0,0 +1,559 @@
/*
* arch/arm/mach-orion5x/pci.c
*
* PCI and PCIe functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <asm/mach/pci.h>
#include <asm/plat-orion/pcie.h>
#include "common.h"
/*****************************************************************************
* Orion has one PCIe controller and one PCI controller.
*
* Note1: The local PCIe bus number is '0'. The local PCI bus number
* follows the scanned PCIe bridged busses, if any.
*
* Note2: It is possible for PCI/PCIe agents to access many subsystem's
* space, by configuring BARs and Address Decode Windows, e.g. flashes on
* device bus, Orion registers, etc. However this code only enable the
* access to DDR banks.
****************************************************************************/
/*****************************************************************************
* PCIe controller
****************************************************************************/
#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
void __init orion5x_pcie_id(u32 *dev, u32 *rev)
{
*dev = orion_pcie_dev_id(PCIE_BASE);
*rev = orion_pcie_rev(PCIE_BASE);
}
int __init orion5x_pcie_local_bus_nr(void)
{
return orion_pcie_get_local_bus_nr(PCIE_BASE);
}
static int pcie_valid_config(int bus, int dev)
{
/*
* Don't go out when trying to access --
* 1. nonexisting device on local bus
* 2. where there's no device connected (no link)
*/
if (bus == 0 && dev == 0)
return 1;
if (!orion_pcie_link_up(PCIE_BASE))
return 0;
if (bus == 0 && dev != 1)
return 0;
return 1;
}
/*
* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
* and then reading the PCIE_CONF_DATA register. Need to make sure these
* transactions are atomic.
*/
static DEFINE_SPINLOCK(orion5x_pcie_lock);
static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
unsigned long flags;
int ret;
if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
spin_lock_irqsave(&orion5x_pcie_lock, flags);
ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
return ret;
}
static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
int where, int size, u32 *val)
{
int ret;
if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
/*
* We only support access to the non-extended configuration
* space when using the WA access method (or we would have to
* sacrifice 256M of CPU virtual address space.)
*/
if (where >= 0x100) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
bus, devfn, where, size, val);
return ret;
}
static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
unsigned long flags;
int ret;
if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
spin_lock_irqsave(&orion5x_pcie_lock, flags);
ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
return ret;
}
static struct pci_ops pcie_ops = {
.read = pcie_rd_conf,
.write = pcie_wr_conf,
};
static int __init pcie_setup(struct pci_sys_data *sys)
{
struct resource *res;
int dev;
/*
* Generic PCIe unit setup.
*/
orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
/*
* Check whether to apply Orion-1/Orion-NAS PCIe config
* read transaction workaround.
*/
dev = orion_pcie_dev_id(PCIE_BASE);
if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
"read transaction workaround\n");
pcie_ops.read = pcie_rd_conf_wa;
}
/*
* Request resources.
*/
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
if (!res)
panic("pcie_setup unable to alloc resources");
/*
* IORESOURCE_IO
*/
res[0].name = "PCIe I/O Space";
res[0].flags = IORESOURCE_IO;
res[0].start = ORION5X_PCIE_IO_BUS_BASE;
res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCIe IO resource failed\n");
sys->resource[0] = &res[0];
/*
* IORESOURCE_MEM
*/
res[1].name = "PCIe Memory Space";
res[1].flags = IORESOURCE_MEM;
res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCIe Memory resource failed\n");
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
sys->io_offset = 0;
return 1;
}
/*****************************************************************************
* PCI controller
****************************************************************************/
#define PCI_MODE ORION5X_PCI_REG(0xd00)
#define PCI_CMD ORION5X_PCI_REG(0xc00)
#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
/*
* PCI_MODE bits
*/
#define PCI_MODE_64BIT (1 << 2)
#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
/*
* PCI_CMD bits
*/
#define PCI_CMD_HOST_REORDER (1 << 29)
/*
* PCI_P2P_CONF bits
*/
#define PCI_P2P_BUS_OFFS 16
#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS 24
#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
/*
* PCI_CONF_ADDR bits
*/
#define PCI_CONF_REG(reg) ((reg) & 0xfc)
#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN (1 << 31)
/*
* Internal configuration space
*/
#define PCI_CONF_FUNC_STAT_CMD 0
#define PCI_CONF_REG_STAT_CMD 4
#define PCIX_STAT 0x64
#define PCIX_STAT_BUS_OFFS 8
#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
/*
* PCI Address Decode Windows registers
*/
#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \
((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
/*
* PCI configuration helpers for BAR settings
*/
#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
/*
* PCI config cycles are done by programming the PCI_CONF_ADDR register
* and then reading the PCI_CONF_DATA register. Need to make sure these
* transactions are atomic.
*/
static DEFINE_SPINLOCK(orion5x_pci_lock);
int orion5x_pci_local_bus_nr(void)
{
u32 conf = orion5x_read(PCI_P2P_CONF);
return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}
static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
u32 where, u32 size, u32 *val)
{
unsigned long flags;
spin_lock_irqsave(&orion5x_pci_lock, flags);
orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
*val = orion5x_read(PCI_CONF_DATA);
if (size == 1)
*val = (*val >> (8*(where & 0x3))) & 0xff;
else if (size == 2)
*val = (*val >> (8*(where & 0x3))) & 0xffff;
spin_unlock_irqrestore(&orion5x_pci_lock, flags);
return PCIBIOS_SUCCESSFUL;
}
static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
u32 where, u32 size, u32 val)
{
unsigned long flags;
int ret = PCIBIOS_SUCCESSFUL;
spin_lock_irqsave(&orion5x_pci_lock, flags);
orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
if (size == 4) {
__raw_writel(val, PCI_CONF_DATA);
} else if (size == 2) {
__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
} else if (size == 1) {
__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
} else {
ret = PCIBIOS_BAD_REGISTER_NUMBER;
}
spin_unlock_irqrestore(&orion5x_pci_lock, flags);
return ret;
}
static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 *val)
{
/*
* Don't go out for local device
*/
if (bus->number == orion5x_pci_local_bus_nr() &&
PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
PCI_FUNC(devfn), where, size, val);
}
static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
if (bus->number == orion5x_pci_local_bus_nr() &&
PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
return PCIBIOS_DEVICE_NOT_FOUND;
return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
PCI_FUNC(devfn), where, size, val);
}
static struct pci_ops pci_ops = {
.read = orion5x_pci_rd_conf,
.write = orion5x_pci_wr_conf,
};
static void __init orion5x_pci_set_bus_nr(int nr)
{
u32 p2p = orion5x_read(PCI_P2P_CONF);
if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) {
/*
* PCI-X mode
*/
u32 pcix_status, bus, dev;
bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
pcix_status &= ~PCIX_STAT_BUS_MASK;
pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
} else {
/*
* PCI Conventional mode
*/
p2p &= ~PCI_P2P_BUS_MASK;
p2p |= (nr << PCI_P2P_BUS_OFFS);
orion5x_write(PCI_P2P_CONF, p2p);
}
}
static void __init orion5x_pci_master_slave_enable(void)
{
int bus_nr, func, reg;
u32 val;
bus_nr = orion5x_pci_local_bus_nr();
func = PCI_CONF_FUNC_STAT_CMD;
reg = PCI_CONF_REG_STAT_CMD;
orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
}
static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
{
u32 win_enable;
int bus;
int i;
/*
* First, disable windows.
*/
win_enable = 0xffffffff;
orion5x_write(PCI_BAR_ENABLE, win_enable);
/*
* Setup windows for DDR banks.
*/
bus = orion5x_pci_local_bus_nr();
for (i = 0; i < dram->num_cs; i++) {
struct mbus_dram_window *cs = dram->cs + i;
u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
u32 reg;
u32 val;
/*
* Write DRAM bank base address register.
*/
reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
val = (cs->base & 0xfffff000) | (val & 0xfff);
orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
/*
* Write DRAM bank size register.
*/
reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
(cs->size - 1) & 0xfffff000);
orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
cs->base & 0xfffff000);
/*
* Enable decode window for this chip select.
*/
win_enable &= ~(1 << cs->cs_index);
}
/*
* Re-enable decode windows.
*/
orion5x_write(PCI_BAR_ENABLE, win_enable);
/*
* Disable automatic update of address remaping when writing to BARs.
*/
orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
}
static int __init pci_setup(struct pci_sys_data *sys)
{
struct resource *res;
/*
* Point PCI unit MBUS decode windows to DRAM space.
*/
orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
/*
* Master + Slave enable
*/
orion5x_pci_master_slave_enable();
/*
* Force ordering
*/
orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
/*
* Request resources
*/
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
if (!res)
panic("pci_setup unable to alloc resources");
/*
* IORESOURCE_IO
*/
res[0].name = "PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[0].start = ORION5X_PCI_IO_BUS_BASE;
res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCI IO resource failed\n");
sys->resource[0] = &res[0];
/*
* IORESOURCE_MEM
*/
res[1].name = "PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCI Memory resource failed\n");
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
sys->io_offset = 0;
return 1;
}
/*****************************************************************************
* General PCIe + PCI
****************************************************************************/
static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
/*
* Prevent enumeration of root complex.
*/
if (dev->bus->parent == NULL && dev->devfn == 0) {
int i;
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
dev->resource[i].start = 0;
dev->resource[i].end = 0;
dev->resource[i].flags = 0;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
if (nr == 0) {
orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
ret = pcie_setup(sys);
} else if (nr == 1) {
orion5x_pci_set_bus_nr(sys->busnr);
ret = pci_setup(sys);
}
return ret;
}
struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
{
struct pci_bus *bus;
if (nr == 0) {
bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
} else if (nr == 1) {
bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
} else {
bus = NULL;
BUG();
}
return bus;
}

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