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arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes

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The J7200 Main NavSS block contains a Mailbox IP instance with
multiple clusters, and follows the same integration style as on
J721E SoCs.

Add all the Mailbox clusters as their own nodes under the MAIN
NavSS interconnect node instead of creating an almost empty parent
node for the new K3 mailbox IP and the clusters as its child nodes.
All these nodes are enabled by default in the base dtsi file, but
any cluster that does not define any child sub-mailbox nodes
should be disabled in the corresponding board dts files.

NOTE:
The NavSS only has a limited number of interrupts, so none of the
interrupts generated by a Mailbox IP are added by default. Only
the needed interrupts that are targeted towards the A72 GIC will
have to be added later on in the board dts files alongside the
corresponding sub-mailbox child nodes.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>
Link: https://lore.kernel.org/r/20201026232637.15681-3-s-anna@ti.com
This commit is contained in:
Suman Anna 2020-10-26 18:26:36 -05:00 committed by Nishanth Menon
parent 1d7a01c408
commit d15d1cfbd7
1 changed files with 108 additions and 0 deletions
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108
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
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@ -121,6 +121,114 @@
#hwlock-cells = <1>;
};
mailbox0_cluster0: mailbox@31f80000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f80000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster1: mailbox@31f81000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f81000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster2: mailbox@31f82000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f82000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster3: mailbox@31f83000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f83000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster4: mailbox@31f84000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f84000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster5: mailbox@31f85000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f85000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster6: mailbox@31f86000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f86000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster7: mailbox@31f87000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f87000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster8: mailbox@31f88000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f88000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster9: mailbox@31f89000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f89000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster10: mailbox@31f8a000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8a000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster11: mailbox@31f8b000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8b000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x3c000000 0x00 0x400000>,