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iommu/amd: Remove the unused device errata code
The device errata mechism is entirely unused, so remove it. Signed-off-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210402143312.372386-2-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -693,7 +693,6 @@ struct iommu_dev_data {
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} ats; /* ATS state */
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bool pri_tlp; /* PASID TLB required for
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PPR completions */
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u32 errata; /* Bitmap for errata to apply */
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bool use_vapic; /* Enable device to use vapic mode */
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bool defer_attach;
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@ -290,15 +290,6 @@ static bool pci_iommuv2_capable(struct pci_dev *pdev)
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return true;
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}
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static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
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{
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struct iommu_dev_data *dev_data;
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dev_data = dev_iommu_priv_get(&pdev->dev);
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return dev_data->errata & (1 << erratum) ? true : false;
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}
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/*
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* This function checks if the driver got a valid device from the caller to
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* avoid dereferencing invalid pointers.
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@ -1531,33 +1522,9 @@ static void pdev_iommuv2_disable(struct pci_dev *pdev)
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pci_disable_pasid(pdev);
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}
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/* FIXME: Change generic reset-function to do the same */
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static int pri_reset_while_enabled(struct pci_dev *pdev)
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{
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u16 control;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
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control |= PCI_PRI_CTRL_RESET;
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pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
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return 0;
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}
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static int pdev_iommuv2_enable(struct pci_dev *pdev)
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{
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bool reset_enable;
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int reqs, ret;
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/* FIXME: Hardcode number of outstanding requests for now */
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reqs = 32;
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if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
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reqs = 1;
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reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
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int ret;
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/* Only allow access to user-accessible pages */
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ret = pci_enable_pasid(pdev, 0);
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@ -1570,16 +1537,11 @@ static int pdev_iommuv2_enable(struct pci_dev *pdev)
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goto out_err;
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/* Enable PRI */
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ret = pci_enable_pri(pdev, reqs);
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/* FIXME: Hardcode number of outstanding requests for now */
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ret = pci_enable_pri(pdev, 32);
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if (ret)
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goto out_err;
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if (reset_enable) {
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ret = pri_reset_while_enabled(pdev);
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if (ret)
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goto out_err;
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}
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ret = pci_enable_ats(pdev, PAGE_SHIFT);
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if (ret)
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goto out_err;
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@ -2594,18 +2556,6 @@ struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
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}
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EXPORT_SYMBOL(amd_iommu_get_v2_domain);
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void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
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{
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struct iommu_dev_data *dev_data;
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if (!amd_iommu_v2_supported())
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return;
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dev_data = dev_iommu_priv_get(&pdev->dev);
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dev_data->errata |= (1 << erratum);
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}
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EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
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int amd_iommu_device_info(struct pci_dev *pdev,
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struct amd_iommu_device_info *info)
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{
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@ -32,24 +32,6 @@ struct pci_dev;
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extern int amd_iommu_detect(void);
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extern int amd_iommu_init_hardware(void);
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/**
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* amd_iommu_enable_device_erratum() - Enable erratum workaround for device
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* in the IOMMUv2 driver
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* @pdev: The PCI device the workaround is necessary for
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* @erratum: The erratum workaround to enable
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*
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* The function needs to be called before amd_iommu_init_device().
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* Possible values for the erratum number are for now:
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* - AMD_PRI_DEV_ERRATUM_ENABLE_RESET - Reset PRI capability when PRI
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* is enabled
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* - AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE - Limit number of outstanding PRI
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* requests to one
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*/
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#define AMD_PRI_DEV_ERRATUM_ENABLE_RESET 0
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#define AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE 1
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extern void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum);
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/**
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* amd_iommu_init_device() - Init device for use with IOMMUv2 driver
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* @pdev: The PCI device to initialize
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