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synced 2024-11-11 12:28:41 +08:00
Merge remote-tracking branches 'spi/topic/adi-v3', 'spi/topic/atmel', 'spi/topic/cleanup' and 'spi/topic/davinci' into spi-next
This commit is contained in:
commit
d1345c524e
@ -8,7 +8,8 @@ Required properties:
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- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
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- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
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- reg: Offset and length of SPI controller register space
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- num-cs: Number of chip selects
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- num-cs: Number of chip selects. This includes internal as well as
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GPIO chip selects.
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- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
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IP to the interrupt controller within the SoC. Possible values
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are 0 and 1. Manual says one of the two possible interrupt
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@ -17,6 +18,12 @@ Required properties:
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- interrupts: interrupt number mapped to CPU.
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- clocks: spi clk phandle
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Optional:
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- cs-gpios: gpio chip selects
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For example to have 3 internal CS and 2 GPIO CS, user could define
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cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
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where first three are internal CS and last two are GPIO CS.
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Example of a NOR flash slave device (n25q032) connected to DaVinci
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SPI controller device over the SPI bus.
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@ -660,10 +660,9 @@ static int adi_spi_setup(struct spi_device *spi)
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struct adi_spi3_chip *chip_info = spi->controller_data;
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (!chip) {
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dev_err(&spi->dev, "can not allocate chip data\n");
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if (!chip)
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return -ENOMEM;
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}
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if (chip_info) {
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if (chip_info->control & ~ctl_reg) {
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dev_err(&spi->dev,
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@ -597,21 +597,15 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
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goto err_exit;
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/* Send both scatterlists */
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rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
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&as->dma.sgrx,
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1,
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DMA_FROM_DEVICE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
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NULL);
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rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
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DMA_FROM_DEVICE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!rxdesc)
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goto err_dma;
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txdesc = txchan->device->device_prep_slave_sg(txchan,
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&as->dma.sgtx,
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1,
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DMA_TO_DEVICE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
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NULL);
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txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
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DMA_TO_DEVICE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!txdesc)
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goto err_dma;
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@ -1018,7 +1012,7 @@ static int atmel_spi_setup(struct spi_device *spi)
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csr |= SPI_BF(DLYBCT, 0);
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/* chipselect must have been muxed as GPIO (e.g. in board setup) */
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npcs_pin = (unsigned int)spi->controller_data;
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npcs_pin = (unsigned long)spi->controller_data;
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if (gpio_is_valid(spi->cs_gpio))
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npcs_pin = spi->cs_gpio;
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@ -1253,7 +1247,7 @@ msg_done:
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static void atmel_spi_cleanup(struct spi_device *spi)
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{
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struct atmel_spi_device *asd = spi->controller_state;
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unsigned gpio = (unsigned) spi->controller_data;
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unsigned gpio = (unsigned long) spi->controller_data;
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if (!asd)
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return;
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@ -664,7 +664,7 @@ static int __maybe_unused cdns_spi_resume(struct device *dev)
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static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend,
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cdns_spi_resume);
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static struct of_device_id cdns_spi_of_match[] = {
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static const struct of_device_id cdns_spi_of_match[] = {
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{ .compatible = "xlnx,zynq-spi-r1p6" },
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{ .compatible = "cdns,spi-r1p6" },
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{ /* end of table */ }
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@ -184,8 +184,6 @@ static int spi_clps711x_probe(struct platform_device *pdev)
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}
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master->max_speed_hz = clk_get_rate(hw->spi_clk);
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platform_set_drvdata(pdev, master);
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hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3");
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if (IS_ERR(hw->syscon)) {
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ret = PTR_ERR(hw->syscon);
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@ -30,6 +30,7 @@
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#include <linux/edma.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/slab.h>
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@ -38,8 +39,6 @@
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#define SPI_NO_RESOURCE ((resource_size_t)-1)
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#define SPI_MAX_CHIPSELECT 2
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#define CS_DEFAULT 0xFF
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#define SPIFMT_PHASE_MASK BIT(16)
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@ -142,7 +141,7 @@ struct davinci_spi {
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void (*get_rx)(u32 rx_data, struct davinci_spi *);
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u32 (*get_tx)(struct davinci_spi *);
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u8 bytes_per_word[SPI_MAX_CHIPSELECT];
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u8 *bytes_per_word;
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};
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static struct davinci_spi_config davinci_spi_default_cfg;
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@ -213,13 +212,16 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
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u8 chip_sel = spi->chip_select;
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u16 spidat1 = CS_DEFAULT;
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bool gpio_chipsel = false;
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int gpio;
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dspi = spi_master_get_devdata(spi->master);
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pdata = &dspi->pdata;
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if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
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pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
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if (spi->cs_gpio >= 0) {
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/* SPI core parse and update master->cs_gpio */
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gpio_chipsel = true;
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gpio = spi->cs_gpio;
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}
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/*
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* Board specific chip select logic decides the polarity and cs
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@ -227,9 +229,9 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
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*/
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if (gpio_chipsel) {
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if (value == BITBANG_CS_ACTIVE)
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gpio_set_value(pdata->chip_sel[chip_sel], 0);
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gpio_set_value(gpio, spi->mode & SPI_CS_HIGH);
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else
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gpio_set_value(pdata->chip_sel[chip_sel], 1);
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gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH));
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} else {
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if (value == BITBANG_CS_ACTIVE) {
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spidat1 |= SPIDAT1_CSHOLD_MASK;
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@ -392,17 +394,40 @@ static int davinci_spi_setup(struct spi_device *spi)
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int retval = 0;
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struct davinci_spi *dspi;
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struct davinci_spi_platform_data *pdata;
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struct spi_master *master = spi->master;
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struct device_node *np = spi->dev.of_node;
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bool internal_cs = true;
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unsigned long flags = GPIOF_DIR_OUT;
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dspi = spi_master_get_devdata(spi->master);
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pdata = &dspi->pdata;
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if (!(spi->mode & SPI_NO_CS)) {
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if ((pdata->chip_sel == NULL) ||
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(pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
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set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
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flags |= (spi->mode & SPI_CS_HIGH) ? GPIOF_INIT_LOW : GPIOF_INIT_HIGH;
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if (!(spi->mode & SPI_NO_CS)) {
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if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
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retval = gpio_request_one(spi->cs_gpio,
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flags, dev_name(&spi->dev));
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internal_cs = false;
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} else if (pdata->chip_sel &&
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spi->chip_select < pdata->num_chipselect &&
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pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
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spi->cs_gpio = pdata->chip_sel[spi->chip_select];
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retval = gpio_request_one(spi->cs_gpio,
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flags, dev_name(&spi->dev));
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internal_cs = false;
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}
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}
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if (retval) {
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dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
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spi->cs_gpio, retval);
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return retval;
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}
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if (internal_cs)
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set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
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if (spi->mode & SPI_READY)
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set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
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@ -414,6 +439,12 @@ static int davinci_spi_setup(struct spi_device *spi)
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return retval;
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}
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static void davinci_spi_cleanup(struct spi_device *spi)
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{
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if (spi->cs_gpio >= 0)
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gpio_free(spi->cs_gpio);
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}
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static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
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{
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struct device *sdev = dspi->bitbang.master->dev.parent;
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@ -812,6 +843,8 @@ static int spi_davinci_get_pdata(struct platform_device *pdev,
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/*
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* default num_cs is 1 and all chipsel are internal to the chip
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* indicated by chip_sel being NULL or cs_gpios being NULL or
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* set to -ENOENT. num-cs includes internal as well as gpios.
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* indicated by chip_sel being NULL. GPIO based CS is not
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* supported yet in DT bindings.
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*/
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@ -850,7 +883,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
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struct resource *r;
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resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
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resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
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int i = 0, ret = 0;
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int ret = 0;
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u32 spipc0;
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master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
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@ -876,6 +909,14 @@ static int davinci_spi_probe(struct platform_device *pdev)
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/* pdata in dspi is now updated and point pdata to that */
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pdata = &dspi->pdata;
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dspi->bytes_per_word = devm_kzalloc(&pdev->dev,
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sizeof(*dspi->bytes_per_word) *
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pdata->num_chipselect, GFP_KERNEL);
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if (dspi->bytes_per_word == NULL) {
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ret = -ENOMEM;
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goto free_master;
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (r == NULL) {
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ret = -ENOENT;
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@ -915,6 +956,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
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master->num_chipselect = pdata->num_chipselect;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
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master->setup = davinci_spi_setup;
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master->cleanup = davinci_spi_cleanup;
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dspi->bitbang.chipselect = davinci_spi_chipselect;
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dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
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@ -962,14 +1004,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
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spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
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iowrite32(spipc0, dspi->base + SPIPC0);
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/* initialize chip selects */
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if (pdata->chip_sel) {
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for (i = 0; i < pdata->num_chipselect; i++) {
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if (pdata->chip_sel[i] != SPI_INTERN_CS)
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gpio_direction_output(pdata->chip_sel[i], 1);
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}
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}
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if (pdata->intr_line)
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iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
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else
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@ -425,8 +425,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
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master->unprepare_transfer_hardware = falcon_sflash_unprepare_xfer;
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master->dev.of_node = pdev->dev.of_node;
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platform_set_drvdata(pdev, priv);
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret)
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spi_master_put(master);
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@ -58,7 +58,7 @@ static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
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.type = TYPE_GRLIB,
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};
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static struct of_device_id of_fsl_spi_match[] = {
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static const struct of_device_id of_fsl_spi_match[] = {
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{
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.compatible = "fsl,spi",
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.data = &of_fsl_spi_fsl_config,
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@ -420,8 +420,6 @@ static int omap1_spi100k_probe(struct platform_device *pdev)
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master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
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master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
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platform_set_drvdata(pdev, master);
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spi100k = spi_master_get_devdata(master);
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/*
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@ -304,7 +304,7 @@ static int hspi_remove(struct platform_device *pdev)
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return 0;
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}
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static struct of_device_id hspi_of_match[] = {
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static const struct of_device_id hspi_of_match[] = {
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{ .compatible = "renesas,hspi", },
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{ /* sentinel */ }
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};
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@ -680,8 +680,6 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
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p = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, p);
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of_id = of_match_device(sh_msiof_match, &pdev->dev);
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if (of_id) {
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p->chipdata = of_id->data;
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